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74181 ALU Design and Verification Guide

1. The document describes developing a Verilog code for a 4-bit ALU using the 74181 IC and verifying its functionality through simulation and testing the actual IC. 2. The Verilog code models the 74181 IC as modules to perform the 16 possible Boolean functions on 4-bit inputs A and B based on a function select line. 3. The ALU design was simulated and the 74181 IC was tested against a truth table, verifying the functionality of both the Verilog model and the physical IC.

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SunilKumarReddy
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36 views3 pages

74181 ALU Design and Verification Guide

1. The document describes developing a Verilog code for a 4-bit ALU using the 74181 IC and verifying its functionality through simulation and testing the actual IC. 2. The Verilog code models the 74181 IC as modules to perform the 16 possible Boolean functions on 4-bit inputs A and B based on a function select line. 3. The ALU design was simulated and the 74181 IC was tested against a truth table, verifying the functionality of both the Verilog model and the physical IC.

Uploaded by

SunilKumarReddy
Copyright
© All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Exp: 8 ALU DESIGN 74181 Date:

AIM:

1. To develope source code for 4-bit ALU by using verilog code and obtain
simulation and synthesis report.

2. To verify the functionality of 74LS181 IC.

APPARATUS: SOFTWARE: 1. COMPUTER

2. XILINX TOOL

HARDWARE: 74LS181 - 1

THEORY:

The 74181 can be modeled as above. Recognizing the logic that makes up a CLA block in
this case, the circled elements in the gate-level schematic is the key step in unraveling the
secrets of the 74181. The four boxed circuits in the gate-level schematic are represented above
by the single module M1 with 4-bit I/O buses. The second quadruplicated circuit in the 74181
leads to the high-level module M2. The various XOR gates are also grouped into 4-bit word
gates as indicated above. Further analysis shows that the 74181 original designers cleverly
constructed the M1 and M2 logic so that with input line M = 1, each setting of the S (function
select) bus produces one of the 16 possible Boolean functions of the form F(A,B). The M line
above has been logically moved from within the CLA block M3, to after the block. This was done
to make module M3 a standard CLA block. The change preserves the function, but does make
subtle differences when analyzing, for example, path delays in the two circuits.

PROCEDURE: HARDWARE:
1. Connect the circuit as shown in the figure.
2. Check the functionality of IC w.r.t function table.
SOFTWARE:
1. Write the verilog program in Xilinx software.
2. Check the syntax.
3. Generate synthesis report & simulations.
4. Check the verilog program functionality w.r.t simulation and function table.

30 | P a g e
Pin Diagram:

Logic Diagram:

31 | P a g e
Verilog Code:

///ALU: Behavioural model

module alu (s,a,b,f);


input [3:0] a,

input [3:0] b,

output [3:0] f;

always@(s, a, b)

case(s)

0: f= 4'b0000;

1: f= b-a;

2: f= a-b;

3: f= a+b;

4: f= a^b;

5: f=a|b;

6: f=a&b;

7: f= 4'b1111;

endcase

endmodule

RESULT:

The hardware and software for 74181 ALU has been simulated and verified successfully.

32 | P a g e

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