Chapter 6

Combinational-Circuit
Building Blocks
Commonly used combinational building
blocks in design of large circuits:
Multiplexers
Decoders
Encoders
Comparators
Arithmetic circuits

Multiplexers
A multiplexer (mux) has a number of data inputs, one or more select
inputs, and one output.
It selects and passes the signal value on one of the data inputs to
the output.
w0
s
s f
w0 0 s f
f 0 w0
w1 1
1 w1
w1

(a) Graphical symbol (b) Truth table (c) Sum-of-products circuit

Figure 6.1. A 2-to-1 multiplexer.

Chapter 6-2
 Multiplexers
s0
s1 s1 s0 f
w0 00 0 0 w0
w1 01 w1
f 0 1
w2 10 w2
1 0
w3 11
1 1 w3

(a) Graphic symbol (b) Truth table

s0
w0
s1

w1

w2

w3

(c) Circuit
Chapter 6-3
Figure 6.2. A 4-to-1 multiplexer.

Multiplexers
Larger muxes could be constructed using smaller ones.
s0
s1
s1 w0
s0
w3

w0 0 w4 s2
w1 1
s3
w7
0
f f
1
w8
w2 0
w11
w3 1

w12
Figure 6.3. Using three 2-to-1 multiplexers to
build a 4-to-1 multiplexer. w15
Figure 6.4. A 16-to-1 multiplexer using five
4-to-1 muxes Chapter 6-4
 Multiplexers
Refer to Fig 6.5 and 6.6 for practical application of muxes in implementation
of crossbars and programmable switches in FPGAs.
General-purpose chips exist that contain muxes as their logic resources.
Actel Corp and QuickLogic Corp offer FPGAs in which the logic block
comprises muxes. TI offers gate array chips with mux based logic blocks.
Muxes can also be used in a more general way to synthesize logic functions.

w1 w2 f
w2 w1 f
w1 w2 f
w1 0 0 0 w2
0
0 0 0 0 1 1
0 1 w2
0 1 1 1 0 1
1
1 0 1 f 1 1 0
1
1 1 0 0
(b) Modified truth table
w1
(a) Implementation using a 4-to-1 mux

w2
f
Figure 6.7. Synthesis of an XOR gate
using a mux
(c) Efficient implementation usingChapter
2-to-1 mux
6-5

w1 w2 w3 f
w1 w2 f
0 0 0 0
0 0 0
0 0 1 0 w3
0 1
0 1 0 0 1 0 w3
0 1 1 1 1 1 1
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 1

(a) Original and modified truth tables

w2
w1

0
w3
f
1
(b) Circuit

Figure 6.8. Implementation of the three-input majority function

using a 4-to-1 multiplexer. Chapter 6-6
w1 w2 w3 f

0 0 0 0
0 0 1 1 w2
w2 w3
0 1 0 1 w1
0 1 1 0 w3
1 0 0 1 f
1 0 1 0
w2 w3
1 1 0 0
1 1 1 1

(a) Truth table (b) Circuit

Figure 6.9. Three-input XOR implemented with

2-to-1 multiplexers.

Chapter 6-7

w1 w2 w3 f

0 0 0 0
w3
0 0 1 1 w2
w1
0 1 0 1
w3
0 1 1 0 w3
1 0 0 1 f
w3
1 0 1 0
1 1 0 0
w3
1 1 1 1

(a) Truth table (b) Circuit

Figure 6.10. Three-input XOR function implemented with

a 4-to-1 multiplexer.

Chapter 6-8
 Shannons Expansion for synthesis
using muxes
Allows functions to be synthesized using combination of muxes and
other logic gates.
Shannons Expansion theorem allows any Boolean function f to be
written in the form:
f(w1, w2, . . . , wn) = w1 f(0, w2, . . . , wn) + w1 f(1, w2, . . . , wn)

Example: Shannon expansion of the majority function in terms of w1

f(w1, w2, w3) = w1w2 + w1w3 + w2w3 = w1(w2w3) + w1(w2+w3)
w1 w2 w3 f
w1
0 0 0 0 w1 f w2
0 0 1 0 w2w3 w3
0
0 1 0 0 1 w2 + w3 f
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 1 Figure 6.11. The three-input majority function implemented
using a 2-to-1 multiplexer. Chapter 6-9

Shannons Expansion for synthesis

using muxes
w1
Shannon Expansion can be done
in terms of more than one
variable. f
w3
If it is done on two variables the
w2
resulting expression could be
implemented using a 4-to-1 mux.
(a) Using a 2-to-1 multiplexer
Note that if Shannon Expansion is
done in terms of all n variables,
then the result is the canonical w2
SOP of the function. w1
w2 w1 w3
f
0
w3 1
f
(b) Using a 4-to-1 multiplexer
1 Figure 6.12. Synthesis of
Figure 6.13. Three input majority f = w1w3 + w1w2 + w1w3
function using only 2-to-1 muxes Chapter 6-10
 Decoders
Decoders are used to decode encoded information.
A binary decoder has n inputs and 2n outputs. Only one of the output
lines is asserted at a time, and each output corresponds to one
valuation of the inputs.
A decoder also typically has an enable input, En, that is used to
enable or disable the output.
If En is deasserted (En = 0) none of the decoder outputs is asserted.
If En is asserted (En = 1) the valuation wn-1wn-2w1w0 determines
which of the output is asserted.
An n-bit binary code in which exactly one of the bits is set to 1 at a
time is called one-hot encoded.
The outputs of a binary decoder are one-hot encoded.
A decoder can be designed to have active-high or active-low
outputs.

Chapter 6-11

w0 y0
n
inputs 2n
wn 1 outputs
y2n 1
Enable En

Figure 6.15. An n-to-2n binary decoder.

w0
y0
w1
En w1 w0 y0 y1 y2 y3
y1
1 0 0 1 0 0 0 w0 y0
1 0 1 0 1 0 0 w1 y1
1 1 0 0 0 1 0
y2 y2
1 1 1 0 0 0 1
En y3
0 x x 0 0 0 0

y3
(a) Truth table (b) Graphical symbol
En
(c) Logic circuit

Figure 6.16. A 2-to-4 decoder. Chapter 6-12

 Decoders
w0 w0 y0 y0
w1 w1 y1 y1
y2 y2
w0 w0 y0 y0 En y3 y3
w1 w1 y1 y1
y2 y2 w0 y0 y4
w2 y3 w1 y1 y5
En y3
y2 y6
w2 w0 y0 En y3 y7
w3 w1 y1
En w0 y0 y4 y2
w1 y1 y5 En En y3 w0 y0 y8
w1 y1 y9
y2 y6 y2 y10
En y3 y7 En y3 y11

Figure 6.17. A 3-to-8 decoder using two w0 y0 y12

2-to-4 decoders. w1 y1 y13
y2 y14
En y3 y15

Figure 6.18. A 4-to-16 decoder built using

a decoder tree. Chapter 6-13

Decoders
Building a multiplexer using a decoder

w0
w0

w1 s0
s0 w0 y0 w0 y0 w1
s1 s1 w1 y1
w1 y1 f f
y2 w2 y2
1 y3 1 En y3
En w2

w3
w3

Figure 6.19. A 4-to-1 multiplexer built Figure 6.20. A 4-to-1 multiplexer built using
using a decoder. a decoder and tri-state buffers.

Chapter 6-14
 Decoders
One of the most important applications of decoders is for address decoding.
The location of each row of memory cells is identified by its address.
The first row has address 0 and the last row has address 2m-1, where m is the number of input
signals used for addressing.
Information stored in a row of memory cells can be accessed by asserting the corresponding
select lines.
A decoder with m inputs and 2m outputs is used to generate the select signals.
Sel 0
0/1 0/1 0/1
Sel 1

m -to-2m decoder
0/1 0/1 0/1
a0 Sel 2
a1 0/1 0/1 0/1
Address
am 1

Sel 2m 1
0/1 0/1 0/1

Read
Figure 6.21. A 2m x n read-only
memory (ROM) block. Data dn 1 dn 2 d0
Chapter 6-15

Demultiplexers
A demultiplexer (demux) circuit performs the opposite of a mux, i.e.
switching the value of a single data input onto one of multiple data
output lines.
An n-to-2n decoder can be used as a 1-to-2n demux.
However, in practice decoder circuits are used more often as
decoders than as demuxes.
w0
Example: a 2-to-4 decoder can be used y0
as a 1-to-4 data demultiplexer. w1
In this case the En input serves as the
y1
data input for the demux, and the y0 to y3
outputs are the data outputs.
The valuation of w1w0 determines which y2
of the outputs is set to the value of En.

y3

En

Chapter 6-16
 Encoders
An encoder performs the opposite function of a decoder. Often it is
used to encode a given information into a more compact form.
A binary encoder encodes data from 2n inputs into an n-bit code.
Exactly one of the input lines should have a value of 1, i.e. the input
should be one-hot encoded data. The outputs present the binary
number that identifies which input is 1.
In binary encoders, all input patterns that have multiple 1s are not
legal input code and hence are treated as dont-care conditions.
Encoders are used to reduce the number of bits needed to represent
given information, for example:
Helps reduce number of wires in a transmission link
Helps reduce number of bits in data storage

Chapter 6-17

Encoders
w3 w2 w1 w0 y1 y0

0 0 0 1 0 0
w0
y0 0 0 1 0 0 1
0 1 0 0 1 0
2n n 1 0 0 0 1 1
inputs outputs
yn 1 (a) Truth table
w2n 1
w0

Figure 6.22. A 2n-to-n binary encoder. w1

y0

w2

w3 y1

(b) Circuit

Figure 6.23. A 4-to-2 binary encoder.

Chapter 6-18
 Priority Encoders
In a priority encoder each input has a priority level associated with it.
The encoder output indicates the active input that has the highest
priority.
When an input with a high priority is asserted, the other inputs with
lower priority are ignored.
Example: In the 4-to-2 priority encoder truth table (Fig 6.24) we assume
w0 has the lowest priority and w3 has the highest priority.
The outputs y1 and y0 represent the binary number that identifies the
highest priority input set to 1.
Since it is possible that all of the inputs could be left de-asserted (i.e.
equal to 0), an output z is provided to indicate this condition.
z is set to 1 when at least one of the inputs is equal to 1. It is set to 0
when all inputs are equal to 0.
When z = 0, the outputs y1 and y0 are meaningless (dont cares).

Chapter 6-19

Priority Encoders
A logical circuit that implements the truth table can
be synthesized by using the techniques studied
earlier.
A more convenient way is to define a set of w3 w2 w1 w0 y1 y0 z
intermediate signals, i0, , i3, such that each
signal ik is equal to 1 only if the input with the 0 0 0 0 d d 0
same index, wk, represents the highest-priority 0 0 0 1 0 0 1
input that is set to 1. 0 0 1 x 0 1 1
0 1 x x 1 0 1
Thus, i0 = w3w2w1w0
1 x x x 1 1 1
i1 = w3w2w1
Figure 6.24. Truth table for a 4-to-2
i2 = w3w2 priority encoder.
i3 = w3

Using the intermediate signals, the circuit for the

priority encoder will have the same structure as
the binary encoder in Fig 6.23 with
y0 = i1 + i3
y1 = i2 + i3
and z = i0 + i1 + i2 + i3
Chapter 6-20
 BCD-to-7-segment code converter
Converts binary-coded-decimal (BCD) code into signals suitable for
driving seven-segment displays.
For each valuation of inputs w3, , w0, the seven outputs are set to
display the appropriate BCD digit. (see below)
Note that the last 6 rows of the truth table are left as dont cares as
they dont correspond to legal BCD codes.
w3 w2 w1 w0 a b c d e f g

a a 0 0 0 0 1 1 1 1 1 1 0
b 0 0 0 1 0 1 1 0 0 0 0
w0 f b 0 0 1 0 1 1 0
c 1 1 0 1
w1 0 0 1 1 1 1 1
d g 1 0 0 1
w2 e c
e 0 1 0 0 0 1 1 0 0 1 1
w3
f 0 1 0 1 1 0 1 1 0 1 1
g d 0 1 1 0 1 0 1 1 1 1 1
0 1 1 1 1 1 1 0 0 0 0
(a) Code converter (b) 7-segment display 1 0 0 0 1 1 1 1 1 1 1
1 0 0 1 1 1 1 1 0 1 1

(c) Truth table

Figure 6.25. A BCD-to-7-segment display code converter. Chapter 6-21

Arithmetic Comparison Circuits

A comparator compares the relative sizes of two numbers.
Consider a comparator that has two n-bit inputs, A and B, which
represent unsigned binary numbers. It produces three outputs:

AeqB which is set to 1 if A = B

AgtB which is set to 1 if A > B

AltB which is set to 1 if A < B
The desired comparator can be designed by creating a truth table that
specifies the three outputs as a function of A and B.
However, even for moderate values of n, the truth table is large.
Alternatively, Let n = 4, A = a3a2a1a0 and B = b3b2b1b0
Define intermediate signals i3, i2, i1,,and i0. Each signal ik is 1 if the bits of
A and B with the same index are equal, i.e. ik = ak bk
Thus, the comparator outputs are given by:
AeqB = i3i2i1i0
AgtB = a3b3 + i3a2b2 + i3i2a1b1 + i3i2i1a0b0
AtlB = AeqB + AgtB
Chapter 6-22
 a3 i3
b3

a2 i2
b2
AeqB
a1 i1
b1

a0 i0
b0
AltB

AgtB

Figure 6.26. A four-bit comparator circuit. Chapter 6-23

Full Adder
c i x i yi c i +1 si
xi yi xi yi
0 0 0 0 0 ci 00 01 11 10 ci 00 01 11 10
0 0 1 0 1
0 1 0 0 1 0 1 1 0 1
0 1 1 1 0
1 1 1 1 1 1 1
1 0 0 0 1
1 0 1 1 0 si = xi yi ci ci + 1 = xi yi + xi ci + yi ci
1 1 0 1 0
1 1 1 1 1

ci s si
xi s HA c
yi
xi
si HA c ci +1
yi
ci

ci
si
xi
ci +1 yi
ci +1

Figure 5.4. Full-adder. Figure 5.5. A decomposed implementation of

the full-adder circuit. Chapter 6-24
 Ripple-Carry Adder
Cascade n full-adders using the carry signals to implement an n-bit
adder.
The carry bit propagates from lower to higher significant adder units.
Each adder introduces a time delay, say t, before its si and ci+1
outputs are valid.
The delay for the complete sum and carry out to be available is nt.
The circuit is called ripple-carry adder because of the way the carry
signals ripple through the full adder stages.
xn 1 yn 1 x1 y1 x0 y0

c1
cn cn-1 c c
FA 2 FA FA 0

sn 1 s1 s0
MSB position LSB position

Figure 5.6. An n-bit ripple-carry adder.

Chapter 6-25

n-bit Adder Application Example

Build a circuit that multiplies an eight-bit unsigned number by 3.
Let, A = a7a6a1a0 denote the number and P = p0p1p1p0 denote the
product P = 3A. Note that 10 bits are needed to represent the product.
A : a7 a0

x7 x0 y7 y0 A : a7 a0
c7
s7 s0

0 0
0
x8 x1 x0 y8 y7 y0
x8 x7 x0 y8 y7 y0 c8
c8 s8 s0
s8 s0

P = 3 A : P9 P8 P0
P = 3 A : P9 P8 P0

(a) Naive approach (b) Efficient design

Figure 5.7. Circuit that multiplies an eight-bit unsigned number by 3.

Chapter 6-26
 Adder/Subtractor Unit
yn 1 y1 y0
Add Sub
control

xn 1 x1 x0

cn n -bit adder c0

sn 1 s1 s0

Figure 5.13. Adder/subtractor unit.

If we assume that the n-bit adder is a ripple-carry adder, what is the worst
case propagation delay?
The delay for cout signal in a full adder is 2 gate delays.
For n-bit full adder the total delay is thus nt = 2n gate delays.
If we assume the delay contribution by the XOR gates at the inputs to be
about one gate delay, the total worst case delay would be 2n+1 gate delays
Chapter 6-27

Carry-Lookahead Adder
To reduce the delay caused by the effect of carry propagation
through the ripple-carry adder, for each stage we can attempt to
evaluate on the spot whether the carry-in from the previous stage
will have a value of 1 or 0.
So this scheme will avoid the waiting of carries to ripple through the
cascade network as it is the case in the ripple-carry adder.
The carry-out function for stage i can be realized as:
ci+1 = xiyi + xici + yici
ci+1 = xiyi + (xi + yi)ci
ci+1 = gi + pici
where generate (gi) and propagate (pi) functions are defined as:
gi = xiyi
pi = xi + yi
Thus, gi is 1 when both xi and yi are equal, regardless of the value of
the incoming carry ci to this stage.
The effect of pi is, if it is equal to 1 then a carry-in of ci = 1 will be
propagated through stage i.
Chapter 6-28
 Carry-Lookahead Adder
Expanding ci+1 in terms of ci-1 gives:
ci+1 = gi + pici = gi + pi(gi-1 + pi-1ci-1)
= gi + pigi-1 + pipi-1ci-1
If we continue the expansion until we end with stage 0, we obtain:
ci+1 = gi + pigi-1 + pipi-1gi-2 + . . . + pipi-1p2p1g0 + pipi-1p2p1g0 c0
This expansion represents a 2-level AND-OR realization in which ci+1 is
evaluated very quickly. The adder based on this expansion is called carry-
lookahead adder.
The speed of a circuit is limited by the longest delay along the paths through
the circuit, often referred to as the critical-path delay, and the path that
causes this delay is called the critical path.
The slow speed of ripple-carry adder is due to the long path along which a
carry must propagate (see Fig 5.15). The critical path is from x0 and y0 to c2.
It passes through 5 gates as highlighted in blue. Thus, for an n-bit ripple-
carry adder the total delay along the critical path is 2n+1.
For the carry-lookahead adder (see Fig 5.16), the critical path for producing
c2 is the same as that for c1, it is just 3 gate delays. Extending to n bits, the
final carry-out cn would also be produced after 3 gate delays.
Chapter 6-29

Carry-Lookahead Adder
x1 y1 x0 y0
x1 y1 x0 y0
x0 y0

g p g0 p0
1 1
g1 p1 g0 p0
c1 c0
c2
c0
c
2 c1

Stage 1 Stage 0

s1 s0 s1 s0

Figure 5.15. A ripple-carry adder based on Figure 5.16. The first two stages of a carry-
expression 5.3. lookahead adder.
Chapter 6-30
 Carry-Lookahead Adder
x1 y1 x0 y0

g1 p1 g0 p0

c0
c2
c1

s1 s0

Figure 5.19. An alternative design for a carry-lookahead adder. Chapter 6-31

A hierarchical adder design

The complexity of an n-bit carry-lookahead adder increases rapidly with n.
To reduce the complexity, a hierarchical design is common.
For example, we can build a 32-bit adder by dividing it into four 8-bit adder
blocks each of which are implemented as 8-bit carry-lookahead adder.
The carry-out signals from the four blocks are c8, c16, c24, and c32.
We have two possibilities to connect the four adder blocks:
1. Connect the 4 blocks as 4 stages in ripple-carry adder (Fig. 5.17)
2. Connect using second level carry-lookahead circuits (relies on group level
generate and propagate Pj and Gj produced by each block) (Fig. 5.18)
x31 24 y31 24 x15 8 y15 8 x7 0 y7 0

c8
c32 Block c24 c16 Block Block c0
3 1 0

s31 24 s15 8 s7 0
Figure 5.17. A hierarchical carry-lookahead adder with ripple-carry between blocks.
Chapter 6-32
 A hierarchical adder design
x31 24 y31 24 x15 8 y15 8 x7 0 y7 0

Block Block Block c0

3 c24 1 0
G3 P3 G1 P1 G0 P0

s31 24 s15 8 s7 0

c32 c16 c8

Second-level lookahead

Figure 5.18. A hierarchical carry-lookahead adder.

Chapter 6-33

BCD Addition
Care has to be taken when adding two BCD digits since the sum
may become invalid (i.e. exceed 9).
Let X = x3x2x1x0 and Y = y3y2y1y0 represent two BCD digits and let
S = s3s2s1s0 be the desired sum digit, S = X + Y.
If X + Y 9, then the addition is just like addition of two 4-bit
unsigned numbers.
But, if X + Y > 9, then the result requires two BCD digits, moreover
the 4-bit sum obtained from the 4-bit adder may be incorrect. Thus
in this case a correction needs to be applied to the result.
The necessary correction arises from the fact that 4-bit binary
addition is a modulo-16 scheme, whereas decimal addition is a
modulo-10 scheme.
Therefore, a correct decimal digit can be generated by adding 6 to
the result of the 4-bit addition whenever it exceeds 9.
Z=X+Y
If Z 9, then S = Z and carry-out = 0
if Z > 9, then S = Z + 6 and carry-out = 1
Chapter 6-34
 BCD Addition
X Y x3 x2 x1 x0 y3 y2 y1 y0

c in
4-bit adder Four-bit adder c in
carry-out

z3 z2 z1 z0
Z

Detect if
sum > 9
6 0

MUX
Adjust

Two-bit adder

c out 4-bit adder 0

c out s3 s2 s1 s0
S

Figure 5.36. Block diagram for a Figure 5.38. Circuit for a one-digit BCD adder.
one-digit BCD adder.
Chapter 6-35

Design Using CAD Tools

Schematic capture tools provide a library of graphical symbols that
represent basic logic gates. These gates are used to create
schematics of relatively simple circuits.
Most tools also provide a library of commonly used circuits or
modules, such as adders. Each module can be imported into a
schematic as part of a larger circuit.
In some CAD systems such modules are called macrofunctions or
megafunctions.
Two main types of macrofunctions:
1. Technology-dependent macrofunction designed for specific type of chip
2. Technology-independent macrofunction can be implemented in any type of
chip.
Library of Parameterized Modules (LPM) is included as part of the
Quartus II CAD system.
Each module in the library is technology independent
Each module is parameterized, i.e. it can be used in a variety of ways that can be
configured by using the CAD tools.
Chapter 6-36
 Design Using CAD Tools
Example: The library includes an n-bit adder/subtractor module, named
lpm_add_sub.
Important parameters:
LPM_WIDTH : specifies the number of bits, n, in the adder
LPM_REPRESENTATION : specifies whether to use signed or unsigned integers.
This affects only the way the module determines overflow.

Figure 5.20. Schematic using an LPM adder/subtractor module, with

LPM_WIDTH = 16, and signed representation Chapter 6-37

Design Using CAD Tools

Figure 5.21. Simulation results for the LPM adder.

Chapter 6-38
 n-bit adder in VHDL
Hierarchical design of an n-bit ripple-carry adder using n instances
of full-adders.
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;

ENTITY fulladd IS
PORT ( Cin, x, y : IN STD_LOGIC ;
s, Cout : OUT STD_LOGIC ) ;
END fulladd ;

ARCHITECTURE LogicFunc OF fulladd IS

BEGIN
s <= x XOR y XOR Cin ;
Cout <= (x AND y) OR (Cin AND x) OR (Cin AND y) ;
END LogicFunc ;

Figure 5.22. VHDL code for the full-adder.

Chapter 6-39

n-bit adder in VHDL

LIBRARY ieee ;
USE ieee.std_logic_1164.all ;

ENTITY adder4 IS
PORT ( Cin : IN STD LOGIC ;
x3, x2, x1, x0 : IN STD_LOGIC ;
y3, y2, y1, y0 : IN STD_LOGIC ;
s3, s2, s1, s0 : OUT STD_OGIC ;
Cout : OUT STD_LOGIC ) ;
END adder4 ;
component
declaration
ARCHITECTURE Structure OF adder4 IS
SIGNAL c1, c2, c3 : STD_LOGIC ;
COMPONENT fulladd
PORT ( Cin, x, y : IN STD_LOGIC ;
s, Cout : OUT STD_LOGIC ) ; structural style
component END COMPONENT ; connecting
instantiations BEGIN together sub-
stage0: fulladd PORT MAP ( Cin, x0, y0, s0, c1 ) ; circuits
stage1: fulladd PORT MAP ( c1, x1, y1, s1, c2 ) ;
stage2: fulladd PORT MAP ( c2, x2, y2, s2, c3 ) ;
stage3: fulladd PORT MAP ( positional
Cin => c3, Cout => Cout, x => x3, y => y3, s => s3 ) ; association
END Structure ;
named
Figure 5.23. VHDL code for a four-bit adder. association
Chapter 6-40
 VHDL package
Package allows VHDL constructs to be defined in one source file
and then be used in other source code files.
Data type declarations and component declarations are example
constructs that are often placed in a package.
The package declaration can be stored in a separate file or in the
same source code with designs that use the package.
Example in the fulladd_package below the fulladd component is
declared.
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;

PACKAGE fulladd_package IS
COMPONENT fulladd
PORT ( Cin, x, y : IN STD_LOGIC ;
s, Cout : OUT STD_LOGIC ) ;
END COMPONENT ;
END fulladd_package ;
Figure 5.24. Declaration of a package. Chapter 6-41

Using packages
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
USE work.fulladd_package.all ; X, Y, S defined as
multi-bit signals
ENTITY adder4 IS
PORT ( Cin : IN STD_LOGIC ;
X, Y : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ;
S : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) ;
Cout : OUT STD_LOGIC ) ;
END adder4 ;

ARCHITECTURE Structure OF adder4 IS

SIGNAL C : STD_LOGIC_VECTOR(1 TO 3) ;
BEGIN
stage0: fulladd PORT MAP ( Cin, X(0), Y(0), S(0), C(1) ) ;
stage1: fulladd PORT MAP ( C(1), X(1), Y(1), S(1), C(2) ) ;
stage2: fulladd PORT MAP ( C(2), X(2), Y(2), S(2), C(3) ) ;
stage3: fulladd PORT MAP ( C(3), X(3), Y(3), S(3), Cout ) ;
END Structure ;

Figure 5.26. A four-bit adder defined using multibit signals. Chapter 6-42
 Using the + operator
VHDL provides arithmetic, logical and other operators.
Since std_logic_1164 package does not specify that STD_LOGIC
signals can be used with arithmetic operators, the package named
std_logic_signed with STD_LOGIC_VECTOR signals or
std_logic_arith with SIGNED signals could be used.
When the code is compiled it generates an adder circuit to
implement the + operator. When using the Quartus II CAD system,
the adder used by the compiler is actually lpm_add_sub module.
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
USE ieee.std_logic_signed.all ;

ENTITY adder16 IS
PORT ( X, Y : IN STD_LOGIC_VECTOR(15 DOWNTO 0) ;
S : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) ) ;
END adder16 ;

ARCHITECTURE Behavior OF adder16 IS

BEGIN
S <= X + Y ;
END Behavior ;

Figure 5.27. VHDL code for a 16-bit adder. Chapter 6-43

Adder with carry and overflow

Figure 5.28. The 16-bit adder from Figure 5.27 with carry and overflow signals.

Chapter 6-44
Adder with carry and overflow
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
USE ieee.std_logic_arith.all ;

ENTITY adder16 IS
PORT ( Cin : IN STD_LOGIC ;
X, Y : IN SIGNED(15 DOWNTO 0) ;
S : OUT SIGNED(15 DOWNTO 0) ;
Cout, Overflow : OUT STD_LOGIC ) ;
END adder16 ;

ARCHITECTURE Behavior OF adder16 IS

SIGNAL Sum : SIGNED(16 DOWNTO 0) ;
BEGIN
Sum <= ('0' & X) + Y + Cin ;
S <= Sum(15 DOWNTO 0) ;
Cout <= Sum(16) ;
Overflow <= Sum(16) XOR X(15) XOR Y(15) XOR Sum(15) ;
END Behavior ;

Figure 5.29. Use of the arithmetic package. Chapter 6-45

One-digit BCD Adder

LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
USE ieee.std_logic_unsigned.all ;

ENTITY BCD IS
PORT ( X, Y : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ;
S : OUT STD_LOGIC_VECTOR(4 DOWNTO 0) ) ;
END BCD ;

ARCHITECTURE Behavior OF BCD IS

SIGNAL Z : STD_LOGIC_VECTOR(4 DOWNTO 0) ;
SIGNAL Adjust : STD_LOGIC ;
BEGIN
Z <= ('0' & X) + Y ;
Adjust <= '1' WHEN Z > 9 ELSE '0' ;
S <= Z WHEN (Adjust = '0') ELSE Z + 6 ;
END Behavior ;

Figure 5.37. VHDL code for a one-digit BCD adder.

Chapter 6-46
Comparator design using subtractor
The following circuit shows how the Z, N, and V signals can be used
to determine the comparator outputs: X = Y, X < Y, X Y, X > Y, X Y

Figure 5.42. A comparator circuit.

Chapter 6-47

Comparator design using subtractor

LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
USE work.fulladd_package.all ;

ENTITY comparator IS
PORT ( X, Y : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ;
V, N, Z : OUT STD_LOGIC ) ;
END comparator ;

ARCHITECTURE Structure OF comparator IS

SIGNAL S : STD_LOGIC_VECTOR(3 DOWNTO 0) ;
SIGNAL C : STD_LOGIC_VECTOR(1 TO 4) ;
BEGIN
stage0: fulladd PORT MAP ( '1', X(0), NOT Y(0), S(0), C(1) ) ;
stage1: fulladd PORT MAP ( C(1), X(1), NOT Y(1), S(1), C(2) ) ;
stage2: fulladd PORT MAP ( C(2), X(2), NOT Y(2), S(2), C(3) ) ;
stage3: fulladd PORT MAP ( C(3), X(3), NOT Y(3), S(3), C(4) ) ;
V <= C(4) XOR C(3) ;
N <= S(3) ;
Z <= '1' WHEN S(3 DOWNTO 0) = "0000" ELSE '0';
END Structure ;

Figure 5.43. Structural VHDL code for the comparator circuit.

Chapter 6-48
 Comparator design using subtractor

Figure 5.44. Behavioral VHDL code for the comparator circuit.

Chapter 6-49

Selected Signal Assignment

Selected signal assignment - allows a signal to be assigned one of
several values, based on a selection criteria. It begins with the
construct WITH s SLECT where s is used for a selection criterion.
WHEN clause must be included for every possible value of s.
Keyword OTHERS is a convenient way to account for all logic
values that are not explicitly listed in a WHEN clause.
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;

ENTITY mux2to1 IS
PORT ( w0, w1, s : IN STD_LOGIC ;
f : OUT STD_LOGIC ) ;
END mux2to1 ;

ARCHITECTURE Behavior OF mux2to1 IS

BEGIN
WITH s SELECT
f <= w0 WHEN '0',
w1 WHEN OTHERS ;
END Behavior ;
Chapter 6-50
Figure 6.27. VHDL code for a A 2-to-1 multiplexer.
 4-to-1 MUX in VHDL
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;

ENTITY mux4to1 IS
PORT (w0, w1, w2, w3 : IN STD_LOGIC ;
s : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
f : OUT STD_LOGIC ) ;
END mux4to1 ;

ARCHITECTURE Behavior OF mux4to1 IS

BEGIN
WITH s SELECT
f <= w0 WHEN "00",
w1 WHEN "01",
w2 WHEN "10",
w3 WHEN OTHERS ;
END Behavior ;

Figure 6.28. VHDL code for a 4-to-1 multiplexer (Part a).

LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
PACKAGE mux4to1_package IS
COMPONENT mux4to1
PORT (w0, w1, w2, w3 : IN STD_LOGIC ;
s : IN STD_LOGIC_VECTOR(1 DOWNTO 0) ;
f : OUT STD_LOGIC ) ;
END COMPONENT ;
END mux4to1_package ;

Figure 6.28. VHDL code for a 4-to-1 multiplexer (Part b). Chapter 6-51

Hierarchical 16-to-1 MUX

s0
LIBRARY ieee ; s1
USE ieee.std_logic_1164.all ;
LIBRARY work ; w0
USE work.mux4to1_package.all ;
w3
ENTITY mux16to1 IS
PORT (w : IN STD_LOGIC_VECTOR(0 TO 15) ;
s : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ; w4 s2
f : OUT STD_LOGIC ) ; s3
END mux16to1 ; w7

ARCHITECTURE Structure OF mux16to1 IS f

SIGNAL m : STD_LOGIC_VECTOR(0 TO 3) ; w8
BEGIN
Mux1: mux4to1 PORT MAP ( w(0), w(1), w(2), w(3), s(1 DOWNTO 0), m(0) ) ; w
11
Mux2: mux4to1 PORT MAP ( w(4), w(5), w(6), w(7), s(1 DOWNTO 0), m(1) ) ;
Mux3: mux4to1 PORT MAP ( w(8), w(9), w(10), w(11), s(1 DOWNTO 0), m(2) ) ;
Mux4: mux4to1 PORT MAP ( w(12), w(13), w(14), w(15), s(1 DOWNTO 0), m(3) ) ; w 12
Mux5: mux4to1 PORT MAP ( m(0), m(1), m(2), m(3), s(3 DOWNTO 2), f ) ;
END Structure ;
w15

Figure 6.29. Hierarchical code for a 16-to-1 multiplexer.

Chapter 6-52
 2-to-4 binary decoder
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;

ENTITY dec2to4 IS
PORT ( w : IN STD_LOGIC_VECTOR(1 DOWNTO 0) ;
En : IN STD_LOGIC ;
y : OUT STD_LOGIC_VECTOR(0 TO 3) ) ;
END dec2to4 ;

ARCHITECTURE Behavior OF dec2to4 IS

SIGNAL Enw : STD_LOGIC_VECTOR(2 DOWNTO 0) ;
BEGIN
Enw <= En & w ; -- use VHDL concatenate (&) operator
WITH Enw SELECT
y <= "1000" WHEN "100",
"0100" WHEN "101",
"0010" WHEN "110",
"0001" WHEN "111",
"0000" WHEN OTHERS ; -- i.e for cases when En=0
END Behavior ;

Figure 6.30. VHDL code for a 2-to-4 binary decoder.

Chapter 6-53

Conditional Signal Assignment

Similar to the selected signal assignment, a conditional signal
assignment allows a signal to be set to one of several values.
WHEN ELSE clause is used for conditional signal assignment.
The priority level associated with each WHEN clause in the
conditional signal assignment is a key difference from the selected
signal assignment, which has no such priority.
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;

ENTITY mux2to1 IS
PORT (w0, w1, s : IN STD_LOGIC ;
f : OUT STD_LOGIC ) ;
END mux2to1 ;

ARCHITECTURE Behavior OF mux2to1 IS

BEGIN
f <= w0 WHEN s = '0' ELSE w1 ;
END Behavior ;

Figure 6.31. A 2-to-1 multiplexer using a conditional signal assignment.

Chapter 6-54
 4-to-2 priority encoder
LIBRARY ieee ;
w3 w2 w1 w0 y1 y0 z USE ieee.std_logic_1164.all ;

0 0 0 0 d d 0 ENTITY priority IS
0 0 0 1 0 0 1 PORT ( w : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ;
0 0 1 x 0 1 1 y : OUT STD_LOGIC_VECTOR(1 DOWNTO 0) ;
0 1 x x 1 0 1 z : OUT STD_LOGIC ) ;
1 x x x 1 1 1 END priority ;

ARCHITECTURE Behavior OF priority IS

BEGIN
y <= "11" WHEN w(3) = '1' ELSE
"10" WHEN w(2) = '1' ELSE
"01" WHEN w(1) = '1' ELSE
"00" ;
z <= '0' WHEN w = "0000" ELSE '1' ;
END Behavior ;

Figure 6.32. VHDL code for a priority encoder.

Chapter 6-55

LIBRARY ieee ;
USE ieee.std_logic_1164.all ;

ENTITY priority IS
PORT ( w : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ;
y : OUT STD_LOGIC_VECTOR(1 DOWNTO 0) ;
z : OUT STD_LOGIC ) ;
END priority ;

ARCHITECTURE Behavior OF priority IS

BEGIN
WITH w SELECT
y <= "00" WHEN "0001",
"01" WHEN "0010",
"01" WHEN "0011",
"10" WHEN "0100",
"10" WHEN "0101",
"10" WHEN "0110",
"10" WHEN "0111",
"11" WHEN OTHERS ;
WITH w SELECT
z <= '0' WHEN "0000",
'1' WHEN OTHERS ;
END Behavior ;
Figure 6.33. Less efficient code for a priority encoder. Chapter 6-56
 Comparator using relational operator
Use the package named std_logic_unsigned to allow the use of
relational operators on UNSIGNED binary numbers.
Alternately, we can use the package named std_logic_arith for
both UNSIGNED and SIGNED data types.
The VHDL compiler instantiates a predefined module to implement
each of the comparison operations.
LIBRARY ieee ; LIBRARY ieee ;
USE ieee.std_logic_1164.all ; USE ieee.std_logic_1164.all ;
USE ieee.std_logic_unsigned.all ; USE ieee.std_logic_arith.all ;

ENTITY compare IS ENTITY compare IS

PORT (A, B : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ; PORT (A, B : IN SIGNED(3 DOWNTO 0) ;
AeqB, AgtB, AltB : OUT STD_LOGIC ) ; AeqB, AgtB, AltB : OUT STD_LOGIC ) ;
END compare ; END compare ;

ARCHITECTURE Behavior OF compare IS ARCHITECTURE Behavior OF compare IS

BEGIN BEGIN
AeqB <= '1' WHEN A = B ELSE '0' ; AeqB <= '1' WHEN A = B ELSE '0' ;
AgtB <= '1' WHEN A > B ELSE '0' ; AgtB <= '1' WHEN A > B ELSE '0' ;
AltB <= '1' WHEN A < B ELSE '0' ; AltB <= '1' WHEN A < B ELSE '0' ;
END Behavior ; END Behavior ;

Figure 6.34. VHDL code for a four-bit Figure 6.35. The code from Figure 6.34 for
comparator. signed [Link] 6-57

Generate Statements
VHDL provides the FOR GENERATE and IF GENERATE
statements for describing regularly structured hierarchical code.
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
USE work.mux4to1_package.all ;

ENTITY mux16to1 IS
PORT ( w : IN STD_LOGIC_VECTOR(0 TO 15) ;
s : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ;
f : OUT STD_LOGIC ) ;
END mux16to1 ;

ARCHITECTURE Structure OF mux16to1 IS

SIGNAL m : STD_LOGIC_VECTOR(0 TO 3) ;
BEGIN
G1: FOR i IN 0 TO 3 GENERATE
Muxes: mux4to1 PORT MAP (
w(4*i), w(4*i+1), w(4*i+2), w(4*i+3), s(1 DOWNTO 0), m(i) ) ;
END GENERATE ;
Mux5: mux4to1 PORT MAP ( m(0), m(1), m(2), m(3), s(3 DOWNTO 2), f ) ;
END Structure ;
Figure 6.36. Code for a 16-to-1 multiplexer using a generate statement. Chapter 6-58
 LIBRARY ieee ;
USE ieee.std_logic_1164.all ;

ENTITY dec4to16 IS
PORT ( w : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ;
En : IN STD_LOGIC ;
y : OUT STD_LOGIC_VECTOR(0 TO 15) ) ;
END dec4to16 ;

ARCHITECTURE Structure OF dec4to16 IS

COMPONENT dec2to4
PORT ( w : IN STD_LOGIC_VECTOR(1 DOWNTO 0) ;
En : IN STD_LOGIC ;
y : OUT STD_LOGIC_VECTOR(0 TO 3) ) ;
END COMPONENT ;
SIGNAL m : STD_LOGIC_VECTOR(0 TO 3) ;
BEGIN
G1: FOR i IN 0 TO 3 GENERATE
Dec_ri: dec2to4 PORT MAP ( w(1 DOWNTO 0), m(i), y(4*i TO 4*i+3) );
G2: IF i=3 GENERATE
Dec_left: dec2to4 PORT MAP ( w(i DOWNTO i-1), En, m ) ;
END GENERATE ;
END GENERATE ;
END Structure ;
Figure 6.37. Hierarchical code for a 4-to-16 binary decoder (see Fig 6.18 and 6.30)
Chapter 6-59

Concurrent vs. Sequential

Assignment Statements
Concurrent assignment statements has the property that the order in which they
appear in VHDL code does not affect the meaning of the code. Examples of such
statements:
Simple assignment statements (for logic or arithmetic expressions)
Selected assignment statements
Conditional assignment statements
Sequential assignment statements the ordering of the statements may affect the
meaning of the code. Examples:
IF THEN ELSE statement
CASE statement
VHDL requires that sequential assignment statements be placed inside process
statement, that begins with the PROCESS keyword followed by a parenthesized list
of signals, called sensitivity list.
For a combinational circuit the sensitivity list includes all input signals that are used inside the
process.
When there is a change in the value of any signal in the processs sensitivity list the process
becomes active. Once active the statements inside the process are evaluated in sequential
order.
Any assignment made to signals inside the process are not visible outside the process until
all of statements in the process have been evaluated.
If there are multiple assignments to the same signal, only the last one has any visible effect.
While statements in a process are sequential, the process statement itself is a concurrent
statement.
A process statement is translated by the VHDL compiler into logic equations.

Chapter 6-60
 2-to-1 MUX using ifthenelse
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;

ENTITY mux2to1 IS
PORT ( w0, w1, s : IN STD_LOGIC ;
f : OUT STD_LOGIC ) ;
END mux2to1 ;

ARCHITECTURE Behavior OF mux2to1 IS

BEGIN
PROCESS ( w0, w1, s )
BEGIN
IF s = '0' THEN
f <= w0 ;
ELSE
f <= w1 ;
END IF ;
END PROCESS ;
END Behavior ;
Figure 6.38. A 2-to-1 multiplexer specified using an if-then-else statement Chapter 6-61

LIBRARY ieee ;
USE ieee.std_logic_1164.all ;

ENTITY mux2to1 IS
PORT ( w0, w1, s : IN STD_LOGIC ;
f : OUT STD_LOGIC ) ;
END mux2to1 ;

ARCHITECTURE Behavior OF mux2to1 IS

BEGIN
PROCESS ( w0, w1, s ) Actual assignment for f
is scheduled to occur
BEGIN after all of the assignments
f <= w0 ; -- assign default value for f in the process have been
IF s = '1' THEN evaluated.
f <= w1 ;
END IF ;
END PROCESS ;
END Behavior ;

Figure 6.39. Alternative code for a 2-to-1 multiplexer using an if-then-else statement.

Chapter 6-62
Priority encoder using ifthenelse
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY priority IS
PORT (w : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ;
y : OUT STD_LOGIC_VECTOR(1 DOWNTO 0) ;
z : OUT STD_LOGIC ) ;
END priority ;

ARCHITECTURE Behavior OF priority IS

BEGIN
PROCESS ( w )
BEGIN
IF w(3) = '1' THEN
y <= "11" ;
ELSIF w(2) = '1' THEN
y <= "10" ;
ELSIF w(1) = '1' THEN
y <= "01" ; VHDL syntax does not allow
ELSE conditional assignment
y <= "00" ; statement or selected
END IF ; assignment statement to
END PROCESS ; appear inside a process.
z <= '0' WHEN w = "0000" ELSE '1' ;
END Behavior ;

Figure 6.40. A priority encoder specified using the if-then-else statement. Chapter 6-63

LIBRARY ieee ;
USE ieee.std_logic_1164.all ;

ENTITY priority IS
PORT ( w : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ;
y : OUT STD_LOGIC_VECTOR(1 DOWNTO 0) ;
z : OUT STD_LOGIC ) ;
END priority ;

ARCHITECTURE Behavior OF priority IS

BEGIN
PROCESS ( w )
BEGIN
y <= "00" ;
IF w(1) = '1' THEN y <= "01" ; END IF ;
IF w(2) = '1' THEN y <= "10" ; END IF ;
IF w(3) = '1' THEN y <= "11" ; END IF ;

z <= '1' ;
IF w = "0000" THEN z <= '0' ; END IF ;
END PROCESS ;
END Behavior ;

Figure 6.41. Alternative code for the priority encoder.

Chapter 6-64
 1-bit equality comparator
LIBRARY ieee ; LIBRARY ieee ;
USE ieee.std_logic_1164.all ; USE ieee.std_logic_1164.all ;

ENTITY compare1 IS ENTITY implied IS

PORT (A, B : IN STD_LOGIC ; PORT (A, B : IN STD_LOGIC ;
AeqB : OUT STD_LOGIC ) ; AeqB : OUT STD_LOGIC ) ;
END compare1 ; END implied ;

ARCHITECTURE Behavior OF compare1 IS ARCHITECTURE Behavior OF implied IS

BEGIN BEGIN
PROCESS ( A, B ) PROCESS ( A, B )
BEGIN BEGIN
AeqB <= '0' ; -- AeqB <= '0' ; --taken out
IF A = B THEN IF A = B THEN
AeqB <= '1' ; AeqB <= '1' ;
END IF ; END IF ;
END PROCESS ; END PROCESS ;
END Behavior ; END Behavior ;

Figure 6.42. Code for a one-bit equality comparator. Figure 6.43. An example of code that results in implied memory.

A
VHDL semantics stipulate that in cases B AeqB
where the code does not specify the value
of a signal, the signal should retain its
current value Figure 6.44. The circuit generated from the codeChapter
in Figure 6.43.
6-65

CASE Statement
The case statement is similar to a selected signal assignment in that it has a
selection signal and includes WHEN clauses for various valuations of this selection
signal.
The case statement must include a WHEN clause for all possible valuations of the
selection signal.
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;

ENTITY mux2to1 IS
PORT (w0, w1, s : IN STD_LOGIC ;
f : OUT STD_LOGIC ) ;
END mux2to1 ;

ARCHITECTURE Behavior OF mux2to1 IS

BEGIN
PROCESS ( w0, w1, s )
BEGIN
CASE s IS
WHEN '0' =>
f <= w0 ;
WHEN OTHERS =>
f <= w1 ;
END CASE ;
END PROCESS ;
END Behavior ;
Chapter 6-66
Figure 6.45. A case statement that represents a 2-to-1 multiplexer.
 Process for 2-to-4 binary decoder
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY dec2to4 IS
PORT ( w : IN STD_LOGIC_VECTOR(1 DOWNTO 0) ;
En : IN STD_LOGIC ;
y : OUT STD_LOGIC_VECTOR(0 TO 3) ) ;
END dec2to4 ;

ARCHITECTURE Behavior OF dec2to4 IS

BEGIN
PROCESS ( w, En )
BEGIN
IF En = '1' THEN
CASE w IS
WHEN "00" => y <= "1000" ;
WHEN "01" => y <= "0100" ;
WHEN "10" => y <= "0010" ;
WHEN OTHERS => y <= "0001" ;
END CASE ;
ELSE
y <= "0000" ;
END IF ;
END PROCESS ;
END Behavior ;

Figure 6.46. A process statement that describes a 2-to-4 binary decoder. Chapter 6-67

BCD-to7-segment decoder
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
a a ENTITY seg7 IS
w0 b
PORT (bcd : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ;
w1 c f b
d leds : OUT STD_LOGIC_VECTOR(1 TO 7) ) ;
w2 g END seg7 ;
e e c
w3 f ARCHITECTURE Behavior OF seg7 IS
g d BEGIN
PROCESS ( bcd )
BEGIN
w3 w2 w1 w0 a b c d e f g CASE bcd IS -- abcdefg
WHEN "0000" => leds <= "1111110" ;
0 0 0 0 1 1 1 1 1 1 0 WHEN "0001" => leds <= "0110000" ;
0 0 0 1 0 1 1 0 0 0 0 WHEN "0010" => leds <= "1101101" ;
0 0 1 0 1 1 0 1 1 0 1 WHEN "0011" => leds <= "1111001" ;
0 0 1 1 1 1 1 1 0 0 1 WHEN "0100" => leds <= "0110011" ;
0 1 0 0 0 1 1 0 0 1 1 WHEN "0101" => leds <= "1011011" ;
0 1 0 1 1 0 1 1 0 1 1 WHEN "0110" => leds <= "1011111" ;
0 1 1 0 1 0 1 1 1 1 1 WHEN "0111" => leds <= "1110000" ;
0 1 1 1 1 1 1 0 0 0 0 WHEN "1000" => leds <= "1111111" ;
1 0 0 0 1 1 1 1 1 1 1 WHEN "1001" => leds <= "1110011" ;
1 0 0 1 1 1 1 1 0 1 1 WHEN OTHERS => leds <= "-------" ;
END CASE ;
Figure 6.25. A BCD-to-7-segment END PROCESS ;
display code converter. END Behavior ;
Chapterdecoder
Figure 6.47. Code that represents a BCD-to-7-segment 6-68
 Arithmetic Logic Unit (ALU)
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
USE ieee.std_logic_unsigned.all ;
ENTITY alu IS
PORT ( s : IN STD_LOGIC_VECTOR(2 DOWNTO 0) ;
A, B : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ;
F : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) ) ;
END alu ;

ARCHITECTURE Behavior OF alu IS

BEGIN
PROCESS ( s, A, B )
BEGIN
CASE s IS
WHEN "000" =>
F <= "0000" ;
WHEN "001" =>
F <= B - A ;
WHEN "010" =>
F <= A - B ;
WHEN "011" =>
F <= A + B ;
WHEN "100" =>
F <= A XOR B ;
WHEN "101" =>
F <= A OR B ;
WHEN "110" =>
F <= A AND B ;
WHEN OTHERS =>
Figure 6.48. Code that represents the
F <= "1111" ;
functionality of the 74381 ALU chip.
END CASE ;
END PROCESS ; Chapter 6-69
END Behavior ;

VHDL Operators (used for synthesis)

Chapter 6-70