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SAP

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187 views33 pages

Sap

SAP

Uploaded by

Swaroop Kumar
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© All Rights Reserved
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a0 SAP-1 ‘The SAP (Simiple-As-Possible) computer has been designed for you, the beginner. The main purpose of SAP is 10 [Link] the crucial ideas behind computer operation without burying you in unnecessary detail. But even a simple computer like SAP covers many advanced concepts, To avoid bombarding yoy with too much,all at once. we will examine threg different generations of the SAP com- puter, ‘SAP-I is the first stage in the evolution toward modem ‘compoters. Although primitive, SAP-1 is a big step for a beginner. So, dig into this chapter; master SAP-1, its architecture, its programming, and its circuits. Then you ‘will be ready for SAP-2. 10-1 ARCHITECTURE Figure 10-1 shows the architecture (structure) of SAP-1. a bbus-organized computer. All register outputs to the W bus ” are three-state; this allows ordetly transfer of data, Al! other register outputs are two-state; these outputs continuously drive the boxes they are connected to. ‘The layout of Fig. 10-1 emphasizes the registers used in SAP-1. For this reason. no attempt has been made to keep all control circuits in one bleck called the control unit, all input-output: circuits in another block called the 1/0 unit, ete. Many of the registers of Fig. 10-1 aré already iamiliar. from earlier examples and discussions. What follows is a brief description Of each box; detailed explanations come Jater. Program Counter “The program is stofed at the beginning of the memory with Be fist insimction at binary “address 0000. the second instruction at address 0001, the third at address 010. and + so on: The program counter. which is part of the control ‘unit, counts from 0000 to 1111. Jis job is to send to the memory the address of the next instruction to be fetched ‘und executed, It does this as follows. : 140 “The program counter s reset to 0000 before each computer rnin. When the computer run beging, the program counter sends address 0000 to the mentory. The program counter is then incremented to get 0001. After the first instruction is fetched and executed, the program counter sends address 0001 to the ‘memory. Again the program’ counter is incre- mented. After the second instruction is fetched and executed, ‘the program counter sends address 0010 to the memiory. In this way, the program counter is keeping track of the next instruction to be fetched and executed. The program counter is like someone pointing a fnget at alist of instructions, saying do this first, do this second, do this third, ete. This is why the program counter is = sometimes called a [poinrert it points to an address in femory wheré something important is being stored Input and MAR : l Below the program counter is the inpur and MAR block. It includes the address and data switch registers Wiscussed in Sec. 9-4. These'switch registers, which are part of the,inpat unit, allow’ you to send 4 address bits and 8 data bits the RAM. As you fecall,’ instruction and data words are written into the RAM before a computer run, ‘The memory address register (MAR) is part of the SAP- J memory. During @ computer. run. the address in the program counter is latched into. the MAR. A bit Jater, the _ MAR applies this 4-bit address to the RAM, where a read) ‘opetation is performed. © * The RAM ae The RAM is a 16 X 8 static TTL RAM.,As discussed in. See. 9-4; you can program the RAM by means of the address and data switch registers. This allows you to store ‘a program and data in the memory before # computer run, ‘During a computer run, the RAM receives 4-bit addresses from the MAR and a,read operation is performed. In this way, the instruction of data word stored in the RAM is placed fon the W bus for use in some other part of the computer Instruction ci cr cr ‘Controtter/ sequencer CoE ply WL SAP-1 architecture Register Ie instruction register is part of the control unit. To fetch instruction from the memory the computer does a memory operation. This places the contents ofthe addressed location .on the W bus. At the same’ time, the ion register is set up for loading on the next positive k edge. The contents of the instruction register are split into two les. The upper nibble is a two-state output that goes ly to the block labeled “*Controller-sequencer.”* The nibble is a three-state output that is read onto the W bus when needed. Sequencer lower left block ‘contains the controller-sequencer, fore each computer run. a CER signal is sent to the sm counter and a CLR signal to the instruction register. ‘Aéder) subtractor nae wn | foe (ea ee ‘ Output resister = Binary display Ea Suluigly = Cont voll word Cr sit) This resets the program counter to 0000 and wipes out the last instruction in4ine" instruction register, A clock signal CLK is sent to all buffer registers; this synichronizes the operation of the computer, ensuring that things happen when they are supposed to happen. In other ‘words. all register transfers occur on the positive edge of acommon CLK signal. Notice that a CLR signal also goes to the program counter. ‘The 12 bits that come out of:the controller-sequencer form [Link] controlling the rest of the: computer (like a Supervisor telling others what to do.) The 12 wires carrying the control word are called the contro! bus. The control word has the format of CON. = C;E.C,CE LEC.E, S, Lo This word determines how the registers will react to the ext positive CLK edge, For instance, a high E> and a low < Chapter10 sap-1 141 Ty mean that the contents of the program counter are latched into the MAR on the next positive clock edge. As another example, a low CE and a low L, mean that the addressed RAM word will be transferred to the accumulator on the next positive clock edge. Later, we will examine the timing diagrams (0 see exactly when and how these data transfers take place. e. Accumulator = The accumulator (A) is a buffer register that siores inter- mediate answers during a computer run. In Fig. 10+1 the accumulator has two outputs. The two-state output goes directly to the adder-subtracter. The three-state output goes to the W bus. Therefore, the 8-bit accumulator word continuously drives the adder-subtracter; the same word "appears on the W bus when E, is high, ‘The Adder-Subtracter ‘SAPzI uses a 2's-complement adder-subtracter. When Si: is low in Fig. 10-1, the sum out of the adder-subtracter is S=A+B (Recall that the:2's complement is equivalent to # decimal sigp change.) ‘The adder-subtracter is asynchronous (unclocked): this ‘means that its contents can change as soon as the input ” words change. When E,, is high, these contents appear on the W bus. 1B Register The B register is another buffer tegister. It is used in arithmetic: operations. A low Ly and positive clock edge load the word on the W. bus into the B register. The two- state output of the B register drives the adder-subtracter, supplying the number to be added or subtracted from the contents of the accumulator. Output Register Example 8-1 discussed the output register. At the end of a ‘computer run, the accumulator contains the answer to the Problem being solved..At this point, we need to transfer the answer to the outside world. This is, where the output - Fegister is used. When E, is high and Ly is low, the next Positive clock edge loads. the accumulator word into the output register: ‘The output register is often called an ourput port because Processed data can leave the computer through this register, 142 digital Computer Electronics __ input programming switches, the output port, and the binay} face circuits that drive peripheral devices like pri ‘cathode-ray tubes, teletypewriters, and so forth, (An it face circuit prepares the data to drive each device.) ting ip-flop of | output port, the binary display shows us the contents of ‘output port, Therefore, afier we've transferred an ansvel from the accumulator to the output port, we can see: answer in bindry form. Summary ‘The SAP-i control ‘unit consists of the program counter ihe instruction register, and the controller-sequencet produces the control word, the clear signals, and the cl signals, The SAP-1 ALU consisis of an accumulator, a adder-subtracter, and a B register. The SAP-1 memory the MAR and a 16 x. 8 RAM. The VO unit includes i display. 10-2 INSTRUCTION SET A computer is a useless pile of hardware until. someore| you Can program a computer, however, you must learn its instruction set, the basic operations it can perform. The ‘SAP-1 instruction set follows. LDA ‘As described in Chap. 9. the words in the memory can be symbolized by Ro, Rj, Rp, etc. This means that Re is stored at address OH, R, at address 1H, Ry at address 2H, and so on. LDA stands for ‘load the accumulator.” A complete LDA. instruction. includes the hexadecimal address of the data to be loaded. LDA 8H, for example, means “load the ‘accumulator with the contents of memory location’ 8H." Therefore, given Ry = 1111 0000 the execution of LDA 8H resuits in A= 1111 0000 Similarly, LDA AH means “load the accumulator with the contents of memory location AH.” LDA FH ‘means “load the accumulator with the contents of memory location FH," and so on. DD is another SAP-1 instruction. A complete ADD ition includes the address of the word to be added, instance, ADD 9H means “add the contentsisf memory tion 9H to the accurnulator contents"; the sunt replaces original contents of the accumulator. itor and decimal 3 js in memory location 9H. Then A = 00000010 Ry = 00000011 ing the execution of ADD 91, the following things pen. First, Ry is loaded into the B register to get B= 0000 0011 i almost instantly the adder-subtracter forms the sum of nd B SUM= 0000 0101 d, this sum is loaded into the accumulator to get A= 0000 0101 foregoing routine is used for all ADD instructions; addressed RAM word goes to the B register and the -subtracter output to the accumulator. This is why the ion of ADD 9H adds Re to the accumulator contents, ‘execution of ADD FH adds Ry to the accumulator: and, $0-0n. : is another SAP-1 instruction. A complete SUB in- tion includes the address of the word to be subtracted. mc example. SUB-CH means “‘subtract the contents of oty location CH from the [Link] the accumulator’; he difference out of the adder-subtracter then replaces the final contents of the accumulator. Foc concrete example, assume that decimal 7 is in the mumulator and decimal 3 is in memory location CH. Then A = 00000111 Re = 00000011 he execition of SUB CH takes place as follows. First, is loaded into the B register to get B = 0000 0011 i almost instantly the adder-subteacter forms the dilfer- ee of A and B: DIFF = 0000 0100 e's an example. Suppose decimal 2-is in the ascu- - ‘Second, this difference is loaded into the accumulator and ‘A = 0000 0100 ‘The foregoing routine applies 10 all SUB instructions: the addressed RAM word goes to the B register and the adder-subtracter output to the accumulator. This is why the ‘execution of SUB CH subtracts Ro from the contents of the accumulator, the execution. of SUB EH subtracts Ry from the accumulator, and so on. OUT The instruction OUT tells the SAP-1 computer to transfer the accumulator contents to the output port, After QUT has been executed, you can see the answer to the problem being, solved. : OUT is complete by itself; that is, you do not have to include an address when using OUT because the instruction does not involve data in the memory. HLT HLT stands for halt. This instruction tells the computer to Stop processing data, HLT marks the end of a program, similar to the way a period margs the end of a sentence. ‘You must use a HLT instruction at the end of every SAP- L program; atherwise, you get computer trash (meaningless answers caused by runaway processing). : HLT is complete by itself; you do not have to include a RAM word when using HLT because this instruction does not involve the memory. Memory-Reference Instriictions LDA, ADD, and SUB are called memory-reference instruc- tions because they use data stored in the memory. OUT and HLT, on the other hand, are not memory-reference instructions because they do not involve data stored in the memory. : : Mnemonics LDA, ADD, SUB. OUT, and HLT are the instruction set "for SAP-1. Abbreviated instructions like these are called mnemonics (memory aids). Mnemonics are popular in computer work because they remind you of the operation that will take place when the instruction is executed. Table 10-1 summarizes the SAP-1 instruction set. The 8080 and 8085 ‘The 8080 was the first widely used microprocessor. It has 72 instructions. The 8085 is an enhanced version of the 8080 with essentially the same instruction set. To make SAP practical. the SAP instructions will be upward com- Chapter 10 sap-1 143 ‘FABLE 10-1. SAP-1 INSTRUCTION SET ———— ‘Mnemonic Operation EDA Load RAM data into accumulator ADD Add RAM data to accumulator SUB Subtract RAM data from accumulator OUT Load accumulator data into output register HLT “Stop processing patible with the 8080/8085 instruction set. In other words, the SAP-1 instructions LDA, ADD, SUB, OUT, and HLT ‘are 8080/8085 instructions. Likewise, the SAP-2 and SAP- 3 instructions will be part of the 8080/8085 instruction Set: Learning SAP instructions is getting you ready for the 8080 and 8085, two widely used microprocessors. EXAMPLE 10-1 Here's a SAP-1 program in mnemonic form: se ‘Address. Mnemonics oH LDA 9H 11 ADD AR pr ADD BH 3H SUB CH 4H ouT’ SH HLT The data in higher memory is ‘Address Data 6H FFH 7H FFH 8H FEH 9H eH : Aa OH BH 03H cH 4H DH FFH EH FFH. FH FFH What does each instruction do? SOLUTION ‘The program is in the low memory, located at addresses OH to SH. The first instruction loads the accumulator with 144 Digital Computer Etectronics © the contents of memory location 9H, and so the accumula ‘contents become A= 01H ‘The second instruction adds the contents of memory locati AH [Link] accumulator contents to get a new accumul: total of A= 01H + 02H = 03H Similafly, the third instruction add the contents of location BH A = 03H + 03H = 06H ‘The SUB instruction subtracts the contents of location CH to get A = 06H - 04H = 02H ‘The OUT instruction loads the accumulator contents the output port: therefore, the binary display. shows ‘0000 0010 ‘The HLT instruction stops the data processing. 10-3 PROGRAMMING SAP-1 To load instruction and data words into the SAP-1 me we have to use some kind of code that the computer incerpret. Table 10-2 shows the code used in SAP-1. ‘number 0000 stands for LDA, 0001 for ADD, 0010 SUB, 1110 for OUT, and 1111 for HLT. Because this tells the computer which operation to perform, it is an operation code (op code). ‘As discussed earlier, the address and data wi Fig, 9-7 allow. you to program the SAP-1 memory design, these switches produce a 1 in the up postion TABLE 10-2. SAP-1 ~ OPCODE. =, Mnemonic - Op code LDA 0000 ADD. 0001, SWB 0010 ouT 1110 HLT nu upper nibble, and the operand (the rest of the instruction) into the lower nibble. _ For instance, suppose we want to store the following Address Instruction OH LDA FH 1H ADD EH 2H HLT and a 0 in the down position (D). When programming the ata switches with an instruction, the op code goes into the First, convert each instruction to binary as follows: LDAFH = 00001111 ADD EH = 0001 1110 HLT = 1111 XXXX 1111 is the binary equivalent of FH. In the second instruc- tion, 0001 is the op code for ADD, and 1110 is the binary > equivalent of EH. In the third instruction, 1111 is the op code for HLT, and XXXX are don’t cares because the HLT: is not a memory-reference instruction, Next, set up the address and data switches as follows: Address DDDD DDDU DDUD Data DDDD UUUU DDDU UUUD UUUU XXxx ‘ pue sssiuno Buys “1990299 opus $101 “PLA a ts) Jigat of the Q, fip-flop (pin 1, C38). Because of this. [output is initially high. signal drives an active low input. This means negative edge of the CLK signal initiates each T Halfa cycle later. the positive edge of the CLK signal shoes register loading, ‘as previously described. Matrix ADD. SUB, and OUT signals from the instruction br drive the control matrix, C39 to C48, At the same g the ring-counter signals, 7; to Ty, are driving the it (a circuit receiving two groups of bits from’different 23) The matrix produces CON, a 12-bit microinstruc- that tells the rest of the computer what to do. Fig. 10-13, 7, goes high, then T;, then 7, and so on. ze the control matrix and here is what you will find. ghT, produces a high E, and a tow Ly (address sta gh T; results in a high C, (increment state); and a high a low CE and a low Z, (memory state). The jiree T states, therefore, afe always the fetch cycle in 1. In chunked notation, the CON words for the fetch ae State CON Active Bits q SEH T; BE3H Ty 263H ing the execution states, T through T, go high in jon. At the same time, only one of the decoded (LDA through’ OUT) is high. Bécause of this, the PaaS oy ee ate Dan Dt hr amet ol ines, i istance, when LDA is high, the only enabled 2- NANO gates are the first, fourth, seventh, and tenth, tT, is high, it activates the first and seventh NAND resulting in low Z,, and low E, (load MAR with ps field). When 7; is high, it activates the fourth and hh NAND gates, producing a low CE and a low L, (load data into accumulator). When T, goes high, none of control bits are active (nop). fou should analyze the action of the control matrix fing the execution states of the remaining possibilities: ‘ADD. high SUB, and high OUT. Then you will agree control matrix ‘can generate the ADD, SUB, and OUT kninstructions shown in Table 10-5 (SAP-1 micropro- each computer run. the operator enters the program data into the SAP-1 memory. With the program in low memory and the data in high memory. the operator presses and releases the clear button. The CLK: and CLK signals rive the registers and counters. The microinstruction out of the controller-sequencer determines. what happens of ech positive CLK edge. Each SAP-1 machine cycle begins with a fetch cycle. T, is the address state, T; is the increment state, and 7; is the memory state, At the end of the fetch cycle, the instruction is stored in the instruction register. Afier the instruction field has been decoded, the control matrix automatically enerates the comect execution routine, Upon completion of the execution cycle, the ring counter resets apd the next machine cycle begins. ‘The data processing ends when a HLT instruction is loaded into the instruction register. zy 10-8 MICROPROGRAMMING ‘The control matrix of Fig. 10-15 is one, way to generate the microinstructions needed for each execution cycle. With larger instruction sets, the control matrix becomes very ‘complicated and requires hundreds or even thousands of gates, This is why hardwired control (matrix gates séldered together) forced designers to look for an alternative way to produce the control words that run'a computer: Microprogramming is the alternative. The basic idea is to store microinstructions in a ROM rather than produce them, with a control matrix. This approach simplifies the problem of building a controller-sequencer. Storing the Microprogram By assigning addresses and including the fetch routine, we can come up with the SAP-1 microinstructions shown in Table 10-6. These microinstructions can be stored in a control ROM with the fetch routine at addresses OH to 2H, the LDA routine at addresses 3H to SH, the ADD routine at 6H to 8H, the SUB routine at 9H to BH, and the OUT routine at CH to EH. To access any routine, we need. to supply the correct addresses. For instance, to get the ADD routine, we teed to supply addresses GH. 7H, and 8H. To get the OUT. routine, we supply addresses CH, DH, and EH. Therefore, accessing any routine requires three steps: 1, Knowing the starting address of the routine 2. Stepping through the routine addresses 3. Applying the addresses to the control ROM. Address ROM Figure 10-16’ shows how to microprogram the SAPS computer. It has an address ROM. a presettable counter. and 3 control ROM. The address ROM contains the start addresses of each routine in Table 10-6. In other words, + Chapter 10 sari 162 TABLE 10-6. SAP-1 CONTROL ROM . TABLE 10-7, ADDRESS ROM Address ‘Contentst, Routine OH SE3H Fetch 1H BE3H 2H. - 263H 3H 1A3H_ » LDA 4H 2C3H. SH 3E3H 6H 7 1A3H ADD 7H Ts 2E1H 8H og 3C7H 9H 1A3H_ ‘SUB AH 2E1H BH 3CFH CH 3F2H OUT DH 3E3H EH 3E3H FH Ree TCON = GELCE TELE, SuetLy. Fig. 10-16 Microprogrammed control of SAP-1. the address ROM contains the data listed in Table 10-7. As shown, the starting =ddress of the LDA-routine is 0011, the starting address of the ADD rouune is 0110, and so on. ‘When the op-code bits Indsly drive the address ROM, the starting address is generated. For instance, if the ADD FG3 > bignst coupieer Kimerenics Routine | ‘Address Contents ~~ 0000 ool LDA 0001 0110 * “ADD 0010, * 1001 SUB O01 XXXX None 0100 XXXX None 101 XXXX | None 0110 XXXX None Onl XXXX None 1000 XXXX None 1001 XXXX None 1010 XXXX Notie 101t XXXX None 1100 XXXX None J x01 XXXX None 110 1100 our mt XXXX None instruction is being executed, Inlglsl, is 0001. This is input to the address ROM; the output of this ROM is Ol} Presettable Counter When T, is high, the load input of the preseriable is high and the counter loads the starting address from! address ROM. During the other 7 states, the counter Initially, a high CLR signal from the clear-stan. is differentiated to, get a narrow positive spike. the counter. When the computer run begins, the output is 0000 during the 7; state, 0001 during the 7 and 0010 during the 7; state. Every fetch cycle ts the: because 0000, 0001, arid 0010 come out of the during states T,, 7, and Ts. ‘The op code in. the instruction register controls execution cycle. If an ADD instruction has’been fe the Iyk[jl, bits are 0001. These op-code bits drive address ROM, producing an output of 9110 (Table I This starting address is the input to the presettable When T, is high, the next negative clock edge loads: into the presettable counter. The counter is now preset, ‘counting can resume at the starting address of the routine. The counter output is 0110 during the T, 0111 during the T; state, and 1000 during the 7, state, ‘When the T, state begins, the leading edge of the! signal is differentiated to produce a narrow positive which resets the counter to 0000, the starting address the fetch routine. A new machine eycle then begins. ol ROM he control ROM: stores the SAP-1 microinstructions. ing the: fetch cycle, it receives addresses 0000. 0001, 10010, Therefore, its outputs are 5E3H BESH 263H yse microinstruction, listed in Table 10-6, produce the state, increment state, and memory state. if m ADD instruction is being executed, the control OM teceives addresses 0110, O111, dnd 1000 during the rection cycle. fts outputs are 2 - \ 1a3H * 2E1H 3C7H pse microinstructions carry out the addition as previously: ‘For another exarnple, suppose the OUT instruction is ing executed: Then the op code is 1110 and the starting dress is 1100 (Table 10-7). During the execution cycle, ‘counter output is 1100, 1101, and 1110. The output of control ROM is 3F2H, 3E3H, and 3E3H (Table 10-6). routine transfers the accumulator contents to the output Machine Cycle microinstruction 3E3H in Table 10-6 is a nop. It occurs vt in the LDA routine and twice in the OUT routine. nops are used in SAP-1 to get a fixed machine cycle ot all instructions. In other words, each machine cycle Hikes exactly six T'states, no matter what the instruction. some computers a fixed machine cycle is an advantage. ‘when speed is important, the nops are a waste of time nd can be eliminated. One way to speed up the operation of SAP-1 is to skip ay T state with a nop. By redesigning the circuit of Fig. (416 we can eliminate the nop states. This will shorten machine cycle of the LDA instruction to five states (T, T,, Tz, and T;). It also shortens the machine cycle of OUT instruction to four T states (T,, Tz, Ts, and T,). Figure 10-17 shows one way to get a variable machine gue. With an LDA instruction, the action is the same as Iefore during the 7; to T; states. When the T,, state begins, control ROM produces an output of 3E3H (the nop ‘nicroinstruction). The NAND gate detects this nop instantly and produces a low output signal NOP. NOP is fed back ‘othe ring counter through an AND gate, as shown in Fig. 10-18. This resets the ring counter to the T, state, and a new machine cycle begins. This reduces the machine cycle cf the LDA instruction from six stites to five. Adaress tex 4 is L0ao % ca Sk Prewtabie ‘counter Control ROM 16X12 4 é Microinstrucion Fig. 10-17 Variable machine cycle. | gy SI 4 Fig. 10-18, With the OUT instruction, the first nop occurs in the 7; state. In this case, just after the 7; state begins, the control ROM produces an output of 3E3H, which is detected by the NAND gate. The low NOP signal then resets the ring counter to the 7; state, In this way, we have reduced the machine cycle of the OUT instruction from six states to four. chapter 10 sapt 163 Variable machine cyeles are commonly used with imicro- processors. In the 8085, for example, the machine cycles take from, two to six’ 7 states because all unwanted nop slates are ignored. | Advantages ‘One advantage of microprogramming is the elimination of. the instruction decoder and control matrix; both of these become very complicated for larger instruction sets. {n other words, it's,a lot easier to store microinstructions in a ROM than it is to wire an instruction decoder and control matrix. Furthermore, once you wire an instruction decoder aru ‘control matrix, the only way you can change the instruction GLOSSARY ‘address state The T; state. During this state, the address in the program counter is transferred to the MAR. ‘accumulator. ‘The place where answers to arithmetic and logic operations are accumulated. Sometimes called the A register. assembly language ‘The mnemonics used in writing a rogram. B register ‘An auxiliary register that stores the data to be added or subtracted from the accumulator. Setch eycle “The first part of the instruction cycle. During ‘the fetch cycle, the address is sent to the memory, the rogram counter is incremented, and the instruction is transferred from the memory to the instruction register. increment state. The T; state. During this state, the pro- ‘gram counter is incremented. instruction cycle All the states necded to fetch and execute an instruction. instruction register The register that receives the instruc- tion from the memory, instruction set The instructions 4 computer responds to. LDA Mnemonic for load the accumulator. machine cycle All the states generated by the sing counter. machine language The strings of Os and Is used in a Program. macroinstruction set. ‘One of the instructions in the instruction SELF-TESTING REVIEW Read each of the following and provide the missing words. Answers appear at the beginning of the next question. 1. The counter, which is part of the con-. counts from 0000,to 1111. It sends to the memory the of the next instruction. 164 Digital Computer Electronics is by disconnecting and rewiring. This is not with microprogrammed' control; all you have to do is the control ROM and the starting-address, ROM. This i Summary In conclusion, most modem microprocessors use micropro grammed control instead of hardwired contro}. The micro programming tables and circuits are more complicated thay those for SAP-1,.but the idea is the same. Microinstructic are stored in a control-ROM and accessed by applying i address of the desired microinstruction. MAR * Memory address register. This register receives address of the dita to be accessed in memory. The supplies this address to the memory. memory-reference instruction An instruction that fot a second memory uperation to access data. ‘memory state Tue T, state. During this state, the i tion in the memory is transferred to the instruction regis ‘microinstruction . A control word out of the controll sequencer. The smallest step in the data processing. op No operation. A state during which nothing happe output register The register that receives processed from the accumulator and drives the eutput display of S 1. Also called an output port. ‘object program A program written in machine | opcode Operation code. That part of the instruction whi tells the computer what operation to perform. program counter A register thet counts in binary. contents are the address of the next instruction to be fe from the memory, RAM -Random-aecess memory. A better name is write memory. ‘The RAM stores the program and needed for a computer rin. source program ~ A program written in mnemonics. 2. (program, address) The MAR, or ister, latches the address from the program cou A bit later, the MAR applies this address to the « where a read'operation is performed. 3. (memory-address, RAM) The instruction register ih reg] lar to Example 10-1) that will display the result of 5+4-6 ‘Use addresses DH, EH, and FH forthe data. 1. Convert the assembly language of Prob. 10-1 into SAP-1 machine language. Show the answer in binary form and in hexadecimal form. Write an assembly-language program that per- forms this operation: * 8+4<54+5-2 ‘Use addresses BH 10 FH for the data. Convert the program and data of Prob. 10-3°into machine language. Express the result in both binary and hexadecimal form. Figure 10-19 shows the timing diagram for the ADD instruction. Draw the timing diagram for the SUB instruction. 1. Write a SAP-1 program using mnemonics (simi- “partof the control unit, The contents of the 9. (op, Assembly, Machine) SAP-1 has —__T. register are split into two nibbles. The states, periods during which register contents upper nibble goes to the —_____. change. The ring counter, or _______ counter, (insiruction, controller-sequencer) The controller- produces these T states. These six T states represent sequencer produces a 12-bit word that controls the ‘one machine cycle. In SAP-I the instruction cycle rest of the computer. The 12 wires carrying this thas only one machine cycle. In microprocessors. like ‘word are called the control the 8080 and the 8085, the cyele may as hhave from one to five machine cycles. (control. bus) The is a buffer register 10. (six. state, instruction) The controller-sequencer _thatstores sums or differences. Its two-state output sends out control words, one during each T state * 40es to the adder-subtracter. The —______pro- ‘or clock cycle. Each control word is called a duces the sum when S, is low and the difference Instructions like LDA, ADD, SUB, when S, is high. The output register is sometimes tc, are called .. Each SAP-1. maeroin- called an output struction is made up of three (accumulator, adder-subtracter, port) The SAP-1 1. (microinstruction, macroinstructions, microinstruc- | —_____ tis LDA, ADD, SUB, OUT, and tions) With larger instruction sets, the control ma- HLT. LDA. ADD, and SUB are called —_____

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