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Moore FSM for Sequence Detection

This document describes a Moore type finite state machine (FSM) implementation of a sequence detector that detects the binary sequence 10100101. It provides the state diagram and Verilog code for the FSM module and testbench. The FSM has 8 states (S0-S8) and its output is determined solely by the current state (S8 in this case), characteristic of a Moore machine. The code defines the state transition logic and outputs for each state based on the current input bit to detect the target sequence.

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Priya Apte
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10 views9 pages

Moore FSM for Sequence Detection

This document describes a Moore type finite state machine (FSM) implementation of a sequence detector that detects the binary sequence 10100101. It provides the state diagram and Verilog code for the FSM module and testbench. The FSM has 8 states (S0-S8) and its output is determined solely by the current state (S8 in this case), characteristic of a Moore machine. The code defines the state transition logic and outputs for each state based on the current input bit to detect the target sequence.

Uploaded by

Priya Apte
Copyright
© All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd

EE16M044

Apte Priya Narayanrao

EE5703 : VLSI DESIGN LAB


Sequence Detector(Moore type)

A sequence detector accepts as input a string of bits: either 0 or


1. Its output goes to 1 when a target sequence has been
detected. A finite state machine can be divided into two types
:Mealy and Moore . A Mealy machine is a finite-state machine
whose output values are determined both by its current state and
the current inputs. This is in contrast to a Moore machine, whose
output values are determined solely by its current state.
In this assignment we are implementing Moore type fsm with non
overlapping sequence detection .The sequence to be detected is
10100101.
State machine diagram is given below :
Verilog code :
module pattern_moore (clk, reset, in, out );

input clk, reset;


input in;
output out;
reg out;

parameter S0 = 0,
S1 = 1,
S2 = 2,
S3 = 3,
S4 = 4,
S5 = 5,
S6 = 6,
S7 = 7,
S8 = 8;

// Registers to hold current and next state


reg [3:0]cstate, nstate;

always @(posedge clk) begin


if (reset) begin
cstate <= S0;
end else begin
cstate <= nstate;
end
end

always @(cstate or in) begin


nstate = cstate;

case (cstate)
S0: begin
if (in == 'b1) begin
nstate = S1;
end
else begin
nstate = S0;
end
end
S1: begin
if (in == 'b0) begin
nstate = S2;
end
else begin
nstate = S0;
end
end
S2: begin
if (in == 'b1) begin
nstate = S3;
end
else begin
nstate = S0;
end
end
S3: begin
if (in == 'b0) begin
nstate = S4;
end
else begin
nstate = S1;
end
end
S4: begin
if (in == 'b0) begin
nstate = S5;
end
else begin
nstate = S3;
end
end
S5: begin
if (in == 'b1) begin
nstate = S6;
end
else begin
nstate = S0;
end
end
S6: begin
if (in == 'b0) begin
nstate = S7;
end

else begin
nstate = S1;
end
end
S7: begin
if (in == 'b1) begin
nstate = S8;
end
else begin
nstate = S0;
end
end
S8: begin
if (in == 'b1) begin
nstate = S1;
end
else begin
nstate = S0;
end
end
default: begin

nstate = S0;
end
endcase // case (cstate)
end // always @ (cstate or in)

always @ (cstate) begin


out = (cstate == S8);

end //
// always @ (cstate)

endmodule // fsm

Verilog code for testbench :


module pattern_moore_tb;
parameter NUMINPUTS = 100;

reg clk, reset, in;


wire out;
reg inputs[0:NUMINPUTS-1];
integer i;

// Instantiate module to be tested


pattern_moore dut(.clk(clk),
.reset(reset),
.in(in),
.out(out));

always #5 clk = ~clk;

initial begin
$readmemb("[Link]", inputs);
$monitor($time, "in = %b, out = %b", in, out);

clk = 0;
reset = 1;
#10 reset = 0;

// Simple way to wait until next clock edge:


@ (posedge clk);

for (i=0; i<NUMINPUTS; i=i+1) begin


in = inputs[i];
@ (posedge clk);
end
$finish;

end

endmodule // pattern_tb

Results :
Exercise : In the example sequence detector to detect 101
sequence it was Mealy fsm. A Mealy machine is a finite-state
machine whose output values are determined both by its current
state and the current inputs. This is in contrast to a Moore
machine, whose output values are determined solely by its
current state.
In Moore we have one extra state which has its output value set
high to indicate that he pattern is detected .

Common questions

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Using a Moore machine for sequence detection often requires more states than a Mealy machine because output changes can only occur on state transitions. This can lead to less precise control over output timing, as changes must wait for a state transition rather than responding immediately to input changes, which is permissible in a Mealy machine .

The reset signal initializes the current state (cstate) to the starting state (S0) when it is active. This ensures the state machine begins in a known state for consistent operation .

A testbench is important because it simulates the operation of the Moore FSM by providing a controlled and repeatable test environment. It applies inputs over time, monitors outputs, and verifies the FSM transitions and outputs correctly match expected behavior, thereby ensuring the design meets specifications .

The non-overlapping sequence detector transitions through a series of predefined states corresponding to each part of the input sequence. Starting at S0, it advances to specific states (S1 through S8) upon recognizing parts of the sequence '10100101'. Once it reaches S8, the sequence is considered detected and the output is set to 1 .

A Moore machine determines its output solely based on its current state, whereas a Mealy machine's output is determined by both its current state and current inputs .

In Moore machines, output changes occur only on state transitions. The extra state is required to have an output value set high, as the output depends solely on the state and cannot change in response to input without a new state .

The transition to the next state in the Moore FSM is caused by a change in the input values, as evaluated in the 'always' block associated with the current state (cstate). The next state is determined and stored based on these input conditions as outlined in the 'case' statement .

The 'case' statement in the Verilog implementation is used to decide the next state (nstate) based on the current state (cstate) and input. It evaluates the current state and input condition to transition the FSM to the appropriate next state .

The implementation uses an always block to toggle the clock signal every 5 units of time, effectively simulating a continuous clock signal to drive state transitions and operations within the FSM .

The 'reg' keyword is used to declare the output variable 'out' because in Verilog, outputs that depend on sequential logic or are modified inside always blocks must be of type 'reg'. This ensures the output can hold its value through sequential state transitions .

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