ARM Instructions
B
B.1
Data-processing Instructions
B.2
Memory Instructions
B.3
Branch Instructions
B.4
Miscellaneous Instructions
B.5
Condition Flags
This appendix summarizes ARMv4 instructions used in this book.
Condition encodings are given in Table 6.3.
Application
Software
B.1 DATA-PROCESSING INSTRUCTIONS
Standard data-processing instructions use the encoding in Figure B.1. The
4-bit cmd field specifies the type of instruction as given in Table B.1.
When the S-bit is 1, the status register is updated with the condition flags
produced by the instruction. The I-bit and bits 4 and 7 specify one of
three encodings for the second source operand, Src2, as described in
Section 6.4.2. The cond field specifies which condition codes to check,
as given in Section 6.3.2.
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Digital Design and Computer Architecture, Second Edition. DOI: 10.1016/B978-0-12-800056-4.00017-0
2016 Elsevier Inc. All rights reserved.
535
536
APPENDIX B
ARM Instructions
Immediate
Data-processing
11:8
7:0
rot
imm8
I=1
31:28
27:26 25
24:21
20
cond op
I cmd S
00
19:16
15:12
11:0
Rn
Rd
Src2
funct
11:7
I=0
3:0
6:5 4
Register shamt5 sh 0
11:8
Rs
0 sh 1
6:5
Rm
3:0
Rm
Register-shifted
Register
Figure B.1 Data-processing instruction encodings
Table B.1 Data-processing instructions
cmd
Name
Description
Operation
0000
AND Rd, Rn, Src2
Bitwise AND
Rd Rn & Src2
0001
EOR Rd, Rn, Src2
Bitwise XOR
Rd Rn ^ Src2
0010
SUB Rd, Rn, Src2
Subtract
Rd Rn Src2
0011
RSB Rd, Rn, Src2
Reverse Subtract
Rd Src2 Rn
0100
ADD Rd, Rn, Src2
Add
Rd Rn+Src2
0101
ADC Rd, Rn, Src2
Add with Carry
Rd Rn+Src2+C
0110
SBC Rd, Rn, Src2
Subtract with Carry
Rd Rn Src2 C
0111
RSC Rd, Rn, Src2
Reverse Sub w/ Carry
Rd Src2 Rn C
1000 (S = 1)
TST Rd, Rn, Src2
Test
Set flags based on Rn & Src2
1001 (S = 1)
TEQ Rd, Rn, Src2
Test Equivalence
Set flags based on Rn ^ Src2
1010 (S = 1)
CMP Rn, Src2
Compare
Set flags based on Rn Src2
1011 (S = 1)
CMN Rn, Src2
Compare Negative
Set flags based on Rn+Src2
1100
ORR Rd, Rn, Src2
Bitwise OR
Rd Rn | Src2
1101
I = 1 OR
(instr11:4 = 0)
I = 0 AND
(sh = 00;
instr11:4 0)
I = 0 AND
(sh = 01)
Shifts:
MOV Rd, Src2
Move
Rd Src2
LSL Rd, Rm, Rs/shamt5
Logical Shift Left
Rd Rm << Src2
LSR Rd, Rm, Rs/shamt5
Logical Shift Right
Rd Rm >> Src2
(continued)
537
B.1 Data-processing Instructions
Table B.1 Data-processing instructionsContd
cmd
Name
Description
Operation
I = 0 AND
(sh = 10)
I = 0 AND
(sh = 11;
instr11:7, 4 = 0)
I = 0 AND
(sh = 11;
instr11:7 0)
ASR Rd, Rm, Rs/shamt5
Arithmetic Shift Right
Rd Rm>>>Src2
RRX Rd, Rm, Rs/shamt5
Rotate Right Extend
{Rd, C} {C, Rd}
ROR Rd, Rm, Rs/shamt5
Rotate Right
Rd Rn ror Src2
1110
BIC Rd, Rn, Src2
Bitwise Clear
Rd Rn & ~Src2
1111
MVN Rd, Rn, Src2
Bitwise NOT
Rd ~Rn
NOP (no operation) is typically encoded as 0xE1A000, which is equivalent to MOV R0, R0.
B . 1 . 1 Multiply Instructions
Multiply instructions use the encoding in Figure B.2 The 3-bit cmd field
specifies the type of multiply, as given in Table B.2.
Multiply
31:28
cond
4 bits
27:26 25:24 23:21 20
19:16
15:12
op 00 cmd S
00
Rd
4 bits
2 bits
6 bits
11:8
7:4
3:0
Figure B.2 Multiply instruction
Ra
Rm
1001
Rn
encoding
4 bits
4 bits
4 bits
4 bits
Table B.2 Multiply instructions
cmd
Name
Description
Operation
000
MUL Rd, Rn, Rm
Multiply
Rd Rn Rm (low 32 bits)
001
MLA Rd, Rn, Rm, Ra
Multiply
Accumulate
Rd (Rn Rm)+Ra (low 32 bits)
100
UMULL Rd, Rn, Rm, Ra
Unsigned Multiply
Long
{Rd, Ra} Rn Rm
(all 64 bits, Rm/Rn unsigned)
101
UMLAL Rd, Rn, Rm, Ra
Unsigned Multiply
Accumulate Long
{Rd, Ra} (Rn Rm)+{Rd, Ra}
(all 64 bits, Rm/Rn unsigned)
110
SMULL Rd, Rn, Rm, Ra
Signed Multiply
Long
{Rd, Ra} Rn Rm
(all 64 bits, Rm/Rn signed)
111
SMLAL Rd, Rn, Rm, Ra
Signed Multiply
Accumulate Long
{Rd, Ra} (Rn Rm)+{Rd, Ra}
(all 64 bits, Rm/Rn signed)
538
ARM Instructions
APPENDIX B
B.2 MEMORY INSTRUCTIONS
The most common memory instructions (LDR, STR, LDRB, and STRB) operate on words or bytes and are encoded with op = 01. Extra memory
instructions operating on halfwords or signed bytes are encoded with
op = 00 and have less flexibility generating Src2. The immediate offset
is only 8 bits and the register offset cannot be shifted. LDRB and LDRH
zero-extend the bits to fill a word, while LDRSB and LDRSH sign-extend
the bits. Also see memory indexing modes in Section 6.3.6.
Memory
31:28
cond
27:26
25:20
op I P U B W L
01
Immediate
19:16
15:12
11:0
Rn
Rd
Src2
I=1
Extra memory
31:28
27:26
25:20
op 0 P U I W L
00
19:16
15:12
Rn
Rd
imm12
11:7
funct
cond
11:0
I=0
shamt5
Immediate
7
6:5
3:0
Src2a 1 op2 1 Src2b
funct
I=0
3:0
Rm
Register
I=1
11:8
6:5
sh 1
11:8
3:0
imm87:4
imm83:0
11:8
3:0
0000
Rm
Register
Figure B.3 Memory instruction encodings
Table B.3 Memory instructions
op
op2
Name
Description
Operation
01
N/A
STR
Rd, [Rn, Src2]
Store Register
Mem[Adr] Rd
01
N/A
LDR
Rd, [Rn, Src2]
Load Register
Rd Mem[Adr]
01
N/A
STRB Rd, [Rn, Src2]
Store Byte
Mem[Adr] Rd7:0
01
N/A
LDRB Rd, [Rn, Src2]
Load Byte
Rd Mem[Adr]7:0
00
N/A
01
STRH Rd, [Rn, Src2]
Store Halfword
Mem[Adr] Rd15:0
00
N/A
01
LDRH Rd, [Rn, Src2]
Load Halfword
Rd Mem[Adr]15:0
00
N/A
10
LDRSB Rd, [Rn, Src2]
Load Signed Byte
Rd Mem[Adr]7:0
00
N/A
11
LDRSH Rd, [Rn, Src2]
Load Signed Half
Rd Mem[Adr]15:0
539
B.3 Branch Instructions
B.3 BRANCH INSTRUCTIONS
Figure B.4 shows the encoding for branch instructions (B and BL) and
Table B.4 describes their operation.
Branch
31:28
27:26 25:24
23:0
cond op
10 1L
Figure B.4 Branch instruction
imm24
encoding
funct
Table B.4 Branch instructions
Name
Description
Operation
B label
Branch
PC (PC+8)+imm24 << 2
BL label
Branch with Link
LR (PC+8) 4; PC (PC+8)+imm24 << 2
B.4 MISCELLANEOUS INSTRUCTIONS
The ARMv4 instruction set includes the following miscellaneous instructions. Consult the ARM Architecture Reference Manual for details.
Instructions
Description
Purpose
LDM, STM
Load/store multiple
Save and recall registers in
subroutine calls
SWP / SWPB
Swap (byte)
Atomic load and store for
process synchronization
LDRT, LDRBT,
STRT, STRBT
Load/store word/byte
with translation
Allow operating system to
access memory in user virtual
memory space
SWI1
Software Interrupt
Create an exception, often
used to call the operating
system
CDP, LDC, MCR,
MRC, STC
Coprocessor access
Communicate with optional
coprocessor
MRS, MSR
Move from/to status
register
Save status register during
exceptions
SWI was renamed SVC (supervisor call) in ARMv7.
540
APPENDIX B
ARM Instructions
B.5 CONDITION FLAGS
Condition flags are changed by data-processing instructions with S = 1 in
the machine code. All instructions except CMP, CMN, TEQ, and TST must have
an S appended to the instruction mnemonic to make S = 1. Table B.5
shows which condition flags are affected by each instruction.
Table B.5 Instructions that affect condition flags
Type
Instructions
Condition Flags
Add
ADDS, ADCS
N, Z, C, V
Subtract
SUBS, SBCS, RSBS, RSCS
N, Z, C, V
Compare
CMP, CMN
N, Z, C, V
Shifts
ASRS, LSLS, LSRS, RORS, RRXS
N, Z, C
Logical
ANDS, ORRS, EORS, BICS
N, Z, C
Test
TEQ, TST
N, Z, C
Move
MOVS, MVNS
N, Z, C
Multiply
MULS, MLAS, SMLALS, SMULLS, UMLALS,
UMULLS
N, Z