LESSON PLAN
Name of the Faculty : [Link]
Subject with Code : VLSI DESIGN (A60432 )
Year / Semester : III [Link]-II-Sem
Course Objective:
Academic Year : 2015-16
Branch / Sec:
ECE-A
Sl.
No.
UNIT-I Introduction to IC Technology & Basic Electrical Properties
1
2
3
4
5
6
7
UNIT-II VLSI Circuits Design Processes
8
9
10
11
12
UNIT-III Gate Level Design
13
14
15
16
17
UNIT-IV Data Path Subsystem
18
19
20
21
22
UNIT-V Programmable Logic Design
23
24
25
26
27
28
29
30
31
FACULTY
LESSON PLAN
of the Faculty : [Link]
t with Code : VLSI DESIGN (A60432 )
Semester : III [Link]-II-Sem
Objective:
Academic Year : 2015-16
Branch / Sec:
ECE-A
The objective of this course is to introduce different IC technologies, fabrication ,electric properties,constructions of
layout diagram and study of different array logics such as PLA,PAL,FPGA,CPLD and CMOS testing.
Topic
UNIT-I Introduction to IC Technology & Basic Electrical Properties
Introduction: Introduction to IC Technology
MOS, PMOS, NMOS, CMOS &BiCMOS
Basic Electrical Properties of MOS and BiCMOS Circuits
MOS transistor threshold Voltage
gm, gds, Figure of merit Wo
Pass transistor, NMOS Inverter
Various pull ups, CMOS Inverter analysis and design, Bi-CMOS Inverters.
UNIT-II VLSI Circuits Design Processes
VLSI Design Flow, MOS Layers, Stick Diagrams
Design Rules and Layout, 2 lcm CMOS
Design rules for wires, Contacts
Transistors Layout Diagrams for NMOS
CMOS Inverters and Gates, Scaling of MOS circuits.
UNIT-III Gate Level Design
Logic Gates and Other complex gates, Switch logic
Alternate gate circuits
Time delays, Driving large capacitive loads
Wiring capacitance
Fan - in. Fan - out, Choice of layers.
UNIT-IV Data Path Subsystem
Subsystem Design, Shifters, Adders
ALUs. Multipliers, Parity generators.
Zero/One Detectors. Counters.
Array Subsystem: SRAM, DRAM, ROM
Serial Access Memories, Content
UNIT-V Programmable Logic Design
PLA'S, FPGAS, CPLDS
Standard cell's PAL
Design Approach
Parameters influencing low power design
CMOS Testing
Need for testing
Test Principles
Design Strategies for test
Chip level Test Techniques
Text Books :
1. Essentials of VLSI circuits and systems - Pucknell
2. Essentials of VLSI circuits and systems - Kamran Eshraghian.
3. VLSI Desing- K .Lai Kishore
4. CMOS VLSI Design -Neil H. E
Course Outcomes:
Upon successfully completing the course, the student should be able to:
1. Acquire qualitative knowledge about the fabrication process of integrated circuit using MOS
Transistor.
2. Choose an appropriate inverter depending on specifications required for circuit
3. Draw the layout of any logic circuit which helps to understand and estimate parasitic of any logic circuit.
4. Design different types of logic gates using CMOS inverter and analyze their transfer characteristics.
5. Provide design concepts required to design building blocks of data path using gates.
6. Provide design concepts required to design building blocks of data path using gates.
7. Design simple logic circuit using PLA, PAL, FPGA and CPLD.
8. Understand different types of faults that can occur in a system and learn the concept of testing and adding extra har
improve testability of system.
HOD
DEAN
ctions of stick diagrams,
[Link] Periods per
Unit
I/13
II/12
III/13
IV/13
V/13
extra hardware to
SVS GROUP OF INSTITUTIONS INTEGRATED CAM
SVSIT
LESSON PLAN (II)
DEPARTMENT OF ECE
Name of the Faculty: G. RAMESH
Name of the Subject with code: A40415
Academic Year: 2016-17
UNIT
II
Class& Se
Year& Sem
III
IV
SVS GROUP OF INSTITUTIONS INTEGRATED CAMPUS
SVSIT
LESSON PLAN (II)
DEPARTMENT OF ECE
Name of the Faculty: G. RAMESH
Name of the Subject with code: A40415
Academic Year: 2016-17
Class& Section: EC
Year& Semester: II
TOPIC & SUB TOPIC
LINEAR WAVE SHAPING: Introduction
High pass RC ckt and its response to Sinusoidal,Step & Pulse i/ps
High pass RC ckt and its response to Square and Ramp i/ps
Low pass RC ckt and its response to Sinusoidal,Step & Pulse i/ps
Low pass RC ckt and its response to Square and Ramp i/ps
High pass RC-ckt as Differentiator
Low Pass RC-ckt as Integrator
Attenuators and its application as CRO probe
RL-ckt and its response for Step i/p
RLC-ckt and its response for Step i/p
Ringing circuit
Problem solving
Non-Linear Wave shaping:
Diode Clippers
Transistor clippers
TWO level Clippers
Comparators
Applications of Voltage Comparators
Clamping operation
Clamping circuit taking Sourse & Diode resistances into account
Clamping Circuit Theorem
Practical clamping circuits
Effect of Diode Characteristics on clamping voltages
Synchronized Clamping
SWITCHING CHARACTERISTICS OF DEVICES
Diode as a Switch, Piece wise Linear Diode characteristics
Diode Switching Times
Trasistor as Switch, Break down voltages, Trasistor in saturation
Temperature variation of saturation parameters
Transistor switching times
Silicon Controlled Switch circuits
Sampling Gates: Basic principle: Uni-directional gates
Bi-Directional gates
Four Diode sampling gate
Reduction of pedastal in Gate circuits
Problem solving
MULTIVIBRATORS:Analysis, Operation
Bistable Multivibrator
Mono-stable Multivibrator
Astable Multivibrator
Schmmitt trigger circuit
TIME BASE GENERATORS:General features of Time base signal, methods of generating time base
signal
Basic principles of Time base generators
Transistor Miller Time base Generator
Transistor Bootstrap Time base Generator
Transistor current Time base generators
Methods of Linearity Improvement
Problem solving
SYNCHRONIZATION & FREQUENCY DIVISION
Pulse Synchronization of Relaxation devices
Frequency division in Sweep circuits
stability of relaxation devices
Astable relaxation circuit
Monostable relaxation circuit
Synchronization of sweep circuit with Symmetrical signals
Sine wave frequency division with a sweep circuit
A sinusoidal divider using Regeneration & Modulation
REALIZATION OF LOGIC GATES WITH DIODES & TRANSISTORS: AND, OR, NOT gates
using Diodes
AND, OR, NOT gates using Transistors
DCTL, RTL logic families
DTL & TTL Logic families
CML logic families & comparison of all logic families
TEXT BOOKS:
1. Digital and Switching waveforms- J. Millman H. Taub and Mothiki S. Prakash Rao, 2 Ed., 2008, TMH
2. Solid State Pulse Circuits- David A. Bell, 4 Ed., 2002 PHI
REFERENCE BOOKS:
1. Pulse and Digital Circuits-A. Anand Kumar, 2005, PHI
2. Fundamentals of Pulse and Digital Circuits-Ronald J. Tocci, 3 Ed., 2008
3. Wave generation and shaping- L. Strauss
Faculty
HOD
RATED CAMPUS
Class& Section: ECE
Year& Semester: II-II
Proposed Date Actual Date
12/9/2016
12/10/2016
12/12/2016
12/14/2016
12/15/2016
12/16/2016
12/17/2016
12/19/2016
12/20/2016
12/21/2016
12/22/2016
12/23/2016
12/24/2016
12/26/2016
12/27/2016
12/28/2016
12/29/2016
12/30/2016
12/31/2016
1/2/2017
1/3/2017
1/4/2017
1/5/2017
1/6/2017
1/7/2017
Hours taken
as per the
Topic
Cumulative
Hours taken
1/9/2017
1/10/2017
1/11/2017
1/16/2017
1/17/2017
1/18/2017
1/19/2017
1/20/2017
1/21/2017
1/23/2017
1/24/2017
2008, TMH
1/25/2017
1/27/2017
2/20/2017
2/21/2017
2/22/2017
2/23/2017
2/25/2017
2/27/2017
2/28/2017
3/1/2017
3/2/2017
3/3/2017
3/6/2017
3/7/2017
3/8/2017
3/16/2017
3/17/2017
3/20/2017
3/21/2017
3/22/2017
3/23/2017
3/29/2017
3/30/2017
4/3/2017
4/4/2017
4/5/2017
Principal
SVS GROUP OF INSTITUTIONS INTEGRATED CAMPUS
SVSIT
DEPARTMENT OF ECE
LESSON PLAN-I
Name of the Subject Faculty:
G. RAMESH
Class & Section:
Name of the Subject with Code: Pulse and Digital circuits(A40415)
UNIT
TOPIC
Year & Sem: II
SUB-TOPICS
High pass RC ckt and its response to Sinusoidal,Step & Pulse i/ps
High pass RC ckt and its response to Square and Ramp i/ps
Low pass RC ckt and its response to Sinusoidal,Step & Pulse i/ps
Low pass RC ckt and its response to Square and Ramp i/ps
II
LINEAR WAVE SHAPING
CIRCUITS
High pass RC-ckt as Differentiator
Low Pass RC-ckt as Integrator
Attenuators and its application as CRO probe
RL-ckt and its response for Step i/p
RLC-ckt and its response for Step i/p
Ringing circuit
Diode Clippers
Transistor clippers
TWO level Clippers
Comparators
Applications of Voltage Comparators
NON-LINEAR WAVE SHAPING
CIRCUITS
Clamping operation
Clamping circuit taking Sourse & Diode resistances into account
Clamping Circuit Theorem
Practical clamping circuits
Effect of Diode Characteristics on clamping voltages
Synchronized Clamping
III
SWITCHING
CHARACTERISTICS OF
DEVICES
Diode as a Switch
Piece wise Linear Diode characteristics
Diode Switching Times
Trasistor as Switch, Break down voltages, Trasistor in saturation
Temperature variation of saturation parameters
Transistor switching times
Silicon Controlled Switch circuits
Sampling Gates: Basic principle: Uni-directional gates
Bi-Directional gates
Four Diode sampling gate
Reduction of pedastal in Gate circuits
Analysis, Operation of Multivibrator
Bistable Multivibrator
Mono-stable Multivibrator
Astable Multivibrator
Schmmitt trigger circuit
IV
MULTIVIBRATORS & TIME
BASE GENERATORS
SYNCHRONIZATION &
FREQUENCY DIVISION and
REALIZATION OF LOGIC
GATES WITH DIODES &
TRANSISTORS
General features of Time base signal, methods of generating time base signal
Basic principles of Time base generators
Transistor Miller Time base Generator
Transistor Bootstrap Time base Generator
Transistor current Time base generators
Methods of Linearity Improvement
Pulse Synchronization of Relaxation devices
Frequency division in Sweep circuits
stability of relaxation devices
Astable relaxation circuit
Monostable relaxation circuit
Synchronization of sweep circuit with Symmetrical signals
Sine wave frequency division with a sweep circuit
A sinusoidal divider using Regeneration & Modulation
AND, OR, NOT gates using Diodes
AND, OR, NOT gates using Transistors
DCTL, RTL logic families
DTL & TTL Logic families
CML logic families & comparison of all logic families
TEXT BOOKS:
1. Digital and Switching waveforms- J. Millman H. Taub and Mothiki S. Prakash Rao, 2 Ed., 2008, TMH
2. Solid State Pulse Circuits- David A. Bell, 4 Ed., 2002 PHI
REFERENCE BOOKS:
R1: Pulse and Digital Circuits-A. Anand Kumar, 2005, PHI
R2: Fundamentals of Pulse and Digital Circuits-Ronald J. Tocci, 3 Ed., 2008
R3: Wave generation and shaping- L. Strauss
Signature of Faculty
Signature of HOD
NTEGRATED CAMPUS
F ECE
N-I
Class & Section: ECE
Year & Sem: II-II
Methods of
Teching
Teaching Aid
No. of
Lecturer
Hours
CLASS ROOM
DISCUSSION
BB
BB
BB
BB
2
1
1
1
Objective
Objective
Descriptive
Descriptive
LAB
PPT
Objective
LAB
PPT
NPTEL video
PPT
PPT
NPTEL video
BB
BB
PPT
PPT
1
2
1
1
1
1
1
1
1
Objective
Descriptive
Case study
Case study
Descriptive
Objective
Objective
Objective
Descriptive
NPTEL video
Case study
NPTEL video
PPT
BB
PPT
NPTEL video
NPTEL video
1
2
1
1
1
1
Descriptive
Case study
Descriptive
Case study
Objective
Case study
CLASS ROOM
DISCUSSION
LAB
GUEST LECTURE
CLASS ROOM
DISCUSSION
LAB
GUEST LECTURE
Date of
Reference
Type of
Completion of Book for SubAssignment Works
Unit
Topic
12/23/2016
T1
R1 & R3
1/6/2017
T1
R1 & R3
CLASS ROOM
DISCUSSION
LAB
CLASS ROOM
DISCUSSION
PPT
BB
NPTEL video
PPT
PPT
NPTEL video
NPTEL video
PPT
PPT
PPT
NPTEL video
1
1
1
2
1
1
1
1
1
1
1
Objective
Objective
Descriptive
Descriptive
Case study
Descriptive
Case study
Objective
Descriptive
Case study
Objective
1/24/2017
T2
R2 & R3
CD
LAB VERIFICATION
GUEST LECTURE
CLASS ROOM
DISCUSSION
CLASS ROOM
DISCUSSION
LAB
CLASS ROOM
DISCUSSION
GUEST LECTURE
NPTEL video
NPTEL video
NPTEL video
NPTEL video
PPT
1
1
1
1
1
Descriptive
Descriptive
Descriptive
Descriptive
Case study
NPTEL video
Objective
PPT
NPTEL video
PPT
NPTEL video
PPT
PPT
NPTEL video
PPT
PPT
PPT
NPTEL video
NPTEL video
NPTEL video
BB
BB
NPTEL video
NPTEL video
PPT
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Objective
Case study
Descriptive
Case study
Case study
Descriptive
Descriptive
Objective
Descriptive
Descriptive
Case study
Case study
Descriptive
Objective
Objective
Objective
Objective
Descriptive
3/3/2017
T1
R1 & R3
4/5/2017
T1
R1 & R2
Signature of Principal