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Automated NCL Gate Mapping Methodology

The document proposes a new methodology for mapping multirail logic expressions to a NULL convention logic (NCL) gate library. This new methodology aims to reduce area and improve delay of NCL circuits. It can target any cost function or gate library subset, unlike the original approach which only targeted area reduction. Both methodologies were implemented in Perl and compared, showing the new methodology offers up to 10% smaller area and 39% faster delay depending on the circuit.

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Arjun Reddy Reddy
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4 views1 page

Automated NCL Gate Mapping Methodology

The document proposes a new methodology for mapping multirail logic expressions to a NULL convention logic (NCL) gate library. This new methodology aims to reduce area and improve delay of NCL circuits. It can target any cost function or gate library subset, unlike the original approach which only targeted area reduction. Both methodologies were implemented in Perl and compared, showing the new methodology offers up to 10% smaller area and 39% faster delay depending on the circuit.

Uploaded by

Arjun Reddy Reddy
Copyright
© All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd

Gate Mapping Automation for Asynchronous NULL

Convention Logic Circuits


Dt:

Abstract
Design automation techniques are a key challenge in the widespread application of
timing-robust asynchronous circuit styles. In this paper, a new methodology for mapping
multirail logic expressions to a NULL convention logic (NCL) gate library is proposed. The new
methodology is then compare to another recently proposed mapping approach, demonstrating
that the new methodology can further reduce the area and improve the delay of NCL circuits.
Also, in contrast to the original approach, which only targets area reduction, the new
methodology can target any arbitrary cost function or use any subset of the NCL gate library for
mapping.
In order to automate the new methodology and compare it with the original one, both
methodologies were implemented in the Perl programming language and compared in terms of
mapping performance and runtime. The results show that, depending on the test circuit, the new
methodology can offer up to 10% improvement in area, and 39% improvement in delay.

[Link] REDDY
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