Protel 99SE PCB Design Tutorial
Protel 99SE PCB Design Tutorial
When designing a PCB using the T-Tech Quick Circuit, several key considerations must be kept in mind. First, while the T-Tech can create single and double-sided boards, it cannot handle complicated designs, making it limited in terms of complexity compared to professionally manufactured boards . Designers should ensure that their parts are placed appropriately so that connections cross each other as minimally as possible, which aids in simplifying the routing process . Additionally, since T-Tech boards have exposed copper layers, special attention should be paid to ensuring solderability, such as using oval or oblong pads, which make soldering easier . This approach reduces the risk of damaging the board during soldering and enhances the reliability of the connections. Another significant aspect is ensuring that traces for power signals are wide enough to handle the current, thus avoiding damaging the board .
Protel 99SE's library management system enhances PCB design efficiency through its robust library referencing and global modification capabilities. Footprints, which are essential for translating schematic symbols into physical layout requirements, are managed within designated PCB libraries like the MLL_PCB.DDB for T-Tech boards. Designers can assign footprints to components by accessing these libraries, ensuring accurate representation of physical part dimensions . Through global features, assignments can be streamlined by modifying properties across all similar components simultaneously, such as changing all instances of an MM74HC08 component to a DIP14R footprint . This system not only simplifies the design process by leveraging predefined standards but also assures consistency and reduces potential human error in footprint assignments.
The preparation of a schematic for PCB design in Protel 99SE involves several steps. Initially, component placements are made using the schematic libraries available, such as the Miscellaneous Devices library . Once components are placed, connections are made using wires and net labels for efficient connectivity . Following the placement, annotations are applied using the Tools/Annotate feature, which systematically assigns designators to components based on typically used defaults, ensuring a well-organized schematic . Post-annotation, the schematic undergoes an Electrical Rule Check (ERC) to identify and rectify potential errors like short circuits, ensuring the integrity and functionality of the design before progressing to PCB layout .
In Protel 99SE, Keepout Layers are utilized to define the physical boundaries of the PCB, ensuring that all components fit within a specified area, which is particularly important for manufacturing constraints and design efficiency . For T-Tech operations, these layers are crucial as they help manage the physical layout of the board without extraneous overlap or extension beyond the defined board edge, which could lead to manufacturing issues or increased costs . By setting up a Keepout Layer, designers can ensure that the routing stays within board limits, facilitating efficient use of space and adherence to design specifications, which is especially critical when using T-Tech, where designs are often created with single or double-sided copper layers directly exposed for easier soldering . The use of Keepout Layers thus ensures design viability within the capacity constraints of MIL's prototyping systems.
Finalizing dimensions and layouts in a PCB project using Protel 99SE involves several critical steps and considerations. Initially, the layout process begins with the strategic placement of components in close proximity to minimize trace lengths and crossings . The board dimensions are defined using the Keepout Layer, wherein designers draw a boundary box that encases all components, establishing the physical limitations of the board . Next, design rules are configured, such as setting the routing layer constraints in Design/Rules to determine which PCB layers are utilized, crucial for ensuring manufacturability according to design specifications . Additionally, trace width constraints are adjusted to balance electrical performance with available space, often requiring traces to be widened for high-current paths to prevent overheating and potential damage . Finally, using Protel's AutoRouter, the layout is finalized by routing all connections, ensuring the design adheres to the defined electrical and physical constraints, which are validated through simulation and rule checks before proceeding to fabrication .
Protel 99SE's global feature significantly aids in managing design changes during PCB development by enabling designers to perform batch modifications across multiple components with similar attributes, thus enhancing efficiency and reducing manual errors. For instance, when a footprint needs updating across several identical components, the global feature allows these changes to be applied universally by setting criteria such as a Library Reference and specific properties to be modified . This not only saves time but also ensures consistency across the design. When updating components like multiple logic gates using a single chip part, input characteristics, such as footprint, can be modified globally in one operation, which is critical for maintaining design integrity as changes propagate accurately through the schematic . This level of control is especially beneficial in large-scale projects where extensive component lists require systematic and error-free management.
In Protel 99SE, accommodating both single-sided and double-sided PCB designs entails strategic layer management and component placement. For single-sided designs, components are typically placed on one layer, known as the bottom layer when using T-Tech, which does not support overlay layers . Strategic component placement is critical to minimizing trace crossovers, which makes routing simpler and more efficient for single-sided boards. When a design complexity necessitates a double-sided board, components may be distributed across both top and bottom layers, reducing trace congestion and optimizing board space . Additional considerations include modifying design rules in the AutoRouter to restrict or enable routing on desired layers and adjusting trace width constraints to ensure reliability and performance .
In Protel 99SE schematic design, power and ground symbols play a pivotal role by simplifying the representation of electrical connectivity throughout the circuit. These symbols, known as Power Ports, are essentially net names with special graphical attributes, connecting various circuit nodes without the need for explicit wiring, thus decluttering the schematic and enhancing readability . In terms of PCB manufacturing implications, they define connectivity that must be maintained across different parts of the board, ensuring that critical power and ground paths are preserved through the routing process. Proper use of these symbols can significantly impact the overall board performance and reliability by ensuring efficient power distribution and grounding, crucial for preventing common issues like ground loops .
The inability of T-Tech to perform overlay layers imposes several implications for PCB projects at the Machine Intelligence Lab (MIL). This limitation means that graphical symbols indicating component layouts (typically added on overlay layers) cannot be utilized, potentially complicating the assembly process as the reference to part placement must be managed differently . This constraint affects project planning by requiring designers to rely more heavily on precise documentation and alternative labeling methods to convey component positions effectively. Additionally, without overlay layers, multi-layer designs are restricted to electrical routing layers, which necessitates careful layer management and often results in more challenging routing scenarios where designers must effectively utilize both Top and Bottom copper layers to ensure circuit functionality . These challenges necessitate robust planning during the schematic phase to mitigate potential assembly and routing difficulties.
The Electrical Rule Check (ERC) in Protel 99SE is crucial for validating the schematic design before proceeding to the PCB creation. It ensures that the design is free from common electrical issues such as short circuits or unconnected nodes, serving as a diagnostic tool to prevent potential operational failures. By using the default settings, designers can identify and rectify these issues early in the design process, thereby optimizing the schematic for successful PCB implementation .