64-BIT BINARY COMPARATOR USING DIFFERENT LOGIC

STYLES

BY
KANIKA HANS
ROLL NO (11472005)

Under the Guidance of

[Link] Kaur Dhaliwal

Department of Electronics and Communication Engineering

Punjabi University, Patiala

Contents
1. Introduction
2. Literature Review
3. Research Gap
4. Problem Formulation
5. Objective
6. Research Methodology

7. References

Introduction: In digital system, comparison of two numbers is an arithmetic

operation that determines if one number is greater than, equal to
or less than the other number so comparator is used for this
purpose.
Magnitude comparator is a combinational circuit that compares
two numbers, A and B, and determines their relative magnitudes.
The result of comparison is specified by three binary variables that
indicate whether A>B, A=B, or A< A=B, or A<B.
Comparison is most basic arithmetic operation that compares one
number is greater than, less than or equal to comparator is used
for comparison operation.
Comparator is used for comparison operation.
The logic style used in logic gates basically influences the speed,
power dissipation, size and the wiring complexity.
Circuit size depends on number of transistors and their sizes and
on the wiring complexity.
The wiring complexity is determined by their length and
Size.
The circuit for comparing two n-bit numbers has, 2n inputs & 22n
entries in the truth table.
It has been an important logic block in an ALU and have extensive
applications such as decoding of x86 instructions
It also finds applications in MIMO (Multiple Input Multiple
Output) decoding algorithms require extensive iterations of binary
comparison.

Block diagram of n-bit magnitude comparator

Application of comparator: Used in the address decoding circuitry in computers and

microprocessor based devices to select a specific input/output
device for the storage of data.

In control applications in which the binary numbers representing

physical variables such as temperature, position etc. are
compared with a reference value.

Types of comparator: 2-bit comparator

2-bit comparator compares two number each having two bits
(A1, A0 &B1, B0) and 4 inputs and 16 rows in the truth table.

4-bit Comparator

4-bit comparator compares four number each having four bits

(A3, A2, A1, A0 &B3, B2, B1, B0) and 8 inputs and 128 rows in the
table.

8-bit Comparator
8-bit comparator compares four number each having six bits (A7,
A6,A5,A4,A3,A2,A1,A0 & B7,B6,B5,B4,B3,B2,B1,B0) and 16 inputs
and 65536 rows in the truth table

64-bit Binary Comparator: 64-bit binary comparator compares two numbers each heaving 64
bits (A63 to A0 & B63 to B0).
Truth table has 128 inputs & 2^128 entries.
64-bit comparator is composed of eight 8-bit comparators and
one final 8-bit comparator.

The 64-bits are divided into eight bytes which are evaluated at the
same time, and then the 8-bit comparator produces the final
output.

Schematic of 64-bit binary Comparator

CMOS Technology
It consists of one NMOS & one transistor.
If input A=0 (logic low) then both gates are at zero potential &
PMOS is on & provide low impedance path from VDD to output
(Y). Therefore output (Y) approaches to high level of VDD.

Symbol of CMOS
If input A=1(logic high) then both gates are at higher potential &
NMOS is on & provide high impedance path from ground to
output (Y). Therefore output (Y) approaches to low level of 0V.
Pull up network has only PMOS circuitry and Pull down network
has only NMOS circuitry.

 The function of PUN is to provide connection between output and

VDD.
The function of PDN is to provide connection between output and
GND.
PUN and PDN networks are constructed in a way that one and
only one network is conducting at a time.
Number of transistors for N-input logic gate is 2N.
Any logic function can be realized by NMOS pull-down and PMOS
pull up network. Number of transistors for N-input logic gate is
2N.

Advantages of CMOS Technology: Gates are very simple. The basic gate is an inverter, which is only
two transistors. This together with the low power means it lends
itself well to dense integration. Or conversely get a lot of logic for
the size, cost and power.
low power consumption
High degree of noise immunity
High input impedance. The input signal is driving electrodes with a

layer of insulation (the metal oxide) between them and what they
are controlling. This gives them a small amount of capacitance,
but virtually infinite resistance. The current into or out of CMOS
input held at one level is just leakage usually 1 nanoampere or
less.
The outputs actively drive both ways.
Large Fan Out

Application:
Creating Images
The CMOS sensor converts the light that enters the lens into electrical
signals, which can then be stored easily. A CMOS sensor will create
lower quality images than a CCD Sensor, but this is acceptable in some
circumstances.

 To eliminate the cross-talk between high frequency RF and digital

mixed signal devices on the same die.
CMOS sensors are much cheaper to produce, and the power
savings are also desirable for digital cameras.
They can be used for RF circuits, mixed signal devices and as
transmission gates.

Tree Based Comparator:64-bit comparator represents tree based structure which is inspired
by fact that G (generate) and P (propagate) signal can be defined for
binary comparisons, similar to G (generate) and P (propagate) signals
for binary additions

For A<B- BBig, EQ is 1, 0. For A=B-BBig, EQ is 0, 1. Hence, For A>B- BBig,

EQ is 0, 0. Where BBig is defined as output A less than B (A_LT_B).

Where A &B are binary inputs, Cin is carry input, Cout is carry output,
and G & P are generate & propagate signals, respectively. After
comparing equations (1) & (3)

Cin can be considered as G0. Since for static logic equation (1)
requires tall transistor stack height, hence, an encoding scheme is
employed to solve this problem.

Where i=0.63 put these two values from equations (7) & (8) in
equations (1) & (2)

Where j = 0..31. G & P signals

Similarly, for 64-bit comparator, BBig & EQ can be computed as:

Diagram of Tree based Structure

Parallel Prefix Tree:The prefix tree structures area and power consumption can be
improved by supports two input multiplexers at each level and
generate-propagate logic cells on the first level which takes advantage
of ones complement addition. Using this logic composition, a prefix
tree requires six levels for the most common comparison bit width of
64-bit suffers from high power consumption due to every cell in the
structure being active , regardless of the input operands values.
The structure can perform only greater than or less -than
comparisons and not equality. To improve the speed and reduce power
consumption, several designs rely on pipelining and power down
mechanisms to reduce switching activity with respect to the actual
input operands bit values. One design uses all N transistor (ANT)
circuits to compensate for high fan in with high pipeline throughput.
A 64-bit comparator requires only three pipeline cycles using a
multiphase locking scheme

Block diagram of comparator architecture consisting of comparison

resolution module comparison connected to a decision module

Parallel prefix tree structure is a novel MSB to LSB that performs

bitwise comparison of two N-bit operands A and B, denoted as AN-1,
AN-2,.,A0 and BN-1, BN-2,.,B0, where the subscripts range
from N-1 for the MSB to 0 for the LSB.
The comparison resolution module performs the bitwise comparison
from left to right, such that the comparison logics computation is
triggered only if all bits of greater significance are equal.
The parallel structure encodes the bitwise comparison results into two
N-bit buses, the left bus and the right bus, each of which stores the
partial comparison result as each bit position is evaluated
If Ak > Bk, then leftk = 1 and rightk = 0
If Ak < Bk , then leftk = 0 and rightk = 1
If Ak = Bk , then leftk = 0 and rightk = 0.
In addition to reduce switching activities, as soon as a bitwise
comparison is not equal , the bitwise comparison of every bit of lower
significance is terminated and all such positions are set to zero on both
buses, thus there is never more than one high bit on either bus.

The decision module uses two OR- networks to output the final
comparison decision based on separate OR- scans of all of the bits on
the right bus.
If LR = 00, then A=B
If LR = 10 then A>B,
If LR = 01 then A<B, and LR =11 is not possible.

An 8-bit comparison of input operands A= 01011101 and B = 01101001

in the first step, a parallel prefix tree structure generates the encoded
data on the left bus and right bus for each pair of corresponding bits
from A and B.

Diagram of Parallel Prefix Tree

In this example , A7 = 0 and B7 = 0 encodes as left7 = right7=0, A6 = 1,

and B6 = 1 encodes as left6=right6=0, and A5 = 0 and B5=1 encodes
left5 = 0 and right5 = 1.
At this point, the bits are unequal, the comparison terminates and a
final comparison decision can be made on the first three bits evaluated.
The parallel prefix structure forces all the first three bits of lesser
significance on each bus to o, regardless of the remaining bits values in
the operands, in the second step, the OR-networks performs the ORscans, resulting in 0 and 1, and the final comparison decision is A>B

Literature Review
In 2012 Manoj Sachdev [Link] designed A Low Power High
Performance Single Cycle Tree Based 64-Bit Binary
Comapratorwith minimum delay and the speed of the circuit is
2.7x better performance but number of transistor increased
In 2013 Anjuli and Satyajit Anand designed High Speed 64-bit
Binary Comparator with low power consumption and delay is
reduced 6.8% and number of transistor count increased.
In 2013 Anjuli and Satyajit anand designed High Speed 64-bit
Tree based CMOS Comparator with low power consumption and
delay is reduced 6.8% and number of transistor count increased
In 2013 Saleh Afdal Hafeez designed Scalable Digital CMOS
Comparator Using Parallel Prefix Tree with minimum delay and
delay reduced up to 461ps and number of transistor count
decreased.
In 2013 Jyothis Kurain designed Improved 64-bit Binary
Comparator with minimum power consumption and power
reduced up to 722 mw and delay increased.
In 2013 Anjuli and Satyajit anand designed High Speed 64-bit
Binary Comparator with low power consumption and number of
transistor count increased.
In 2014 Deepak Sharma designed A 65nm Parallel Prefix High
Speed 64-bit Binary Comparator with low power consumption
and power consumed up to 2.31 watt and number of transistor
increased.

 In 2014 Manas Ranjan Jena [Link] designed A Low Power 64-bit

Digital Comparator Using CMOS logic with low power
consumption and delay increased.
In 2015 [Link] and [Link] designed Design of Efficient
64-bit Comparator Using Modified Gate Diffusion Input Logic
with Minimum Delay and delay is reduced 1.23% and number of
transistor increased.

Research Gaps

In 2013 Anjuli and Satyajit anand designed 64-bit comparator

using CMOS technology with minimum power consumption and
number of transistor per area but on the other side delay
increased.
In 2014 Deepak Sharma designed 64-bit comparator using parallel
prefix tree based structure with minimum delay and average
power consumption but on the other side number of transistor
count increased.

In 2013 Jyothis Kurain designed 64-bit comparator using tree

Based Structure with average power consumption and less
number of transistor but on the other side delay increased.

Problem Formulation:Area can be reduced by

Decreasing the number of transistor count
Using different logic style
Speed can be improved by
Reducing delay
Power consumption can be reduced by

Using one block at a time

Objective: To minimize power consumption

To reduce the area of the circuit in terms of transistor count so
that the circuit become less complex.
To improve the speed of the circuit
To compare proposed comparator with existing comparator

Research Methodology: Tanner EDA Tool

Technology
1. 65nm
2. 90nm
3. 180nm

References:1. Anjuli and Satyajit High Speed 64-bit CMOS binary Comparator
IJRET Journal Binary Comparator,Vol. 2,pp202-205, (feb 2013)
2. M Morris mano Digital Design. (Pearson Education Asia .3rd Ed,
2002).
3. [Link] and W. Fichtner, Low power Logic Style : CMOS
versus Pass Transistor Logic IEEE JOURNAL Solid State Circuits,
Vol.32, No.7, pp1079-1090,july 1997.
4. [Link] and [Link] Integrated Circuit, Analysis and
Design(Tata McGraw-Hill, 3rd Ed,2003)
5. [Link] and J-S. Wang, High- Performance and Power
Efficient CMOS Comparators, IEEE [Link] State Circuits, vol. 38,
n0.2 , pp.254-262,Feb 2003
6. A. Bellaouar and Mohamed I. Elmasry, Low Power Digital VLSI
Design : Circuits and Systems,Kluwer Academic Publishers, 2nd Ed,
1995
7. Pierce Chuang , David Li and Manoj Sachdev, Fellow, IEEE- A Low
Power High- Performance Single Cycle Tree Based 64-bit Binary
Comparator IEEE Transactions On Circuits and Systems II: Express
Briefs , Vol.59, No 2, Feburary 2012