Intel Processors Comparison
Data
Bus
4
Address
Bus
4
8008
4040
14
External
4
8080
16
Intel
Type
4004
Queue
Cache
Clock
Pin
Remarks
Year
740KHz
16
1971
0.5 0.8 MHz
18-DIP
1972
500 740 KHz
24-DIP
2 MHz
40-DIP
16 Registers
1974
46 Instructions
Needs 20 or more additional devices to
form a functional CPU
24 Registers
60 Instructions
1974
Needs 2 more additional devices to
form a functional CPU
a) System Controller
b)
c)
8085
16
8086
16
16
20
8088
80186
16
16
20
3, 5 & 6MHz
40-DIP
1977
6 Byte
5 10 MHz
40-DIP
1978
6 Byte
5 10 MHz
6 12 MHz
40-DIP
68-PLCC
100-PQFP
68-PGA
1979
1982
80286
80386 DX
16
32
16
32
24
32
6 Byte
16 Byte
6 25 MHz
12 40 MHz
68-PGA 68- 1982
PLCC
68CLCC
132-PGA
1986
Serial I/O Lines
CLK Oscillator
Requires +5V, -5V & +12V supply
Separate Address & Data Lines
Full-Fledged CPU
Only +5V Supply
Four Segments - CS, DS, SS, ES of
64KB
Modes MIN & MAX
Four Segments - CS, DS, SS, ES of
64KB
Modes MIN & MAX
Four Segments - C S, DS, SS, ES of
64KB
Modes REAL & PROTECTED
It cannot switch easily back & forth
b/w Real & Protected Modes
Non-Multiplexed Address Bus
Six Segments - CS, DS, SS, ES, FS,
GS can be as large as 4GB
Modes Virtual 8086, REAL &
PROTECTED
It can switch easily back & forth b/w
Real & Protected Modes using Virtual
8086 Mode
80386 SX
80486
Pentium
32
32
32
16
32
64
24
32
32
16 Byte
32 Byte
12 40 MHz
8KB Data and Instruction 16 100 MHz
cache
100-FP
168-PGA
196-PQFP
1986
1989
Data - 8KB
Instruction 8KB
237-PGA
1993
60 300 MHz
Four Memory Banks
Available in 2 versions SX and DX
Super Scalar Architecture (Two Pipe
Lines, executes more than 1
instruction per clock cycle)
Faster FPU
Pentium Pro
Pentium II
32
32
64
64
32/36
36
L1 Cache:
Data - 8KB
Instruction 8KB
L2 Cache: 256/512KB
Data - 16KB
Instruction 16KB
L2 Cache: 512KB
150 200 MHz
387-PGA
233 452 MHz
1995
1997
Pentium III
32
64
36
L1 Cache:
Data - 16KB
Instruction 16KB
L2 Cache: 512KB
450 MHz 1.4 GHz
370-PGA
1999
Pentium 4
32
64
36
L1 Cache:
Data - 16KB
Instruction 16KB
L2 Cache: 1MB
1.3 3.8 GHz
423-PGA
2000
478-FCPGA
On-Chip FPU (only in DX version)
Branch prediction logic
5-stage pipe line
MMX(Multimedia extension) on-chip
Power supply (3.3V DC)
System management mode (SMM)
Versions: Full blown Pentium: 64-bit
data bus & Pentium overdrive (P24T):
32-bit data bus
Out-of-order execution
Versions: 256 KB L2 cache & 512K L2
cache
It does not come as an IC as earlier
processors. It comes on PCB.
Version: Celeron - without L2 cache &
Xenon - with 512 KB or 1 MB or 2 MB
L2 cache
Early versions of Pentium III is PCB
based with non-blocking 512 KB Level
2 cache. Later versions such as
Coppermine are IC based with 256
KB Level 2 cache.
Hyper-Threading technology
Hyper-Pipelined
technology:
Advanced dynamic execution & very
deep out-of-order execution.
Enhanced Floating Point & MMX units
Two power management capabilities:
SMM & Multiple low power states.
Pentium Dual
Core
64
Core i7
64
Core i5
64
Core i3
64
64
36
L1 Cache:
Data - 16KB
Instruction 16KB
L2 Cache: 2MB
L1 Cache:
Data - 32KB
Instruction 32KB
L2 Cache: 256KB
L3 Cache: 12MB
L1 Cache:
Data 32KB
Instruction 32KB
L2 Cache: 2 X 256KB
L3 Cache: 8MB
L1 Cache:
Data 32KB
Instruction 32KB
L2 Cache: 2 X 256KB
L3 Cache: 4MB
Tukwila,
Tolapai,
Moorestown
Note: PGA - Pin Grid Array
FCPGA - Flip-Chip Pin Grid Array
CPGA - Ceramic Pin Grid Array
OPGA - Organic Pin Grid Array
CLCC - Ceramic Lead less Chip Carrier
PLCC - Plastic Leaded Chip Carrier
FP - Flat Pack
PQFP - Plastic Quad Flat Pack
2.5 3.33 GHz
2006
2.66 3.33 GHz
2010
3.2 3.6 GHz
2010
3.2 3.6 GHz
2010
Upcoming