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Unit 1
Basic MOS Technology

[Link]

Transistor was first invented by [Link], Walter Brattain and John Bardeen
of Bell Labratories. In 1961, first IC was introduced.
Levels of Integration:i)
ii)
iii)
iv)
v)

SSI:- (10-100) transistors => Example: Logic gates

MSI:- (100-1000) => Example: counters
LSI:- (1000-20000) => Example:8-bit chip
VLSI:- (20000-1000000) => Example:16 & 32 bit up
ULSI:- (1000000-10000000) => Example: Special processors, virtual reality
machines, smart sensors

Moores Law:The number of transistors embedded on the chip doubles after every one and a half
years. The number of transistors is taken on the y-axis and the years in taken on the xaxis. The diagram also shows the speed in MHz. the graph given in figure also shows the
variation of speed of the chip in MHz.

Figure 1. Moores law

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The graph in figure2 compares the various technologies available in ICs.

Figure [Link] of available technologies

From the graph we can conclude that GaAs technology is better but still it is not
used because of growing difficulties of GaAs crystal. CMOS looks to be a better
option compared to nMOS since it consumes a lesser power. BiCMOS technology is
also used in places where high driving capability is required and from the graph it
confirms that, BiCMOS consumes more power compared to CMOS.
Levels of Integration:i)
ii)
iii)
iv)
v)

Small Scale Integration:- (10-100) transistors => Example: Logic gates

Medium Scale Integration:- (100-1000) => Example: counters
Large Scale Integration:- (1000-20000) => Example:8-bit chip
Very Large Scale Integration:- (20000-1000000) => Example:16 & 32 bit up
Ultra Large Scale Integration:- (1000000-10000000) => Example: Special
processors, virtual reality machines, smart sensors

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Basic MOS Transistors:
Why the name MOS?
We should first understand the fact that why the name Metal Oxide
Semiconductor transistor, because the structure consists of a layer of Metal (gate), a
layer of oxide (Sio2) and a layer of semiconductor. Figure 3 below clearly tell why
the name MOS.

.
Figure [Link] section of a MOS structure

We have two types of FETs. They are Enhancement mode and depletion mode
transistor. Also we have PMOS and NMOS transistors.
In Enhancement mode transistor channel is going to form after giving a proper
positive gate voltage. We have NMOS and PMOS enhancement transistors.
In Depletion mode transistor channel will be present by the implant. It can be
removed by giving a proper negative gate voltage. We have NMOS and PMOS
depletion mode transistors.
N-MOS enhancement mode transistor:This transistor is normally off. This can be made ON by giving a positive gate
voltage. By giving a +ve gate voltage a channel of electrons is formed between source
drain.

P-Mos enhancement mode transistors:This is normally on. A Channel of Holes can be performed by giving a ve gate
voltage. In P-Mos current is carried by holes and in N-Mos its by electrons. Since the
mobility is of holes less than that of electrons P-Mos is slower.

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N-MOS depletion mode transistor:This transistor is normally ON, even with Vgs=0. The channel will be implanted
while fabricating, hence it is normally ON. To cause the channel to cease to exist, a
ve voltage must be applied between gate and source.

NOTE: Mobility of electrons is 2.5 to 3 times faster than holes. Hence P-MOS devices
will have more resistance compared to NMOS.
Enhancement mode Transistor action:-

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Figure 8(a)(b)(c) Enhancement mode transistor with different Vds values

To establish the channel between the source and the drain a minimum voltage (Vt)
must be applied between gate and source. This minimum voltage is called as Threshold
Voltage. The complete working of enhancement mode transistor can be explained with
the help of diagram a, b and c.
a) Vgs > Vt
Vds = 0
Since Vgs > Vt and Vds = 0 the channel is formed but no current flows between
drain and source.
b) Vgs > Vt
Vds < Vgs - Vt
This region is called the non-saturation Region or linear region where the drain
current increases linearly with Vds. When Vds is increased the drain side becomes more
reverse biased(hence more depletion region towards the drain end) and the channel starts
to pinch. This is called as the pinch off point.
c) Vgs > Vt
Vds > Vgs - Vt
This region is called Saturation Region where the drain current remains almost
constant. As the drain voltage is increased further beyond (Vgs-Vt) the pinch off point
starts to move from the drain end to the source end. Even if the Vds is increased more
and more, the increased voltage gets dropped in the depletion region leading to a constant
current.
The typical threshold voltage for an enhancement mode transistor is given by Vt = 0.2 *
Vdd.

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Depletion mode Transistor action:-

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We can explain the working of depletion mode transistor in the same manner, as that of
the enhancement mode transistor only difference is, channel is established due to the
implant even when Vgs = 0 and the channel can be cut off by applying a ve voltage
between the gate and source. Threshold voltage of depletion mode transistor is around
0.8*Vdd.

NMOS Fabrication:

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Figure 9 NMOS Fabrication process steps

The process starts with the oxidation of the silicon substrate (Fig. 9(a)), in which a
relatively thick silicon dioxide layer, also called field oxide, is created on the surface
(Fig. 9(b)). Then, the field oxide is selectively etched to expose the silicon surface on
which the MOS transistor will be created (Fig. 9(c)). Following this step, the surface
is covered with a thin, high-quality oxide layer, which will eventually form the gate
oxide of the MOS transistor (Fig. 9(d)). On top of the thin oxide, a layer of
polysilicon (polycrystalline silicon) is deposited (Fig. 9(e)). Polysilicon is used both
as gate electrode material for MOS transistors and also as an interconnect medium in
silicon integrated circuits. Undoped polysilicon has relatively high resistivity. The
resistivity of polysilicon can be reduced, however, by doping it with impurity atoms.
After deposition, the polysilicon layer is patterned and etched to form the
interconnects and the MOS transistor gates (Fig. 9(f)). The thin gate oxide not
covered by polysilicon is also etched away, which exposes the bare silicon surface on
which the source and drain junctions are to be formed (Fig. 9(g)). The entire silicon
surface is then doped with a high concentration of impurities, either through diffusion
or ion implantation (in this case with donor atoms to produce n-type doping). Figure
9(h) shows that the doping penetrates the exposed areas on the silicon surface,
ultimately creating two n-type regions (source and drain junctions) in the p-type
substrate. The impurity doping also penetrates the polysilicon on the surface,
reducing its resistivity. Note that the polysilicon gate, which is patterned before
doping actually defines the precise location of the channel region and, hence, the
location of the source and the drain regions. Since this procedure allows very precise
positioning of the two regions relative to the gate, it is also called the self-aligned

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process. Once the source and drain regions are completed, the entire surface is again
covered with an insulating layer of silicon dioxide (Fig. 9 (i)). The insulating oxide
layer is then patterned in order to provide contact windows for the drain and source
junctions (Fig. 9 (j)). The surface is covered with evaporated aluminum which will
form the interconnects (Fig. 9 (k)). Finally, the metal layer is patterned and etched,
completing the interconnection of the MOS transistors on the surface (Fig. 9 (l)).
Usually, a second (and third) layer of metallic interconnect can also be added on top
of this structure by creating another insulating oxide layer, cutting contact (via) holes,
depositing, and patterning the metal.
CMOS fabrication: When we need to fabricate both nMOS and pMOS
transistors on the same substrate we need to follow different processes. The three
different processes are,P-well process ,N-well process and Twin tub process.
P-WELL PROCESS:

Figure 10 CMOS Fabrication (P-WELL) process steps

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The p-well process starts with a n type substrate. The n type substrate can be used
to implement the pMOS transistor, but to implement the nMOS transistor we
need to provide a p-well, hence we have provided he place for both n and pMOS
transistor on the same n-type substrate.

Mask sequence.
Mask 1:
Mask 1 defines the areas in which the deep p-well diffusion takes place.
Mask 2:
It defines the thin oxide region (where the thick oxide is to be removed or
stripped and thin oxide grown)
Mask 3:
Its used to pattern the polysilicon layer which is deposited after thin oxide.
Mask 4:
A p+ mask (anded with mask 2) to define areas where p-diffusion is to take
place.
Mask 5:
We are using the ve form of mask 4 (p+ mask) It defines where n-diffusion is
to take place.
Mask 6:
Contact cuts are defined using this mask.
Mask 7:
The metal layer pattern is defined by this mask.
Mask 8:
An overall passivation (overglass) is now applied and it also defines openings
for accessing pads.
The cross section below shows the CMOS pwell inverter.
.

Figure 11 CMOS inverter (P-WELL)

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N-WELL PROCESS:
In the following figures, some of the important process steps involved in the
fabrication of a CMOS inverter will be shown by a top view of the lithographic masks
and a cross-sectional view of the relevant areas.

The n-well CMOS process starts with a moderately doped (with impurity
concentration typically less than 1015 cm-3) p-type silicon substrate. Then, an initial
oxide layer is grown on the entire surface. The first lithographic mask defines the n-well
region. Donor atoms, usually phosphorus, are implanted through this window in the
oxide. Once the n-well is created, the active areas of the nMOS and pMOS transistors can
be defined. Figures 12.1 through 12.6 illustrate the significant milestones that occur
during the fabrication process of a CMOS inverter.

Figure-12.1: Following the creation of the n-well region, a thick field oxide is grown in
the areas surrounding the transistor active regions, and a thin gate oxide is grown on top
of the active regions. The thickness and the quality of the gate oxide are two of the most
critical fabrication parameters, since they strongly affect the operational characteristics of
the MOS transistor, as well as its long-term reliability.

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Figure-12.2: The polysilicon layer is deposited using chemical vapor deposition (CVD)
and patterned by dry (plasma) etching. The created polysilicon lines will function as the
gate electrodes of the nMOS and the pMOS transistors and their interconnects. Also, the
polysilicon gates act as self-aligned masks for the source and drain implantations that
follow this step.

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Figure-12.3: Using a set of two masks, the n+ and p+ regions are implanted into the
substrate and into the n- well, respectively. Also, the ohmic contacts to the substrate and
to the n-well are implanted in this process step.

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Figure-12.4: An insulating silicon dioxide layer is deposited over the entire wafer using
CVD. Then, the contacts are defined and etched away to expose the silicon or polysilicon
contact windows. These contact windows are necessary to complete the circuit
interconnections using the metal layer, which is patterned in the next step.

Figure-12.5: Metal (aluminum) is deposited over the entire chip surface using metal
evaporation, and the metal lines are patterned through etching. Since the wafer surface is
non-planar, the quality and the integrity of the metal lines created in this step are very
critical and are ultimately essential for circuit reliability.

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Figure-12.6: The composite layout and the resulting cross-sectional view of the chip,
showing one nMOS and one pMOS transistor (built-in n-well), the polysilicon and metal
interconnections. The final step is to deposit the passivation layer (for protection) over
the chip, except for wire-bonding pad areas.
Twin-tub process:
Here we will be using both p-well and n-well approach. The starting point is a n-type
material and then we create both n-well and p-well region. To create the both well we
first go for the epitaxial process and then we will create both wells on the same substrate.

Figure 13 CMOS twin-tub inverter

NOTE: Twin tub process is one of the solutions for latch-up problem.

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Bi-CMOS technology: - (Bipolar CMOS)

The driving capability of MOS transistors is less because of limited current
sourcing and sinking capabilities of the transistors. To drive large capacitive loads we can
think of Bi-Cmos technology.
This technology combines Bipolar and CMOS transistors in a single integrated
circuit, by retaining benefits of bipolar and CMOS, BiCMOS is able to achieve VLSI
circuits with speed-power-density performance previously unattainable with either
technology individually.
Characteristics of CMOS Technology
Lower static power dissipation
Higher noise margins
Higher packing density lower manufacturing cost per device
High yield with large integrated complex functions
High input impedance (low drive current)
Scaleable threshold voltage
High delay sensitivity to load (fan-out limitations)
Low output drive current (issue when driving large capacitive loads)
Low transconductance, where transconductance, gm Vin
Bi-directional capability (drain & source are interchangeable)
A near ideal switching device
Characteristics of Bipolar Technology
Higher switching speed
Higher current drive per unit area, higher gain
Generally better noise performance and better high frequency characteristics
Better analogue capability
Improved I/O speed (particularly significant with the growing importance of
package limitations in high speed systems).
high power dissipation
lower input impedance (high drive current)
low voltage swing logic
low packing density
low delay sensitivity to load
high gm (gm Vin)
high unity gain band width (ft) at low currents
essentially unidirectional
From the two previous paragraphs we can get a comparison between bipolar and
CMOS technology.

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The diagram given below shows the cross section of the BiCMOS process which
uses an npn transistor.

Figure 14 Cross section of BiCMOS process

The figure below shows the layout view of the BiCMOS process.

Fig.15. Layout view of BiCMOS process

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The graph below shows the relative cost vs. gate delay.

[Link]

Fig.16. cost versus delay graph

Production of e-beam masks:

In this topic we will understand how we are preparing the masks using e-beam
technology. The following are the steps in production of e-beam masks.

Starting materials is chromium coated glass plates which are coated with e-beam
sensitive resist.
E-beam machine is loaded with the mask description data.
Plates are loaded into e-beam machine, where they are exposed with the patterns
specified by mask description data.
After exposure to e-beam, plates are introduced into developer to bring out
patterns.
The cycle is followed by a bake cycle which removes resist residue.
The chrome is then etched and plate is stripped of the remaining e-beam resist.

We use two types of scanning, Raster scanning and vector scanning to map the
pattern on to the mask.
In raster type, e-beam scans all possible locations and a bit map is used to turn the ebeam on and off, depending on whether the particular location being scanned is to be
exposed or not.

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In vector type, beam is directed only to those location which are to be exposed.
Advantages e-beam masks:

Tighter layer to layer registration;

Small feature sizes

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FORMAT-1B

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Scaling of MOS Circuits

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CONTENTS
1. What is scaling?
2. Why scaling?
3. Figure(s) of Merit (FoM) for scaling
4. International Technology Roadmap for Semiconductors
(ITRS)
5. Scaling models
6. Scaling factors for device parameters
7. Implications of scaling on design
8. Limitations of scaling
9. Observations
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Scaling of MOS Circuits
[Link] is Scaling?
Proportional adjustment of the dimensions of an electronic device while
maintaining the electrical properties of the device, results in a device either larger or
smaller than the un-scaled device. Then Which way do we scale the devices for VLSI?
BIG and SLOW or SMALL and FAST? What do we gain?
[Link] Scaling?...
Scale the devices and wires down, Make the chips fatter functionality, intelligence,
memory and faster, Make more chips per wafer increased yield, Make the end user
Happy by giving more for less and therefore, make MORE MONEY!!
[Link] for Scaling
Impact of scaling is characterized in terms of several indicators:
o Minimum feature size
o Number of gates on one chip
o Power dissipation
o Maximum operational frequency
o Die size
o Production cost
Many of the FoMs can be improved by shrinking the dimensions of transistors and
interconnections. Shrinking the separation between features transistors and wires
Adjusting doping levels and supply voltages.
3.1 Technology Scaling
Goals of scaling the dimensions by 30%:
Reduce gate delay by 30% (increase operating frequency by 43%)
Double transistor density
Reduce energy per transition by 65% (50% power savings @ 43% increase in frequency)
Die size used to increase by 14% per generation
Technology generation spans 2-3 years

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Figure1 to Figure 5 illustrates the technology scaling in terms of minimum feature size,
transistor count, prapogation delay, power dissipation and density and technology
generations.

M inim um Feature Size (m icron)

10

10

10

10

-1

-2

10
1960

1970

1980

1990

2000

2010

Year

Figure-1:Technology Scaling (1)

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Figure-2:Technology Scaling (2)

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Propagation Delay
Figure-3:Technology Scaling (3)

rs
ea

0.1
0.01
80

MPU
DSP
85

90
Year

(a) Power dissipation vs. year.

95

0.7

y
/3
4
x

1000

100

Power Dissipation (W)

10

ears

Power Density (mW/mm2 )

x1.4 / 3 y

100

10

Scaling Factor
normalized by 4 m design rule
(b) Power density vs. scaling factor.

Figure-4:Technology Scaling (4)

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Technology Generations

Figure-5:Technology generation

4.

International Technology Roadmap for Semiconductors (ITRS)

Table 1 lists the parameters for various technologies as per ITRS.

Table 1: ITRS

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[Link] Models

Full Scaling (Constant Electrical Field)
Ideal model dimensions and voltage scale together by the same scale factor

Fixed Voltage Scaling
Most common model until recently only the dimensions scale, voltages remain constant

General Scaling
Most realistic for todays situation voltages and dimensions scale with different factors
[Link] Factors for Device Parameters
Device scaling modeled in terms of generic scaling factors:
1/ and 1/
1/: scaling factor for supply voltage VDD and gate oxide thickness D

1/: linear dimensions both horizontal and vertical dimensions

Why is the scaling factor for gate oxide thickness different from other linear horizontal
and vertical dimensions? Consider the cross section of the device as in Figure 6,various
parameters derived are as follows.

Figure-6:Technology generation

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Gate area Ag
Ag = L *W

Where L: Channel length and W: Channel width and both are scaled by 1/
Thus Ag is scaled up by 1/2

Gate capacitance per unit area Co or Cox

Cox = ox/D
Where ox is permittivity of gate oxide(thin-ox)= inso and D is the gate oxide thickness
scaled by 1/
1
=
Thus Cox is scaled up by
1

Gate capacitance Cg C g = Co * L *W
Thus Cg is scaled up by * 1/ 2 =/ 2

Parasitic capacitance Cx

Cx is proportional to Ax/d
where d is the depletion width around source or drain and scaled by 1/
Ax is the area of the depletion region around source or drain, scaled by (1/ 2 ).
Thus Cx is scaled up by {1/(1/)}* (1/ 2 ) =1/

Carrier density in channel Qon

Qon = Co * Vgs
where Qon is the average charge per unit area in the on state.
Co is scaled by and Vgs is scaled by 1/
Thus Qon is scaled by 1

Channel Resistance Ron

Ron =

L
1
*
W Qon *

Where = channel carrier mobility and assumed constant

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Thus Ron is scaled by 1.

Gate delay Td
Td is proportional to Ron*Cg
1

Td is scaled by

* =

Maximum operating frequency fo

fo =

W CoVDD
*
L
Cg

fo is inversely proportional to delay Td and is scaled by

1 1
=
2

Saturation current Idss

I dss =

Co W
2
* * (Vgs Vt )
2
L

Both Vgs and Vt are scaled by (1/ ). Therefore, Idss is scaled by

Current density J
I dss
where A is cross sectional area of the
Current density, J = A
Channel in the on state which is scaled by (1/ 2).
So, J is scaled by

1
1

Switching energy per gate Eg

E = 1 C V 2
g
g DD
2
So Eg is scaled by

1
1
* 2 = 2
2

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Power dissipation per gate Pg

Pg = Pgs + Pgd

Pg comprises of two components: static component Pgs and dynamic component Pgd:
Where, the static power component is given by:

And the dynamic component by:

2
V DD
Pgs =
R on

Pgd = E g f o

Since VDD scales by (1/) and Ron scales by 1, Pgs scales by (1/2).
Since Eg scales by (1/2 ) and fo by (2 /), Pgd also scales by (1/2). Therefore, Pg
scales by (1/2).

Power dissipation per unit area Pa

1

P g 2 2
Pa =
=
=
Ag 1 2
2

Power speed product PT

PT = Pg * Td =

1
1
= 2
2
2

6.1 Scaling Factors Summary

Various device parameters for different scaling models are listed in Table 2 below.
Table 2: Device parameters for scaling models
NOTE: for Constant E: =; for Constant V: =1
Parameters
VDD
L
W
D
Ag
Co (or Cox)
Cg
Cx
Qon
Ron

General
(Combined V
Description
and
Dimension)
1/
Supply voltage
Channel length
1/
Channel width
1/
Gate oxide thickness 1/
2
Gate area
1/
Gate capacitance per
unit area
Gate capacitance
/2
Parsitic capacitance 1/
1
Carrier density
1
Channel resistance

Constant E

Constant V

1/
1/
1/
1/
2
1/

1
1/
1/
1
2
1/
1

1/
1/

1/
1/

1
1

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1
10

1/
1/
1
Idss
Saturation
current
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Constant V

Parameters

Ac
J
Vg
Eg
Pg
N
Pa
Td
fo
PT

Description
Conductor cross
section area
Current density
Logic 1 level
Switching energy
Power dissipation per
gate
Gates per unit area
Power dissipation per
unit area
Gate delay
Max. operating
frequency
Power speed product

General
Constant E
(Combined V
and
Dimension)
2
2
1/
1/

1/

2 /
1/

1/

2
1

1 / 2

1 / 3

1/

1/

1/
1

2
2 / 2

2
1

2
2

/ 2

1/

2 /

1/
2

1 / 2

1 / 3

1/

[Link] of Scaling

Improved Performance

Improved Cost

Interconnect Woes

Power Woes

Productivity Challenges

Physical Limits

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7.1Cost Improvement
Moores Law is still going strong as illustrated in Figure 7.

Figure-7:Technology generation

7.2:Interconnect Woes
Scaled transistors are steadily improving in delay, but scaled wires are holding
constant or getting worse.
SIA made a gloomy forecast in 1997
Delay would reach minimum at 250 180 nm, then get
worse because of wires
But
For short wires, such as those inside a logic gate, the wire RC delay is negligible.
However, the long wires present a considerable challenge.
Scaled transistors are steadily improving in delay, but scaled wires are holding
constant or getting worse.
SIA made a gloomy forecast in 1997
Delay would reach minimum at 250 180 nm, then get
worse because of wires
But
For short wires, such as those inside a logic gate, the wire RC delay is negligible.
However, the long wires present a considerable challenge.
Figure 8 illustrates delay Vs. generation in nm for different materials.

Figure-8:Technology generation

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7.3 Reachable Radius

We cant send a signal across a large fast chip in one cycle anymore

But the microarchitect can plan around this as shown in Figure 9.

Just as off-chip memory latencies were tolerated

Chip size
Scaling of
reachable radius

Figure-9:Technology generation

7.4 Dynamic Power

Intel VP Patrick Gelsinger (ISSCC 2001)

If scaling continues at present pace, by 2005, high speed processors would

have power density of nuclear reactor, by 2010, a rocket nozzle, and by
2015, surface of sun.

Business as usual will not work in the future.

Attention to power is increasing(Figure 10)

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Figure-10:Technology generation

7.5 Static Power

VDD decreases

Save dynamic power

Protect thin gate oxides and short channels

No point in high value because of velocity saturation.

Vt must decrease to maintain device performance

But this causes exponential increase in OFF leakage

A Major future challenge(Figure 11)

Moore(03)
Figure-11:Technology generation

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7.6 Productivity
Transistor count is increasing faster than designer productivity (gates / week)

Bigger design teams

Up to 500 for a high-end microprocessor

More expensive design cost

Pressure to raise productivity

Rely on synthesis, IP blocks

Need for good engineering managers

7.7 Physical Limits

o Will Moores Law run out of steam?


Cant build transistors smaller than an atom

o Many reasons have been predicted for end of scaling



Dynamic power

Sub-threshold leakage, tunneling

Short channel effects

Fabrication costs

Electro-migration

Interconnect delay

o Rumors of demise have been exaggerated

8. Limitations of Scaling

Effects, as a result of scaling down- which eventually become severe enough to prevent
further miniaturization.
o Substrate doping

o Depletion width
o Limits of miniaturization

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o Limits of interconnect and contact resistance

o Limits due to sub threshold currents

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o Limits on logic levels and supply voltage due to noise

o Limits due to current density
8.1 Substrate doping
o Substrate doping
o Built-in(junction) potential VB depends on substrate doping level can be
neglected as long as VB is small compared to VDD.
o As length of a MOS transistor is reduced, the depletion region width scaled
down to prevent source and drain depletion region from meeting.
o the depletion region width d for the junctions is d =

2 si 0V
q NB 1

o si relative permittivity of silicon

o 0 permittivity of free space(8.85*10-14 F/cm)
o V effective voltage across the junction Va + Vb
o q electron charge
o NB doping level of substrate
o Va maximum value Vdd-applied voltage

KT N B N D
o Vb built in potential and
VB =
ln

q ni ni

8.2 Depletion width

N B is increased to reduce d , but this increases threshold voltage Vt
trends for scaling down.

-against

Maximum value of N B (1.3*1019 cm-3 , at higher values, maximum electric field

applied to gate is insufficient and no channel is formed.

N B maintained at satisfactory level in the channel region to reduce the above

problem.

Emax

2V
d

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maximum electric field induced in the junction.

Emax =

ln

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If N B is inreased by Va =0 Vb increased by ln and d is decreased by

Electric field across the depletion region is increased by

ln
1/

Where

Reach a critical level Ecrit with increasing N B

d=

si 0
q NB

d=

2 si Ecrit .d

q NB 2

( Ecrit )

Figure 12 , Figure 13 and Figure 14 shows the relation between substrate concentration
Vs depletion width , Electric field and transit time.
Figure 15 demonstrates the interconnect length Vs. propagation delay and Figure 16
oxide thickness Vs. thermal noise.

Figure-12:Technology generation

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Figure-13:Technology generation

8.3 Limits of miniaturization

minimum size of transistor; process tech and physics of the device

Reduction of geometry; alignment accuracy and resolution

Size of transistor measured in terms of channel length L

L=2d (to prevent push through)

L determined by NB and Vdd

Minimum transit time for an electron to travel from source to drain is

v drift = E
t=

Vdrift

smaximum

2d
E

carrier drift velocity is approx. Vsat,regardless of supply voltage

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Figure-14:Technology generation

8.4 Limits of interconnect and contact resistance

Short distance interconnect- conductor length is scaled by 1/ and resistance is

increased by

For constant field scaling, I is scaled by 1/ so that IR drop remains constant as a

result of scaling.-driving capability/noise margin.

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Figure-15:Technology generation

8.5 Limits due to subthreshold currents

Major concern in scaling devices.

I sub is directly praportinal exp (Vgs Vt ) q/KT

As voltages are scaled down, ratio of Vgs-Vt to KT will reduce-so that threshold
current increases.

Therefore scaling Vgs and Vt together with Vdd .

Maximum electric field across a depletion region is

Emax = 2{Va + Vb }/ d
8.6 Limits on supply voltage due to noise
Decreased inter-feature spacing and greater switching speed result in noise problems

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Figure-16:Technology generation

9. Observations Device scaling

o Gate capacitance per micron is nearly independent of process
o But ON resistance * micron improves with process
o Gates get faster with scaling (good)
o Dynamic power goes down with scaling (good)
o Current density goes up with scaling (bad)
o Velocity saturation makes lateral scaling unsustainable
9.1 Observations Interconnect scaling
o Capacitance per micron is remaining constant
o About 0.2 fF/mm
o Roughly 1/10 of gate capacitance
o Local wires are getting faster
o Not quite tracking transistor improvement
o But not a major problem
o Global wires are getting slower
o No longer possible to cross chip in one cycle
10. Summary

Scaling allows people to build more complex machines

That run faster too

It does not to first order change the difficulty of module design

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Module wires will get worse, but only slowly

[Link]

You dont think to rethink your wires in your adder, memory

Or even your super-scalar processor core

It does let you design more modules

Continued scaling of uniprocessor performance is getting hard

-Machines using global resources run into wire limitations
-Machines will have to become more explicitly parallel

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CMOS SUBSYSTEM DESIGN

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CONTENTS

[Link]

1. System
2. VLSI design flow
3. Structured design approach
4. Architectural issues
5. MOSFET as switch for logic functionality
6. Circuit Families
Restoring Logic: CMOS and its variants - NMOS and Bi CMOS
Other circuit variants
NMOS gates with depletion (zero -threshold) pull up
Bi-CMOS gates
7. Switch logic: Pass Transistor and Transmission gate (TG)
8. Examples of Structured Design
MUX
DMUX
D Latch and Flop
A general logic function block

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[Link]

[Link] is a System?
A system is a set of interacting or interdependent entities forming and integrate whole.
Common characteristics of a system are
o Systems have structure - defined by parts and their composition
o Systems have behavior involves inputs, processing and outputs (of material,
information or energy)
o Systems have interconnectivity the various parts of the system functional as well
as structural relationships between each other
1.1Decomposition of a System: A Processor

5.
VLSI Design Flow
The electronics industry has achieved a phenomenal growth mainly due to the
rapid advances in integration technologies, large scale systems design-in short due
to VLSI.
Number applications of integrated circuits in high-performance computing,
telecommunications, and consumer electronics has been rising steadily.
Current leading-edge technology trend expected to continue with very important
implications on VLSI and systems design.
The design process, at various levels, is evolutionary in nature.
Y-Chart (first introduced by D. Gajski) as shown in Figure1 illustrates the design
flow for mast logic chips, using design activities.
Three different axes (domains) which resemble the letter Y.
Three major domains, namely
Behavioral domain
Structural domain

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Geometrical domain
Design flow starts from the algorithm that describes the behavior
of target chip.

Figure 1. Typical VLSI design flow in three domains(Y-chart)

VLSI design flow, taking in to account the various representations, or abstractions of

design are
Behavioural,logic,circuit and mask layout.
Verification of design plays very important role in every step during process.
Two approaches for design flow as shown in Figure 2 are
Top-down
Bottom-up
Top-down design flow- excellent design process control
In reality, both top-down and bottom-up approaches have to be combined.
Figure 3 explains the typical full custom design flow.

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Figure 2. Typical VLSI design flow

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Figure 3. Typical ASIC/Custom design flow

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3 Structured Design Approach

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Design methodologies and structured approaches developed with complex

hardware and software.
Regardless of the actual size of the project, basic principles of structured designimprove the prospects of success.
Classical techniques for reducing the complexity of IC design are:
Hierarchy
Regularity
Modularity
Locality

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Figure 4-Structured Design Approach Hierarchy

[Link] Design Approach Regularity

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Design of array structures consisting of identical cells.-such as parallel

multiplication array.
Exist at all levels of abstraction:
transistor level-uniformly sized.
logic level- identical gate structures
2:1 MUX, D-F/F- inverters and tri state buffers
Library-well defined and well-characterized basic building block.
Modularity: enables parallelization and allows plug-and-play
Locality: Internals of each module unimportant to exterior modules and internal
details remain at local level.
Figure 4 and Figure 5 illustrates these design approaches with an example.

4 Architectural issues

Design time increases exponentially with increased complexity

Define the requirements
Partition the overall architecture into subsystems.
Consider the communication paths
Draw the floor plan
Aim for regularity and modularity
convert each cell into layout
Carry out DRC check and simulate the performance

5. MOSFET as a Switch

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9.4 D Flip-flop Operation

QM

CLK = 0

QM

CLK = 1

CLK
D
Q

9.5 Race Condition

Back-to-back flops can malfunction from clock skew
Second flip-flop fires late
Sees first flip-flop change and captures its result
Called hold-time failure or race condition

CLK1
CLK2
Q1

Flop

Flop

CLK1

CLK2
Q2

Q1
Q2

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5.2 Series connection of Switches..

5.3 Series and parallel connection of Switches..

g2

(a)

OFF

OFF

ON

(c)

a
g1

g2
b

OFF

OFF

OFF

ON

ON

0
b
ON

b
OFF

a
0

a
g2

ON

g1

OFF

(b)

0
b

0
b

g2

a
g1

0
b

(d)

g1

1
b

ON

ON

1
b
ON

a
0

1
b
OFF

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[Link]

6. Circuit Families : Restoring logic

CMOS INVERTER

DD

Y
Y

A
1

GND
V
A

OFF

DD

A= 1

Y= 0

ON

GND

V DD
A

ON

A= 0

Y= 1

OFF
GND

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6.1 NAND gate Design..

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[Link]
ON

ON
0

Y=1
OFF

A=0
B=0

OFF

OFF

Y=1
A=0

OFF

B=1

ON

ON
0

ON

A=1
B=0

OFF
Y=1
ON
OFF

NAND gate Design..

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[Link]
Y
A
B
C

6.2 NOR gate Design..

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[Link]

A
B
C
D
Y

CMOS INVERTER

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6.3 CMOS Properties

Pull-up OFF

Pull-up ON

Pull-down OFF

Z (float)

Pull-down ON

X (crowbar)

pMOS
pull-up
network

inputs
output
nMOS
pull-down
network

Complementary CMOS gates always produce 0 or 1

Ex: NAND gate
Series nMOS: Y=0 when both inputs are 1
Thus Y=1 when either input is 0
Requires parallel pMOS
Rule of Conduction Complements

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[Link]

Pull-up network is complement of pull-down

Parallel -> series, series -> parallel
Output signal strength is independent of input.-level restoring
Restoring logic. Ouput signal strength is either Voh (output high) or Vol. (output
low).
Ratio less logic :output signal strength is independent of pMOS device size to
nMOS size ratio.
significant current only during the transition from one state to another and - hence
power is conserved..
Rise and fall transition times are of the same order,
Very high levels of integration,
High performance.

6.4 Complex gates..

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6.5 Complex gates AOI..

Y = A B + C D (A ND -A N D-OR-INV ERT, A O I22)

A

(a)

(b)

B C

(c)

(d)

A
B
C
D

= (A+ B +C
C) D

AY
B

(f)

(e)

A
B
C

D
Y
D

unit inverter

AOI21

Y=A

Y = A B+C

Y = A B+C D

A
B
C

A
B
C
D

A
A

2
1

AOI22

4 B
C

4
C

Y
1

Complex AOI

4 B

4 D

2 C

2 D

Y = A ( B + C) + D E
D
E
A
B
C

gA = 3/3

gA = 6/3

gA = 6/3

gA = 5/3

p = 3/3

gB = 6/3

gB = 6/3

gB = 8/3

gC = 5/3

gC = 6/3

gC = 8/3

p = 7/3

gD = 6/3

gD = 8/3

p = 12/3

gE = 8/3

Y
2

p = 16/3

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[Link]

6.6 Circuit Families : Restoring logic CMOS Inverter- Stick diagram

6.7 Restoring logic CMOS Variants:

nMOS Inverter-stick diagram

Basic inverter circuit: load replaced by depletion mode transistor

With no current drawn from output, the current Ids for both transistor must
be same.
For the depletion mode transistor, gate is connected to the source so it is
always on and only the characteristic curve Vgs=0 is relevant.

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[Link]

Depletion mode is called pull-up and the enhancement mode device pulldown.
Obtain the transfer characteristics.
As Vin exceeds the p.d. threshold voltage current begins to flow, Vout thus
decreases and further increase will cause p.d transistor to come out of
saturation and become resistive.
p.u transistor is initially resistive as the p.d is turned on.
Point at which Vout = Vin is denoted as Vinv
Can be shifted by variation of the ratio of pull-up to pull-down resistances
Zp.u / Zp.d
Z- ratio of channel length to width for each transistor

For 8:1 nMOS Inverter

Z p.u. = L p.u. / W p.u =8
R p.u = Z p.u. * Rs =80K
similarly
R p.d = Z p.d * Rs =10K
Power dissipation(on) Pd = V2 /Rp.u + Rp.d =0.28mV
Input capacitance = 1 Cg

For 4:1 nMOS Inverter

Z p.u. = L p.u. / W p.u =4
R p.u = Z p.u. * Rs =40K
similarly
R p.d = Z p.d * Rs =5K
Power dissipation(on) Pd = V2 /Rp.u + Rp.d =0.56mV
Input capacitance = 2Cg

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6.8Restoring logic CMOS Variants: BiCMOS Inverter-stick diagram

A known deficiency of MOS technology is its limited load driving capabilities

(due to limited current sourcing and sinking abilities of pMOS and nMOS
transistors. )
Output logic levels good-close to rail voltages
High input impedance
Low output impedance
High drive capability but occupies a relatively small area.
High noise margin
Bipolar transistors have
higher gain
better noise characteristics
better high frequency characteristics
BiCMOS gates can be an efficient way of speeding up VLSI circuits
CMOS fabrication process can be extended for BiCMOS
Example Applications
CMOS- Logic
BiCMOS- I/O and driver circuits
ECL- critical high speed parts of the system

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6.9 Circuit Families : Restoring logic CMOS NAND gate

6.10 Restoring logic CMOS Variants: nMOS NAND gate

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[Link]
6.11 Restoring logic CMOS Variants: BiCMOS NAND gate

For nMOS Nand-gate, the ratio between pull-up and sum of all pull-downs must
be 4:1.
nMOS Nand-gate area requirements are considerably greater than corresponding
nMOS inverter
nMOS Nand-gate delay is equal to number of input times inverter delay.
Hence nMOS Nand-gates are used very rarely
CMOS Nand-gate has no such restrictions
BiCMOS gate is more complex and has larger fan-out.

[Link] Families :Switch logic: Pass Transistor

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7.1 Switch logic: Pass Transistor

g=0

g
s

Input g = 1 Output
0
strong 0

g=1
s

1
Input

g=0

g
s

g=1
d

[Link]
degraded 1

g=0

Output
degraded 0

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d

g=1

g=0

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[Link]

7.1 Switch logic: Pass Transistor-nMOS in series

VDD

VDD
VDD

VDD

VDD

VDD
Vs = VDD-Vtn

Vs = |Vtp|

VDD-Vtn VDD-Vtn
VDD
VDD

VDD-Vtn

VDD-Vtn
VDD-2Vtn

VSS

7.2 :Switch logic: Transmission gates

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Input
g
a

b
gb

b
gb

g = 0, gb = 1
a
b

g = 1, gb = 0
0
strong 0

g = 1, gb = 0
a
b

g = 1, gb = 0
strong 1
1

g
a

g
b

gb

Output

b
gb

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8 Structured Design-Tristate
Tristate buffer produces Z when not enabled
EN

[Link]

E N

Tristate buffer produces Z when not enabled

EN

E N
Y

A
E N

8.1 Structured Design-Nonrestoring Tristate

EN
A

Y
EN

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8.3 Structured Design-Tristate Inverter

A
EN
Y
EN

Tristate inverter produces restored output

Violates conduction complement rule
Because we want a Z output

A
EN
Y

EN = 0
Y = 'Z'

EN = 1
Y=A

EN

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8.4 Structured Design-Multiplexers

2:1 multiplexer chooses between two inputs

D1

D0

S
1

D1
1

D0
X

Y
1

S
D0

0
Y

D1

8. 5 Structured Design-Mux Design.. Gate-Level

Y = SD1 + SD0 (too many transistors)

How many transistors are needed?

How many transistors are needed? 20

D1
S
D0

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D1

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8.6 Structured Design-Mux Design-Transmission Gate

Nonrestoring mux uses two transmission gates
Only 4 transistors

S
D0
Y

S
D1
S

Inverting Mux
Inverting multiplexer
Use compound AOI22
Or pair of tristate inverters
Noninverting multiplexer adds an inverter

D0

D0

D1

D1

Y
S

S
Y

D0 0
Y
D1 1

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8.7 Design-4:1 Multiplexer
4:1 mux chooses one of 4 inputs using two selects
Two levels of 2:1 muxes
Or four tristates
S1S0 S1S0 S1S0 S1S0

D0
S0
D0

D1

S1
D1
0
Y

Y
D2

D3

1
D2

D3

9 Structured Design-D Latch

When CLK = 1, latch is transparent
D flows through to Q like a buffer
When CLK = 0, the latch is opaque
Q holds its old value independent of D
a.k.a. transparent latch or level-sensitive latch

CLK

CLK

Latch

D -a latch is level
Q sensitive

a register is edge-triggered
A flip-flop is a bi-stable element

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9.1 D Latch Design

Multiplexer chooses D or old Q

CLK
D

CLK

0
CLK CLK

CLK

9.2 D Latch Operation

Q
D

Q
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CLK = 1
CLK = 0
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Structured Design-Latch Design

Inverting buffer
Restoring
No backdriving
Fixes either
Output noise sensitivity
Or diffusion input
Inverted output

9.3 Structured Design-D Flip-flop

When CLK rises, D is copied to Q
At all other times, Q holds its value
a.k.a. positive edge-triggered flip-flop, master-slave flip-flop

CLK

CLK
Flop

Structured Design-D Flip-flop Design

Built from master and slave D latches

CLK

CLK
CLK

CLK
QM

Latch

Latch

CLK

QM

D
CLK

Q
CLK

CLK

Q
CLK

CLK

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9.4 D Flip-flop Operation

QM

CLK = 0

QM

CLK = 1

CLK
D
Q

9.5 Race Condition

Back-to-back flops can malfunction from clock skew
Second flip-flop fires late
Sees first flip-flop change and captures its result
Called hold-time failure or race condition

CLK1
CLK2
Q1

Flop

Flop

CLK1

CLK2
Q2

Q1
Q2

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