Scribd
Upload
157 views3 pages

Digital Electronics Practice Problems

This document contains 16 practice problems related to decoders, multiplexers, and flip-flops. The problems cover topics such as implementing logic functions using multiplexers, designing counters with flip-flops, deriving the characteristic equations and excitation tables of various flip-flop types, and implementing different flip-flop types using other basic flip-flop types. The problems range from deriving equations to designing circuits and include examples involving K-maps, multiplexers, and flip-flops.

Uploaded by

chintu333
Copyright
© All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOC, PDF, TXT or read online on Scribd
157 views3 pages

Digital Electronics Practice Problems

This document contains 16 practice problems related to decoders, multiplexers, and flip-flops. The problems cover topics such as implementing logic functions using multiplexers, designing counters with flip-flops, deriving the characteristic equations and excitation tables of various flip-flop types, and implementing different flip-flop types using other basic flip-flop types. The problems range from deriving equations to designing circuits and include examples involving K-maps, multiplexers, and flip-flops.

Uploaded by

chintu333
Copyright
© All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOC, PDF, TXT or read online on Scribd
  • Practice Problems 2 to 4
  • Practice Problem 1
  • Practice Problem 6
  • Practice Problem 7
  • Practice Problem 9

CS 147 Practice Problems 3.

The following questions are practice problems associated with the lecture material on the
subject of Decoders and Multiplexers.
1.

[Link] the function f(W, X, Y, Z) = (Sigma)m(2, 3, 4, 6, 7, 15) + (Sigma)d(0, 5, 12,


13) and its K-map, is it possible to realize it using a single 4 --> 1 MUX by choosing
S1 S0 = W X, Di (a member of) {0, 1, Y, not Y, Z, not Z} ; i = 0, 1, 2, 3 (the
complements of the input variables are available). If your answer is positive show the
realiziation; if it's negative explain why.
3. . Implement the sum function for an adder using a 4-input-1-output multiplexer and an
inverter. Remember that the inputs for that function are A, B, and CI and the output is
simply S.
[Link] the following Boolean function by K-map
f(x,y,z) = m(0,2,4) + d(1,3)
5. You are to design a circuit that has two data inputs (A and B) and three control outputs
(C0,C1, and C2). The circuit should implement the function F specified in the function
truth table below. Please give the Boolean equation for F, and then show how to
implement this by PLA with 5 inputs and 1 output.

[Link] the expression

7 Construct a 2-bit counter with a sequence of states 00, 01, 11, and 10 using D flip-flops
and NAND gates
[Link] have invented a new type of flip-flop that you have called MY flip-flop. The two
inputs are M and Y, the outputs are Q and Q'. The truth table of your flip-flop is given
below.
MY

Q+

00

01

10

Q'

11

a.
b.
c.
d.

Give the characteristic equation of the new flip-flop.


Give the excitation table for the new flip-flop.
Show how to implement a T flip-flop using the new MY flip-flop.
Show how to implement your new MY flip-flop using a SR flip-flop. Give the
logic diagram (showing the SR flip-flop and logic gates
e. Give the gate level schematic of the new MY flip-flop (designed in section d
above), assuming that the SR flip-flop is a master-slave flip-flop

9. What type of FF can be used as an R-S, a T, or a D FF?

Q.1 What will be the output of Q if J is HIGH, PS and CLR are HIGH, and
the
clock
is
going
negative?
Q.2 Assume that K goes HIGH and J goes LOW; when will the FF reset?
Q.3 What logic levels must exist for the FF to be toggled by the clock?
Q.4 What two inputs to a J-K FF will override the other inputs?
Q.5 How is the J-K FF affected if PS and CLR are both LOW?

10. Give the circuit symbol ,the excitation table and the characteristic equation of each of the following flipflops:
R-S flip-flop.
D flip-flop.
J-K flip-flop.
T flip-flop.
11. A set dominate flip-flop has a set and a reset input. It differs from a conventional R-S flip-flop in that an
attempt to
simultaneously set and reset results in setting the flip-flop.
Obtain the characteristic table and characteristic equation for such a flip-flop.
Obtain a logic diagram for an asynchronous set-dominate flip-flop.
12. Beginning with an R-S flip-flop show how to get
D flip-flop.
J-K flip-flop.
T flip-flop.
13. Beginning with an D flip-flop show how to get
J-K flip-flop.
T flip-flop.
14. Beginning with an J-K flip-flop show how to get
D flip-flop.
T flip-flop.
15. Beginning with an T flip-flop show how to get
D flip-flop.
J-K flip-flop.
[Link] a new flip-flop type, called X-Y flip-flop, that has the following truth table
X Y Q(t+1)
0 0 Reset
0 1 Q(t)
1 0 Q'(t)
1 1 Set

CS 147 Practice Problems 3. The following questions are practice problems associated with the lecture material on the subjec
6.Given (http://www.tpub.com/neets/book13/55m.htm)the expression 7 Construct a 2-bit counter with a sequence of states 00,
Q.1 (http://www.tpub.com/neets/book13/55m.htm)What will be the output of Q if J is HIGH, PS and CLR are HIGH, and the cloc

You might also like