1

8x4 SRAM in TSMC 0.25m Technology

Adib Nahiyan, Md Mahbub Alam, Mehdi Sadi, Fahim Rahman, and Miao He
Department of Electrical and Computer Engineering, University of Florida, Gainesville, Florida
Email: {adib1991, [Link], [Link], fahim034, tonyhe}@[Link]

AbstractA design and implementation of a 8x4 SRAM

architecture is presented in this work. The objective of this
work is to have a minimized layout area without compromising
performance in terms of stable read and write access operation.
To achieve this, transistor sizing has been optimized for memory
cells, decoder, write driver, and sense amplifier. This design has a
area of 3468 m2 and can perfectly operate at 500MHz frequency.

wordline
M2

bit

M4

M5

M1

bit
M6

M3

I. I NTRODUCTION

In this section, we discuss the design methodology of a

8x4 SRAM. The building blocks used are 6T SRAM cell,
row and column decoders, bit-line conditioning circuitry, readwrite control circuitry, and sense amplifier. We discuss each
of these blocks in subsequent sections.
A. 6T SRAM Cell
A 6T SRAM cell uses two cross-coupled inverters accessed
using two pass transistors, as shown in Fig. 1. Proper sizing
of these transistors is required to achieve the desired cell area,
and stability during read and write. The major SRAM design
goals are the following
During read operation, the high bit-lines must not overpower the NMOSs M1 /M3 . In other words, the drain
to source voltage (Vds ) of these transistors must not
rise above the threshold voltage (Vtn ) of M1 /M3 . This
condition is defined as VQ < VT N .
During write operation, the low bit lines must write new
values into the cells. In other words, Vds of M5 /M6 must
be less than VT N of M1 /M3 . This condition is defined as
VQ < VT N .
We first get the threshold values of M1 /M3 as equal to 0.6V
from simulation. 20% of process variation in threshold voltage
results into a lower bound of VT N 0.48V. For read stability we
need to size the transistors M1 and M5 (M3 and M6 ) so that
VQ < 0.48. For this analysis, we have varied the width of M1

1 W5
(W1 ) and CR (where CR is defined as W
L1 / L5 ) and measured
VQ , as shown in Fig. 2(a). We choose W1 = 360n and CR = 1 to
minimize the size of SRAM cell. It results VQ = 0.32V which
is much lower than VT N = 0.48V .

For write stability we need to size the transistors M4 and

M6 (M2 and M5 ) such that VQ < 0.48V . For this we have
varied the width of M4 (W4 ), and PR (where PR is defined as
W4 W6
L4 / L6 ), and measured VQ , as shown in Fig. 2(b). We choose
the W4 = 360n and PR = 1 to minimize the size of SRAM.
This sizing results in VQ = 0.11V which is much lower than
VT N = 0.48V .
As we see, minimum size transistors (W=360nm and
L=240nm) can provide reasonable level of read and write
stability. Therefore, we have chosen minimum sizing for all
six transistors for SRAM cell.
Static-noise margin (SNM) is defined as the amount of DC
noise necessary to disturb the internal storage node of the cell
and flip its stored data [3]. The SNM can be estimated using
the graphical maximum square method using the inverters
transfer function curve. The hold, read, and write SNM for
our chosen SRAM size is shown in Fig. 3(a), 3(b), and 3(c),
respectively.

0 .5 5
0 .6

0 .5 0
W = 3
W = 4
W = 6
W = 7
W = 8
W = 9
W = 1

0 .4 5

0 .4 0

6 0 n
8 0 n
0 0 n
2 0 n
4 0 n
6 0 n
0 8 0

W = 3
W = 4
W = 6
W = 7
W = 8
W = 9
W = 1

m
m
m

0 .5

m
m
m
0 .4

n m

6 0 n
8 0 n
0 0 n
2 0 n
4 0 n
6 0 n
0 8 0

m
m
m
m
m
m
n m

II. D ESIGN M ETHODOLOGY

Figure 1: 6T 1bit SRAM Cell

Static random access memory (SRAM) is extensively used

as high performance cache in almost all modern processors
and SoCs [1]. Since SRAM incurs a significant area overhead
with large power consumption, we aim to design a SRAM
with high density and fast speed. The SRAM cell sizing is
estimated based on the requirement of reliable operation with
compact layout and small propagation delay. Furthermore,
the row decoder is designed to be pitch-matched with the
SRAM cell height. A predecoding circuitry is added in the
design to reduce fan-in for faster addressing. Rest of the paper
briefly shows the analysis, complete layout, and results of the
designed SRAM architecture.

0 .3 5

0 .3

0 .3 0
0 .2

0 .2 5

0 .2 0

0 .1

1 .0

1 .5

2 .0

C R

(a)

r a tio

2 .5

3 .0

0 .4

0 .6

0 .8

1 .0

P R

1 .2

1 .4

R a tio

(b)

Figure 2: (a) VQ for different W1 & CR, (b) VQ for W4 a& PR.

1 .6

H o ld S N M

R e a d S N M

= 1 .1 9 2 V

= 0 .3 5 V

2 .5

2 .5

2 .0

2 .0

2 .0

1 .5

1 .5

1 .5

W r ite S N M

= 1 .4 7 V

o r V

1 .0

1 .0

1 .0

o r V

o r V

2 .5

0 .5

0 .5

0 .5

0 .0

0 .0
0 .0

0 .5

1 .0

1 .5

V
Q

o r V

2 .0

0 .0

2 .5

0 .5

1 .0

(a)

1 .5
Q

o r V

2 .0

2 .5

0 .0
0 .0

0 .5

1 .0

(b)

1 .5

o r V
Q

2 .0

2 .5

(c)

Figure 3: (a) Hold SNM, (b) Read SNM, and (c) Write SNM.
B. Row Decoder

bit

Data

Address decoding involves feeding an address value into

a binary decoder (n to 2n ) and using the asserted output to
activate the wordline of a subset of memory cells associated
with this address. The main concern in address decoding is
the large fan-in and fan-out requirements of typical memories
because of the number of address bits being decoded and the
large amount of cells that have to be driven [2].
In typical designs, the address decoder contributes significantly to the critical path delay and total power dissipation,
emphasizing the need to optimize the memory arrays decode
hierarchy implementation. Here we investigate three different
approaches for implementing row decoder, namely NOR,
NAND, and pre-decoding circuit implementations [4], to find
one with the lowest critical path delay.
We use the linear delay model [5] to estimate the critical
path delay. According to this model, the delay of a stagedpath is minimized when each stage bears the same effort. If
a path consists of N stages, then delay will be minimized if
each stage has an effort of,
1
f = (G B H) N
(1)

7/3
B=4

5/3
B=4

4/3
B=2

2/3

(a)

2/3

(b)

(c)

2/3

bit

bit

Figure 5: (a) Preconditioning circuit, (b) write driver

where G, B and H is defined as path logical effort, path branch
effort and path electrical effort, respectively.
Fig. 4 shows the critical path of NOR, NAND and Predecoding circuit implementations. The number shown on each
gate signifies the logical effort of that particular gate.
The G, B, H, f, and estimated total delay (Td ) for row
decoder implementations are shown in Table II. It shows that
pre-decoding circuit results in minimum delay. Therefore, we
chose to use pre-decoding circuit for our row decoder and then
use the stage effort value, f to size each transistor.

Decoder
NOR
NAND
Pre-decoder

G
14/9
10/9
40/27

B
4
4
2

H
8/3
8/3
8/3

N
4
5
5

f
2.01
1.63
1.51

Td
8.07
8.19
7.56

C. Column Circuitry
Wc=8

5/3

Data

Table I: Reports of vulnerable transition, V T .

1
Wc=8

bit

Write

1
Wc=8

Figure 4: Critical path of the decoder circuits: (a) NOR,

(b) NAND, and (c) predecoding implementations respectively.
Note that Wc = 8 represents that there are 4 2 gate capacitance (of M5 and M6) are connected with the wordline. The
rectangular box is the wordline driver as implemented in [2].

To support the operation of the SRAM memory cells, the

cells are accompanied by additional peripheral circuitry like
preconditioning circuit, MUX, write circuit, sense amplifier.
1) Preconditioning Circuit: All bitlines are assumed to
be precharged to a given voltage (usually VDD ). Figure 5(a)
shows a preconditioning circuit. During precharge and equalize
operations, all three PMOS transistors are enabled, providing low-impedance paths from both bitlines to Vdd and to
each other. When the bitlines have been precharged, these
transistors are turned off, resulting in very high impedances
isolating Vdd from both bitlines. This configuration speeds up

read

SRAM
BLOCK

Figure 6: Sense amplifier circuit.

the development of the bitline voltage differential because the
pulldown only has to discharge the existing bitline capacitance.
During write operations, no unnecessary power is wasted in
the precharge circuit since it does not affect the operation
of the write driver. The sizing of these precharge transistors
is important because it determines precharging time. In this
work, we choose PMOS width = 1.08 m that works well
with 500MHz clock frequency.
2) Write driver: Write driver is required to write new
values into the SRAM cell by flipping the internal state of the
cell during write operation. Fig. 5(b) shows our implemented
write driver. The write driver adds to NMOSs in series with
each bit-line. During write operation, these NMOSs appear
in series with the SRAM cells M5/M6 NMOS. As discussed
in subsection II-A, for stable write operation VQ < VT N . This
condition requires that the effective combined series resistance
of M5/M6 NMOS and write drivers NMOSs need to be less
than that of M2/M4 PMOS of the SRAM cell. Therefore, we
have used relatively large width 2.16 m for write drivers
NMOSs to make their resistance negligible.
3) Sense Amplifier: The development of a voltage differential in the bitline pairs during a read access is a slow
process because the pulldown device of the memory cell is
hard pressed to discharge the large capacitive load of the
bitline. A sense amplier is needed to speed up the development
of this bitline voltage differential. The schematic of the sense
amplifier is depicted in Fig. 6.
The sizing of the sense amplifiers is crucial because the
overall read access time depends on it. To get the proper sizing,
we plot the propagation delay of the sense amplifier circuit

(a)

Sense
Amp

MUX-1

bit

MUX-2

bit

Inter-Connect

sense

Wordline Driver

sense

Pre-Decoder

Buffer Pre-Conditioning

Write

(b)

Figure 8: (a) Single Cell layout, (b) Complete floor plan

(Y 0) for various NMOS and PMOS widths (see Fig. 7). Our
analysis shows that we get minimum propagation delay for
Wp = Wn = 360m.
4) Column Decoder: The column decoder is implemented
with a 4to1 multiplexer circuit. We used the pass transistor
topology to implement the multiplexer. The reason for using
pass transistor topology is because, during read operation the
MUX need to pass strong 1 and during write operation the
MUX needs to pass strong 0. The pass transistor topology
allows to pass both strong 1 and 0.
These pass transistors also appear in series with the bit-lines.
Therefore, the width of NOMS and PMOS pass transistors are
intentionally made wider so that their effective resistance are
much less than the resistance of M5/M6 NMOS. This ensures
stability during write operation. We choose 2.16 m as the
width of NMOS and PMOS of the pass transistors.
III. I MPLEMENTATION
After finalizing the design parameter, design is implemented
in TSMC 0.25m Technology. All the transistor sizing has
been done as described in Section II. Single cell layout is
shown in Fig. 8(a) with a cell dimensions of 5.76m x
7.39m or 48x62. Total Cell area is 42.5664m2 . Note
that, the layout of the wordline driver and decoder circuit
is implemented is such a way that they are pitch-matched
with the SRAM cells. Floor plan of the complete circuit is
illustrated in Fig. 8(b). Layout of the complete design is given
in Fig. 10. Total area is 3468m2 (52.2m x 69.90m) of
84.9% active area, 12.4% dediacted interconnect area, and only
2.7% unused area.
IV. R ESULTS
The gate capacitance (Cg ), and the diffusion capacitance
(Cdi f f ) of access transistors of this design are calculated
as shown below. A wordline driver consists of two gate
capacitances, hence it has 1.8fF, and bitlines contain 0.74fF
as only diffusion capacitance contributes to bitlines. From
simulation we have got Cg =0.59fF and Cdi f f =1.23fF.

Figure 7: Propagation delay vs NMOS and PMOS widths.

Note that, E0 and X represents the probation delay and ratio
Wp
of PMOS and NMOS width ( ), respectively.
Wn

Cg = Cgc +Coverlap
= wLCOX + 2WCO
= 0.74 f F

Cdi f f = Cbottom +CSW

= C jW LS +C jw (2Ls +W )
= 0.90 f F

Figure 9: Sample read and write operation

Table II: SRAM parameters
Overall SRAM area
Read access time
Write access time
Power dissipation
Shortest clock period
Energy Delay Product

5.76m x 7.39m
0.38ns
0.43ns
1.7mW
2n
6.8 1021 Js

V. C ONCLUSION
A highly dense SRAM architecture with very fast read and
write access time is presented in this work. We optimize the
area by making the decoder, and the wordline driver circuit
pitch-matched with height of the SRAM cell. One possible
future work would be to improve the power dissipation of
the circuit. In this work, we have used static NMOS load
in the wordline driver circuit. This implementation scheme
reduces the delay with somewhat compromising static power
dissipation. We would like to optimize the power in future.
ACKNOWLEDGMENT
We are grateful to Dr. Rizwan Bashirullah for assigning such
thoughtful project and for his suggestion to make the SRAM
design better. We also like to thank all teaching assistances of
this course for their wonderful support.
R EFERENCES
Figure 10: Complete SRAM Layout

Our design perfectly operates at a 500MHz clock frequency.

Sample read and write operations are depicted in Fig. 9.
Average read and write access time is measured over multiple
cycles. Power dissipation is estimated by measuring current
from the supply for 20 cyles. Table II summarizes the result.

[1] Indumathi, G.; Aarthi, V.P.M.B., Energy optimization techniques on

SRAM: A survey, in Communication and Network Technologies (ICCNT), 2014 International Conference on , vol., no., pp.216-221, 18-19
Dec. 2014
[2] Wang et. al., In Praise of Memory Systems: Cache, DRAM, Disk .
[3] J. Lohstroh, [Link], and J. de Groot. 1983. Worstcase mstatic noise
margin criteria for logic circuits and their mathematical equivalence.
IEEE J. Solid-State Circuits, SC-18(6), 803807, Dec. 1983.
[4] Jan M. Rabaey, Digital Integrated Circuits: A Design Perspective,
Prentice-Hall, Inc., Upper Saddle River, NJ, USA, 1996.
[5] Neil Weste and David Harris, CMOS VLSI Design: A Circuits and
Systems Perspective, Addison-Wesley Publishing Company, USA.

Adib Nahiyan obtained his BS in Electrical Engineering from Bangladesh University of Engineering and Technology (BUET) in 2014. Currently he
is perusing his doctorate degree in the Electrical
and Computer Engineering department at University of Florida, Gainesville, USA. His PhD studies
are funded by Semiconductor Research Corporation
(SRC). His research interest includes Hardware Security, Secure VLSI Design and Finding Vulnerabilities in Digital Design.

Md Mahbub Alam obtained his BS in Electrical

Engineering from Bangladesh University of Engineering and Technology (BUET) in 2011. He worked
as Engineer in Samsung Research and Development
Center, Bangladesh from 2011 to 2013. Currently
he is a PhD student in the Electrical and Computer
Engineering department at University of Florida,
Gainesville, USA. His research interest and expertise
are in the areas of Hardware Security and Trust,
Counterfeit IC detection and prevention.

Mehdi Sadi (S12) obtained his BS in Electrical

Engineering from Bangladesh University of Engineering and Technology (BUET) in 2009 and Master
of Science in Electrical Engineering from University
of California at Riverside, USA in 2011. Currently
he is a PhD student in the Electrical and Computer
Engineering department at University of Florida,
Gainesville, USA. His PhD studies are funded by
Semiconductor Research Corporation (SRC) and
NSF. During his graduate studies he worked as
research intern with GlobalFoundries at Malta, NY
and as technical consultant with Freescale Semiconductor at Austin, TX. His
research interest and expertise are in the areas of Digital VLSI Design, Design
For Test (DFT), Computer Architecture and Mixed Signal Circuit Design.

Fahim Rahman Fahim Rahman received his

[Link]. in Electrical and Electronic Engineering from
Bangladesh University of Engineering and Technology, Bangladesh in 2009 and MS in Electrical and
Computer Engineering from the University of Connecticut, USA in 2015. He is currently pursuing the
Ph.D. at the University of Florida, USA under Prof.
Mark Tehranipoor. His contributions and research
interests are in the field of hardware security and
trust. His main specialties include low-cost PUFs
and security aspects of emerging nano-electronic
devices.

Miao He Miao He is currently pursuing his PhD in

Electrical and Computer Engineering at the University of Florida. His research interests include VLSI
Digital Circuits Design and Testing, Reconfigurable
Computing, FPGA-based Dynamic Partial Reconfiguration, and Embedded Systems Design.

Figure 11: DRC report

Figure 12: LVS