INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
HEF40175B
MSI
Quadruple D-type flip-flop
Product specification
File under Integrated Circuits, IC04
January 1995
Philips Semiconductors
Product specification
HEF40175B
MSI
Quadruple D-type flip-flop
buffered outputs (O0 to O3). Information on D0 to D3 is
transferred to O0 to O3 on the LOW to HIGH transition of
CP if MR is HIGH. When LOW, MR resets all flip-flops
(O0 to O3 = LOW, O0 to O3 = HIGH), independent of CP
and D0 to D3.
DESCRIPTION
The HEF40175B is a quadruple edge-triggered D-type
flip-flop with four data inputs (D0 to D3), a clock input (CP),
an overriding asynchronous master reset input (MR), four
buffered outputs (O0 to O3), and four complementary
Fig.1 Functional diagram.
PINNING
Fig.2 Pinning diagram.
D0 to D3
data inputs
CP
clock input (LOW to HIGH; edge-triggered)
MR
master reset input (active LOW)
O0 to O3
buffered outputs
O0 to O3
complementary buffered outputs
FUNCTION TABLE
INPUTS
CP
HEF40175BP(N): 16-lead DIL; plastic
OUTPUTS
MR
no change
no change
(SOT38-1)
HEF40175BD(F): 16-lead DIL; ceramic (cerdip)
(SOT74)
HEF40175BT(D): 16-lead SO; plastic
(SOT109-1)
Notes
( ): Package Designator North America
1. H = HIGH state (the more positive voltage)
L = LOW state (the less positive voltage)
X = state is immaterial
FAMILY DATA, IDD LIMITS category MSI
See Family Specifications
= positive-going transition
= negative-going transition
January 1995
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Philips Semiconductors
Quadruple D-type flip-flop
January 1995
3
Product specification
HEF40175B
MSI
Fig.3 Logic diagram.
Philips Semiconductors
Product specification
HEF40175B
MSI
Quadruple D-type flip-flop
AC CHARACTERISTICS
VSS = 0 V; Tamb = 25 C; CL = 50 pF; input transition times 20 ns
VDD
V
SYMBOL
MIN.
TYPICAL EXTRAPOLATION
FORMULA
TYP. MAX.
Propagation delays
CP On, On
HIGH to LOW
5
10
tPHL
15
5
LOW to HIGH
10
tPLH
15
MR On
HIGH to LOW
5
10
tPHL
15
MR On
LOW to HIGH
5
10
tPLH
15
Output transition times
HIGH to LOW
LOW to HIGH
Dn CP
Hold time
Dn CP
Minimum clock
pulse width; LOW
Minimum MR pulse
width; LOW
Recovery time
for MR
Maximum clock
pulse frequency
53 ns + (0,55 ns/pF) CL
70 ns
24 ns + (0,23 ns/pF) CL
25
50 ns
17 ns + (0,16 ns/pF) CL
70
140 ns
43 ns + (0,55 ns/pF) CL
30
65 ns
19 ns + (0,23 ns/pF) CL
25
45 ns
17 ns + (0,16 ns/pF) CL
75
155 ns
48 ns + (0,55 ns/pF) CL
30
65 ns
19 ns + (0,23 ns/pF) CL
25
50 ns
17 ns + (0,16 ns/pF) CL
70
140 ns
43 ns + (0,55 ns/pF) CL
30
65 ns
19 ns + (0,23 ns/pF) CL
25
50 ns
17 ns + (0,16 ns/pF) CL
10 ns + (1,0 ns/pF) CL
60
120 ns
60 ns
9 ns + (0,42 ns/pF) CL
15
20
40 ns
6 ns + (0,28 ns/pF) CL
60
120 ns
30
60 ns
9 ns + (0,42 ns/pF) CL
20
40 ns
6 ns + (0,28 ns/pF) CL
60
30
ns
10
tTHL
tTLH
20
10
ns
15
10
15
ns
25
ns
10
tsu
10
ns
15
10
ns
90
45
ns
10
thold
tWCPL
35
15
ns
15
25
10
ns
80
40
ns
10
tWMRL
30
15
ns
15
20
10
ns
30
ns
20
ns
15
15
ns
11
MHz
15
30
MHz
20
45
MHz
10
10
15
January 1995
160 ns
30
10
15
Set-up time
80
35
tRMR
fmax
10 ns + (1,0 ns/pF) CL
see also waveforms Fig.4
Philips Semiconductors
Product specification
HEF40175B
MSI
Quadruple D-type flip-flop
AC CHARACTERISTICS
VSS = 0 V; Tamb = 25 C; input transition times 20 ns
VDD
V
TYPICAL FORMULA FOR P (W)
2000 fi + (foCL) VDD2
where
dissipation per
10
8400 fi + (foCL) VDD
fi = input freq. (MHz)
package (P)
15
22 500 fi + (foCL) VDD2
Dynamic power
fo = output freq. (MHz)
CL = load capacitance (pF)
(foCL) = sum of outputs
VDD = supply voltage (V)
Fig.4
Waveforms showing minimum pulse widths for CP and MR, MR to CP recovery time, and set-up time and
hold time for Dn to CP. Set-up and hold times are shown as positive values but may be specified as
negative values.
APPLICATION INFORMATION
Some examples of applications for the HEF40175B are:
Shift registers
Buffer/storage register
Pattern generator
January 1995