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FlipFlop
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bistablemultivibrator.
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(input,outputorintermediate).Flipfloparealsousedtoexercisecontroloverthefunctionalityofadigital
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mainlyusedinsituationswhichrequireoneormoreofthesethree.
Operations,storageandsequencing.
LatchFlipFlop
TheRS(ResetSet)[Link]
whichhastwooutputsoneoutputbeingtheinverseorcomplementoftheother,[Link]
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presetandclearinputs).
SuchflipflopcanbemadesimplybycrosscouplingtwoinvertinggateseitherNANDorNORgatecouldbe
usedFigure1(a)showsonRSflipflopusingNANDgateandFigure1(b)showsthesamecircuitusingNOR
gate.
Figure1:LatchRSFlipFlopUsingNANDandNORGates
TodescribethecircuitofFigure1(a),assumethatinitiallybothRandSareatthelogic1stateandthat
outputisatthelogic0state.
Now,ifQ=0andR=1,thenthesearethestatesofinputsofgateB,thereforetheoutputsofgateBisat1
(makingittheinverseofQi.e.0).TheoutputofgateBisconnectedtoaninputofgateAsoifS=1,both
inputsofgateAareatthelogic1state.ThismeansthattheoutputofgateAmustbe0(aswasoriginally
specified).Inotherwords,the0stateatQiscontinuouslydisablinggateBsothatanychangeinRhasno
effect.Alsothe1stateat
iscontinuouslyenablinggateAsothatanychangeSwillbetransmitted
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statesinceQ=0.
NowsupposethattheRSflipflopintheResetstate,[Link]
to1andwithQ=1andR=1,theoutputofgatesB(
)willgoto0with
now0gateAisdisabled
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device,calledtheSetstatesinceQ=1.NotethatthechangeofthestateofSfrom1to0hascausedtheflip
floptochangefromtheResetstatetotheSetstate.
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willbeforcedto1andwillremainsofaras
longasRandSarekeptat0.Howeverwhenbothinputsreturnto1thereisnowayofknowingwhetherthe
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indeterminatestategreatcaremustbetakenwhenusingRSflipfloptoensurethatbothinputsarenot
instructedsimultaneously.
Table1:ThetruthtablefortheNANDRSflipflop
Initial
Conditions
Inputs
(Pulsed)
FinalOutput
indeterminate
indeterminate
ormoresimplyshowninTable2
Table2:SimpleNANDRSFlipFlopTruth
Table
S
indeterminate
Set(1)
Reset(0)
NoChange
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statewhenRandSareboth0.Achangeofstateiseffectedbypulsingtheappropriateinputtothe1state.
TheindeterminatestateisnowwhenbothRandSaresimultaneouslyatlogic1.Table3showsthis
operation.
Table3:NORGateRSFlipFlopTruthTable
S
R
0
Q
0
NoChange
Reset(0)
Set(1)
Indeterminate
ClockedRSFlipFlop
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thetimeatwhichtheflipflopchangesthestateofitsoutput.
IntheclockedRSflipfloptheappropriatelevelsappliedtotheirinputsareblockedtillthereceiptofapulse
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Figure2:ClockedRSFlipFlop
Table4:ThetruthtablefortheClockedRSflipflop
InitialConditions
Inputs(Pulsed)
FinalOutput
Q(t+1)
indeterminate
indeterminate
TheexcitationtableforRSflipflopisverysimplyderivedasgivenbelow
Table5:ExcitationtableforRSFlipFlop
S
NoChange
Reset(0)
Set(1)
Indeterminate
DFlipFlop
ADtype(Dataordelayflipflop)hasasingledatainputinadditiontotheclockinputasshowninFigure3.
Figure3:DFlipFlop
Basically,suchtypeofflipflopisamodificationofclockedRSflipflopgatesfromabasicLatchflipflopandNOR
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gate,isappliedtotheRinput.
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circuitisstraightforwardasfollows.
Whentheclockislow,bothANDgatesaredisabled,thereforeDcanchangevalueswithoutaffectingthe
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equaltoDwhentheclockagaingoeslow,[Link]
flopisasgivenbelowintable6.
Table6:TruthtableforDFlipFlop
S
Q(t+1)
TheexcitationtableforDflipflopisverysimplyderivedgivenasunder.
Table7:ExcitationtableforDFlipFlop
S
Q
0
JKFlipFlop
OneofthemostusefulandversatileflipflopistheJKflipfloptheuniquefeaturesofaJKflipflopare:
1. IftheJandKinputarebothat1andtheclockpulseisapplied,thentheoutputwillchangestate,
regardlessofitspreviouscondition.
2. IfbothJandKinputsareat0andtheclockpulseisappliedtherewillbenochangeintheoutput.
Thereisnoindeterminatecondition,[Link]
circuitdiagramforaJKflipflopisshowninFigure4.
Figure4:JKFlipFlop
WhenJ=0andK=0
TheseJandKinputsdisabletheANDgates,[Link]
words,Qreturnsitlastvalue.
WhenJ=0andK=1,
TheupperANDgateisdisabledthelowerANDgateisenabledifQis1therefore,flipflopwillbereset(Q=0,
=1)ifnotalreadyinthatstate.
WhenJ=1andK=0
ThelowerANDgateisdisabledandtheupperANDgateisenabledif
settheflipflop(Q=1,
=0)ifnotalreadyset
isat1,Asaresultwewillbeableto
WhenJ=1andK=1
IfQ=[Link]
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forJKflipflopisshownintable8.
Table8:ThetruthtablefortheJKflipflop
InitialConditions
Inputs(Pulsed)
FinalOutput
Q(t+1)
TheexcitationtableforJKflipflopisverysimplyderivedasgivenintable8.
Table6:ExcitationtableforJKFlipFlop
S
NoChange
Toggle
TFlipFlop
AmethodofavoidingtheindeterminatestatefoundintheworkingofRSflipflopistoprovideonlyoneinput(
theTinput)such,[Link]
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asshowninFigure5.
Figure5:TFlipFlop
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inputeachtimeoneofthesetriggers,theoutputoftheflipflopchangesstage.ForinstanceQequals0just
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arrives,itresultsinahighSinput.
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thetriggerpassesthroughtotheRinputthisforcestheflipfloptoreset.
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theinputstatedanotherway,[Link]
adividebytwocircuit.
Adisadvantageofthetoggleflipflopisthatthestateoftheflipflopafteratriggerpulsehasbeenappliedis
onlyknownifthepreviousstateisknown.ThetruthtableforaTflipflopisasgiventable7.
Table7:TruthtableforTFlipFlop
Qn
Qn+1
T
0
TheexcitationtableforTflipflopisverysimplyderivedasshowninTable8.
Table8:ExcitationtableforT
FlipFlop
T
Q
0
Qn
1
n
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relationofTflipflopusingJKflipflop.
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stagehavingQ0transistors
=1,Providingatoggleaction,ifthestagehadQ=1theclockpulsewould
resultinQ=0beingtransferred,[Link]
Figure6willthusoperateasaTtypestage,complementingeachclockpulse.
MasterSlaveFlipFlop
Figure8showstheschematicdiagramofmastersloaveJKflipflop
Figure8:MasterSlaveJKFlipFlop
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