UNIT-I

Micro Processor:
The CPU inbuilt on a single si chip it execute the instructions step by step.
The processors are: 8085, 8086, 8088, 80186,80286,80386,80486,Pentium processor
Explain the architecture of 8086 Micro Processor?BIU,EU Units?
Feature of 8086 micro processor
It is a 16 bit p.
8086 has a 16 bit data bus. The data bus is bidirectional. The data range (D0-D15)
8086 has a 20 bit address bus can access up to 220 memory
locations ( 1 MB) .The address bus is unidirectional. address range (A0-A19)
It can support upto 64K I/O ports.
It provides 14, 16-bit registers.
It has multiplexed address and data bus AD0- AD15 and A16 A19It requires single phase clock with
33% duty cycle to provide internal timing.
8086 is designed to operate in two modes, Minimum and Maximum.
It can prefetches upto 6 instruction bytes from memory and
queues them in order to speed up instruction execution.
It requires +5V power supply.
A 40 pin dual in line package
BUS INTERFACE UNIT(BIU)
The bus interface unit(BIU) are divided into three main blocks are
[Link] Instruction byte queue
2. Segment register
[Link] pointer
EXECUTION UNIT(EU)
The Execution unit divided into three main blocks are
[Link]

[Link]

[Link] unit

Fig:8086 Micro Processor Architecture

[Link] INTERFACE UNIT(BIU)

[Link] Byte queue:

6
5
4
3
2
1

Fig: six instruction byte queue

The Bus Interface Unit (BIU) generates the 20-bit physical memory address and provides the interface
with external memory (ROM/RAM). As mentioned earlier, 8086 has a single memory interface.

Queue follows to Access the memory in FIFO order .

It follows pipelining process ,for each instruction execution it follows following steps:[Link]

[Link] [Link] results.

To speed up the execution, 6-bytes of instruction are fetched in advance and kept in a 6-byte
Instruction Queue while other instructions are being executed in the Execution Unit (EU). Hence
after the execution of an instruction, the next instruction is directly fetched from the instruction
queue without having to wait for the external memory to send the instruction. This is called pipelining and is helpful for speeding up the overall execution process.

[Link] Register:
8086's BIU produces the 20-bit physical memory address by combining a 16-bit segment address
with a 16-bit offset address. There are four 16-bit segment registers, viz., the 1. code segment (CS), the
stack segment (SS), the extra segment (ES), and the data segment (DS). These segment registers hold the
corresponding 16-bit segment addresses. A segment address is the upper 16-bits of the starting address
of that segment. The lower 4-bits of the starting address of a segment is always zero. The offset address
is held by another 16-bit register. The physical 20-bit address is calculated by shifting the segment
address 4-bit left and then adding that to the offset address.
For Example:
Code Segment: It is a 16-bit registers stores starting address of codesegment.
Code
Instruction

segment

Register

pointer

IP

CS

holds

holds
the

the

segment

offset

address

address

which

which
is

is

4569

10A0

H
H

The physical 20-bit address is calculated as follows.

Segment
Offset

address
address

:
:+

45690H
10A0H
Physical address : 46730 H

[Link] pointer: It holds the next instruction address to be executed.

II. EXECUTION UNIT(EU)
[Link]:it performs arithmetic and logical operations
[Link] unit: it generate necessary control signals to execution of operation i .e memory read, write
signals, interrupt acklowledgement.

[Link]: the registers are temporary storage of data in 8086 have 14,16-bit registers.
AX:Accumulator

F:flag register

SI:source index

BX:base register

DI:destination index

CX:counter register

IP:instruction pointer

DX:data register

BP:base pointer
Sp;Stack pointer

Cs:code segment register

Ds:data segment regiter
SS:Stacksegment regiter
Es:Extra segment regiter

Register Organization of Intel 8086 Microprocessor

Intel 8086 was the first 16-bit microprocessor introduced by Intel in 1978.

Register Organization of 8086

All the registers of 8086 are 16-bit registers. The general purpose registers can be used as either
8-bit registers or 16-bit registers.

The register set of 8086 can be categorized into 4 different groups. The register organization of
8086 is shown in the figure.

AH
AX

AL

BH
BX

BL

SS

CH
CX

CL

DS

DH
DX

DL

ES

BP
FLAGS/
PSW

SI
DI
IP

General purpose Registers:

The registers AX, BX,CX and DX are the general purpose 16-bit registers.
[Link] is used as 16-bit accumulator. The lower 8-bit is designated as AL and higher 8-bit is designated as
AH. AL can be used as an 8-bit accumulator for 8-bit operation.
AH
AH: stores higher byte

AL

AL: stores lower byte

This is also used for input and output operations and store final result.
Ex: mov al,15h this will store immediate data 15h into al register.
[Link] data register can be used as either 16 bit or 8 bit. BX is a 16 bit register, but BL indicates the lower
8-bit of BX and BH indicates the higher 8-bit of BX.
BH
BL
The register BX is used as offset storage for forming physical address in case of certain addressing
modes.
BH: stores higher byte
BL: stores lower byte
Ex:mov bl,30h
this will store immediate data 30h into bl register
[Link] register CX is used default counter in case of string and loop instructions.
CH

CL

CH: stores higher byte

CL: stores lower byte
Ex: mov cl,15h this will store immediate data 15h into cl register
[Link] register is a general purpose register which may be used as an implicit operand or destination in
case of a few instructions.
DH
DL
DH: stores higher byte
DL: stores lower byte
Ex: mov dl,15h this will store immediate data 15h into dl register
Special Purpose Register: a) segment register
b)pointer and index registers
c)flag regiter
Segment Registers:
The 8086 architecture uses the concept of segmented memory. 8086 able to address to address a
memory capacity of 1 megabyte and it is byte organized. This 1 megabyte memory is divided into 16
logical segments. Each segment contains 64 kbytes of memory.
There are four segment register in 8086
Code segment register (CS)
Data segment register (DS)
Extra segment register (ES)
Stack segment register (SS)
Code segment register (CS): is used fro addressing memory location in the code segment of the memory,
where the executable program is stored.
Data segment register (DS): points to the data segment of the memory where the data is stored.

Extra Segment Register (ES) : also refers to a segment in the memory which is another data segment in
the memory.
Stack Segment Register (SS): is used fro addressing stack segment of the memory. The stack segment is
that segment of memory which is used to store stack data.
While addressing any location in the memory bank, the physical address is calculated from two parts:
-

The first is segment address, the segment registers contain 16-bit segment base addresses, related
to different segment.
The second part is the offset value in that segment.

The advantage of this scheme is that in place of maintaining a 20-bit register for a physical address, the
processor just maintains two 16-bit registers which is within the memory capacity of the machine.
Pointers and Index Registers.
The pointers contain offset within the particular segments.
-

The pointer register IP contains offset within the code segment.

The pointer register BP contains offset within the data segment.
He pointer register SP contains offset within the stack segment.

The index registers are used as general purpose registers as well as for offset storage in case of indexed,
base indexed and relative base indexed addressing modes.
The register SI is used to store the offset of source data in data segment.
The register DI is used to store the offset of destination in data or extra segment.
The index registers are particularly useful for string manipulation.
Intruction pointer: It holds the next instruction address to be executed.
Flag Register(or)Program Status word
The 8086 flag register contents indicate the results of computation in the ALU. It also contains some flag
bits to control the CPU operations.
A 16 flag register is used in 8086. It is divided into two parts .
(a) Conditional flags :Trap,Interrupt,Direction flag
(b) status flags:carry ,parity,auxillary carry,zero,sign flags
The condition code flag register is the lower byte of the 16-bit flag register. The condition code flag
register is identical to 8085 flag register, with an additional overflow flag.
The control flag register is the higher byte of the flag register. It contains three flags namely direction
flag(D), interrupt flag (I) and trap flag (T).

The complete bit configuration of 8086 is shown in the figure.

15 14 13 12 11 10 9 8
X X X X 0

D I

T S Z

4 3

X AC X P X CY

O-overflow flag
D-direction flag
I-Interrupt flag
T-Trap flag
S-sign flag
Z-zero flag
Ac-Auxillary carry flag
P-parity flag
Cy-carry flay
X-not used/unreserved
S- Sign Flag : This flag is set, when the result of any computation is negative.
10000110
00000111
10001101 s:set to 1
Z- Zero Flag: This flag is set, if the result of the computation or comparison performed by the previous
instruction is zero.
Ex:10000110
00000111
10001101 z:set to 1
P- Parity Flag: This flag is set to 1, if the lower byte of the result contains even number of 1s.
Ex:10000110
00000111
10001101 p:set to 1
C- Carry Flag: This flag is set, when there is a carry out of MSB in case of addition or a borrow in case
of subtraction.
Ex: 10000110
00000111
10001101 c:set to 0
T- Tarp Flag: If this flag is set, the processor enters the single step execution mode.
I- Interrupt Flag: If this flag is set, the maskable interrupt are recognized by the CPU, otherwise they
are ignored.
D- Direction Flag: This is used by string manipulation instructions. If this flag bit is 0, the string is
processed beginning from the lowest address to the highest address, i.e., auto incrementing mode.
Otherwise, the string is processed from the highest address towards the lowest address, i.e., auto
incrementing mode.
AC-Auxilary Carry Flag: This is set, if there is a carry from the lowest nibble, i.e, bit three during
addition, or borrow for the lowest nibble, i.e, bit three, during subtraction.

O- Over flow Flag: This flag is set, if an overflow occurs, i.e, if the result of a signed operation is large
enough to accommodate in a destination register. The result is of more than 7-bits in size in case of
8-bit signed operation and more than 15-bits in size in case of 16-bit sign operations, then the
overflow will be set.
Eg:8-bit range is-127 to +128

Memory Segmentation (or) memory organisation:

The size of address bus of 8086 is 20 and is able to address 1 Mbytes ( 220 ) of physical memory.
The compete 1 Mbytes memory can be divided into 16 segments, each of 16 Kbytes size.
The addresses of the segment may be assigned as 0000H to F000H respectively.
The offset values are from 0000H to FFFFFH.
If the segmentation is done as per above mentioned way, the segments are called non-overlapping
segments.
In some cases segment may overlap also. Suppose a segment starts at a particular address and its
maximum size can go up to 64 Kbytes. But if another segment starts before this 64 Kbytes location of
the first segment, the two segments are said to be overlapping segment.
The area of memory from the start of the second segment to the possible end of the first segment is
called as overlapped segment.
Non-Overlapping Segments
The main advantages of the segmented memory scheme are as follows:
a) Allows the memory capacity to be 1 Mbyte although the actual addresses to be handled are of
16-bit size
b) Allows the placing of code data and stack portions of the same program in different parts
(segments) of memory, for data and code protection.
c) Permits a program and/ or its data to be put into different areas of memory each time program is
executed, ie, provision for relocation may be done.
. Non-overlapping segments and overlapping segments are shown in the figure

Fig: Non-Overlapping Segments

fig:Overlapping Segments

Addressing modes of 8086

Addressing mode represent the different ways of locating data.
[Link] Addressing Mode:
[Link]
[Link]
[Link] Indirect
[Link]
[Link] Relative
[Link] Indexed
[Link] Based Index
[Link] Segment Direct Mode
[Link] Segment Indirect Mode
[Link] Segment Direct Mode
[Link] Segment Indirect Mode
[Link] Addressing Mode: Immediate Data Is A Part Of Instruction.
Ex:Mov Ax,0005h
[Link] Addressing Mode:It Performs Direct And Indirect Register Operation.
Ex;Mov Ax,Bx
[Link] Addressing Mode: Offset Address Is Directly Specified
Ex:Mov Ax,[5000h]
[Link] Indirect Addressing Mode: Offset Address Specified In Registers In Indirect Way.
Ex:Mov Ax,[Bx]
[Link]: Offset Address Specified In Index Registers.
Ex:Mov Ax,[SI]

[Link] Relative :The Data Is Available At An Effective Address Formed By Adding An 8-Bit Or 16Bit Displacement.
Ex:Mov Ax,50h[Bx]
[Link] Indexed: The Effective Address Of Data Is Formed By Adding Base Register And Index
Register .
Ex:Mov Ax,[Bx][Si]
[Link] Based Indexed:The Effective Address Is Formed By Adding An 8-Bit Or 16-Bit
Displacement And Base ,Index Registers.
Ex:Mov Ax,50h[Bx][Si]
9. Intra Segment Direct Mode:the address to which the control is to be transferred lies in same segment.
Ex:JMP SHORT LABLE (LABLE lies -128 to +127)
10. Intra Segment Indirect Mode: the address to which the control is to be transferred lies in same
segment but indirect wayEx:JMP [BX]
11. Inter Segment Direct :the address control is transfer in different segments in direct lacation
Ex:JMP 2000H:5000H
12. Inter Segment InDirect: the address control is transfer in different segments indirectly
Ex;jmp [Bx]

Assembler Directives
The main advantage of machine language programming is that the memory control is directly in
the hands of the programmer/user.
List out the assembler directives
[Link]:Define Byte the DB directive is used to reserve byte of memory location
Ex/stmt: rank DB 01H,02H,03H,04H
[Link]:Define Word the DW directive is used to reserve two byte of memory location
Ex:key DW 1234H,4567H,78ADH
[Link]:Define Quadword the DQ directive is used to reserve 4 words of memory location
Ex:words DQ 1234H,4567H,78ADH
[Link]:Define ten bytes the DT directive is used to reserve 10-bytes of memory location
Ex:ten DT 1234H,4567H,78ADH
[Link]:Assume logical segment Name
The Assume directive is used to names the different logical segments
Ex:ASSUME CS:CODE,DS:DATA,ES:EXTRA,SS:STACK
[Link]:end of program
The end directive is used to the end of progatm
[Link]:end of procedure
The sub program ends with endp.
Ex:PROCEDURE STAR
------STAR ENDP
[Link]:end of segment
The segments are ends with ENDS
Ex:DATA SEGMENT
------DATE ENDS
[Link]:Align on even memory address
Even Alignment of available memory location.
Ex: EVEN
PROCEDURE ROOT
---ROOT ENDP
[Link]:equate
The directive EQU is used to assign a lable with a value or symbol.
Ex: LABLE EQU 0500H
ADDITION EQU ADD

11.*EXTRN&PUBLIC:External and public

The directive EXTRN informs the assembler that the names, procedures and labels declared after
this directive have already been define in some other program modules.
Ex:MODULE1 SEGMENT
PUBLIC FACTORIAL FAR
MODULE1 ENDS
MODULE2 SEGMENT
EXTRN FACTORIAL FAR
MODULE2 ENDS
12.*GROUP:Group The Related Segments
This directive is used to form logical groups of segments with similar type.
Ex:PROGRAM GROUP DATA,STACK,CODE
[Link]:label
The label directive is used to assign a name to the current content of the location counter.
Ex: labels are NEAR,FAR Label BYTE or WORD labels etc.
[Link]:Byte Length Of The Label
This directive is not available in [Link] is used to refer to the length of a data array or a
string.
Ex: MOV CX,LENGTH ATRRAY
[Link]:local
The labels ,variables, constants or procedure declared LOCAL in a module are used in particular
module only.
Ex:LOCAL a,b,data,array
[Link]:Logical Name Of A ModuleThe NAME directive is used to assign a name to an assembly
language program module.
[Link]:offset of a label
The offset operator along with alabel.
Ex:CODE SEGMENT
MOV SI,OFFSET LIST
CODE ENDS
[Link]:origin
The org directive directs the assemblr to start the memory allotment for the particular segment.
Ex:ORG 1200H
[Link]:Pointer
Pointer oprator is used to declare the type of label,variable or memory operand.
Ex:MOV AL,BYTE PTR [SI]
[Link]:segment of a label
The seg operator is used to decide the segment address of the label.
Ex:MOV AX,SEG ARRAY
MOV DS,AX

21.*GLOBAL
the labels variable constants or procedures declared global may be used by other modules of the
program.
Ex:ROUTINE PROC GLOBAL
[Link]
the short operator indicates to the short jump -128 to +127 bytes
ex:jmp short label
23.+&- OPERATORS :
These operators represents arithmetic addition and subtraction.
ex:Mov [si+2]
Mov dx,[bx-5]
[Link] PTR:
This directive indicates far pointer .
Ex:JMP FAR PTR LABEL
[Link] PTR :
This directive indicates near pointer.
Ex:JMP NEAR PTR LABEL

MACRO and PROCEDURE

Macro

Main program the set of instructions are repeated again and again the program is called macro.
The macro program occupies more memory space.
The macro ends with ENDM
Syntax: Display macro
Start:------------Display ENDM
End start
The macro program is fast execution than procedure.

Procedure
The sub program is called procedure
When the group of same instructions repeated again the program becomes lengthy and complex
to separate the program and store in other memory location called as subprogram or procedure.
The used instructions are CALL and RET .
Syntax:Display procedure
Start:------------- sub program
---------Display ENDP

The procedure program occupies less memory space.

The calling parameters are

[Link] parameter in register

[Link] parameter in memory
[Link] parameter using pointer register
[Link] parameter in stack
Nested Procedure:

The address is pushed into stack pointer and instruction pointer load with sub program address
after execution of sub program stack pointer address is reload with IPDifference between macro and
procedure:
Macro
[Link] are used for short sequence of
instructions, preferably below 10 instructions
[Link] does not requires CALL and RET
instructions
[Link] execute faster when compare with
procedure
[Link] are passed as part of a statement
which calls macro
[Link] eliminates the overhead time
requirement.
[Link] ends with ENDM
[Link] of execution remains in the main
program
[Link] occupies more memory space

Procedure
[Link] program are used for long sequence of
instructions, preferably more than 10 instructions.
[Link] requires CALL and RET instruction
[Link] is slower compare to macro
[Link] are passed in register, memory
locations or stack.
[Link] require over head time
[Link] ends with ENDP
[Link] of execution is transferred to the
procedure
[Link] occupies less memory space

Unit-III
PIN CONFIGURATION 8086
The 8086 is a 16-bit microprocessor. This microprocessor operate in single processor or multiprocessor
configurations to achieve high performance. The pin configuration of 8086 is shown in the figure. Some
of the pins serve a particular function in minimum mode (single processor mode) and others function in
maximum mode (multiprocessor mode).

Fig:8086 pin configuration

Description of signals of 8086
AD7 AD0 The address/ data bus lines are the multiplexed address data bus and contain
the right
most eight bit of memory address or data. The address and data bits are separated by using
ALE signal.
AD15 AD8 The address/data bus lines compose the upper multiplexed address/data bus. This lines
contain address bit A15 A8 or data bus D15 D8 . The address and data bits are separated
by using ALE signal.
A19 / S6 A18 / S3 The address/status bus bits are multiplexed to provide address signals A19 A16 and also
status bits S6 S3 . The address bits are separated from the status bits using the ALE
signals. The status bit S6 is always a logic 0, bit S5 indicates the condition of the

interrupt flag bit. The S4 and S3 combinedly indicate which segment register is
presently being used for memory access.

S4
0
0
1
1

S3
0
1
0
1

Funtion
Extra segment
Stack segment
Code or no segment
Data Segment

BHE / S7 The bus high enable (BHE) signal is used to indicate the transfer of data over the higher order

D15 D8 data bus. It goes low for the data transfer over

D15 D8 and is used to derive chip

select of odd address memory bank or peripherals.

BHE
0
0
1
1
RD

A0
0
1
0
1

Indication
Whole word
Upper byte from or to odd address
Lower byte from or to even address
None

: Read : whenever the read signal is at logic 0, the data bus receives the data from the memory or
0 devices connected to the system

READY :This is the acknowledgement from the slow devices or memory that they have completed the
data transfer operation. This signal is active high.
INTR: Interrupt Request: Interrupt request is used to request a hardware interrupt of INTR is held high
when interrupt enable flag is set, the 8086 enters an interrupt acknowledgement cycle after the
current instruction has completed its execution.
TEST : This input is tested by WAIT instruction. If the TEST input goes low; execution will continue.
Else the processor remains in an idle state.
NMI- Non-maskable Interrupt: The non-maskable interrupt input is similar to INTR except that the NMI
interrupt does not check for interrupt enable flag is at logic 1, i.e, NMI is not maskable internally
by software. If NMI is activated, the interrupt input uses interrupt vector 2.
RESET: The reset input causes the microprocessor to reset itself. When 8086 reset, it restarts the
execution from memory location FFFF0H. The reset signal is active high and must be active for
at least four clock cycles.
CLK : Clock input: The clock input signal provides the basic timing input signal for processor and bus
control operation. It is asymmetric square wave with 33% duty cycle.
Vcc 5V power supply for the operation of the internal circuit

COND Ground for the internal circuit

MN / MX : The minimum/maximum mode signal to select the mode of operation either in minimum or
maximum mode configuration. Logic 1 indicates minimum mode.
Minimum mode Signals: The following signals are for minimum mode operation of 8086.
M / IO -Memory/IO M / IO signal selects either memory operation or o operation. This line indicates
that the microprocessor address bus contains either a memory address or an o port address.
Signal high at this pin indicates a memory operation. This line is logically equivalent to S 2 in
maximum mode.
INTA - Interrupt acknowledge: The interrupt acknowledge signal is a response to the INTR input signal.
The INTA signal is normally used to gate the interrupt vector number onto the data bus in
response to an interrupt request.
ALE- Address Latch Enable: This output signal indicates the availability of valid address on the
address/data bus, and is connected to latch enable input of latches.
DT / R : Data transmit/Receive: This output signal is used to decide the direction of date flow through
the bi-directional buffer. DT / R 1 indicates transmitting and DT / R 0 indicates receiving the
data.
Data Enable: Data bus enable signal indicates the availability of valid data over the
DEN
address/data lines.
HOLD: The hold input request a direct memory access(DMA). If the hold signal is at logic 1, the micro
process stops its normal execution and places its address, data and control bus at the high
impedance state.
HLDA: Hold acknowledgement indicates that 8086 has entered into the hold state.
Maximum mode signal: The following signals are for maximum mode operation of 8086.
S 2 , S1 , S0 - Status lines: These are the status lines that reflect the type of operation being carried out by
the processor.
These status lines are encoded as follows
S2
0
0
0
0
1
1

S1
0
0
1
1
0
0

S0
0
1
0
1
0
1

Function
Interrupt Acknowledge
Read i/o port
Write i/o port
Halt
Code Access
Read memory

1
1

1
1

0
1

Write memory
passive

LOCK : The lock output is used to lock peripherals off the system, ie, the other system bus masters will
be prevented from gaining the system bus.
QS1 and QS0 - Queue status: The queue status bits shows the status of the internal instruction queue. The
encoding of these signals is as follows
QS1
0
0
1
1

QS0
0
1
0
1

Function
No operation, queue is idle
First byte of opcode
Queue is empty
Subsequent byte of opcode

RQ / GT 1 and RQ / GT 0 - request/Grant: The request/grant pins are used by other local bus masters to
force the processor to release the local bus at the end of the processors current bus cycle. These
lines are bi-directional and are used to both request and grant a DMA operation. RQ / GT 0 is
having higher priority than RQ / GT 1
Physical Memory Organization
In an 8086 based system, the 1Mbyte memory is physically organized as odd bank and even bank, each
of 512kbytes, addressed in parallel by the processor.
Byte data with even address is transferred on D7 D0 and byte data with odd address is transferred on
D15 D8 .
The processor provides two enable signals, BHE and A0 for selecting of either even or odd or both the
banks.

BHE
0
0
1
1

FIG
Function
A0
0
Whole word
1
Upper byte/ odd address
0
Lower byte/even address
1
none

D15 D0 / A15 A0 are the

common signal line in 8086 as
AD15 AD0

If the address bus contains FFFFOH

If BHE 0 , then it reads the 16 bits data from memory location FFFFOH and FFFF1H .
If BHE 1 , it reads the 8 bits data from memory location FFFFOH