MOSFET: Introduction

Metal Oxide Semiconductor Field Effect Transistor (MOSFET) is widely

used to implement digital designs
High integration density
Relatively simple manufacturing process
It is therefore possible to realize 106-7 transistors on an Integrated Circuit
(IC) economically

The MOS Transistor

Gate Oxide
Source

Gate
Polysilicon

n+

Drain
n+

p-substrate

Field-Oxide
(SiO2 )
p+ stopper

Heavily doped n-type source and drain regions are implanted

(diffused) into a lightly doped p-type substrate (body)
A thin layer (approx. 50 A0) of silicon dioxide (SiO2) is grown
over the region between source and drain and is called thin or
gate oxide

 Gate oxide is covered by a conductive material, often polycrystalline

silicon (polysilicon) and forms the gate of the transistor
MOS transistors are insulated from each other by thick oxide
(SiO2) and reverse biased p-n+ diode
Adding p+ field implant (channel stop implant) makes sure a
parasitic MOS transistor is not formed
MOS Transistor as a switch
Vin > VT : a conducting channel is formed between source and
drain and current flows
Vin <VT : the channel does not form and switch is said to be
Open
Vin >VT : current is a function of gate voltage

NMOS, PMOS, and CMOS

Technology
In an NMOS transistor, current is carried by electrons (from
source, through an n-type channel to the drain
Different than diode where both holes and electrons contribute
to the total current
Therefore, MOS transistor is also known as unipolar device
Another MOS device can be formed by having p+ source and
drain and n-substrate (PMOS)
Current is carried by holes through a p-type channel
A technology that uses NMOS (PMOS) transistors only is
called NMOS (PMOS) technology
In NMOS or PMOS technologies, substrate is common and is
connected to +ve voltage, GND (NMOS) or VDD (PMOS)

In a complementary MOS (CMOS) technology, both PMOS

and NMOS transistors are used
NMOS and PMOS devices are fabricated in isolated region
from each other (i.e., no common substrate for all devices)

MOS transistor is a 4 terminal device, if 4th terminal is not

shown it is assumed to be connected to appropriate voltage

Static Behavior
Only the NMOS transistor is discussed, however, arguments
are valid for PMOS transistor as well
The threshold voltage
Consider the case where Vgs = 0 and drain, source and bulk
are connected to ground

Static Behavior
Under these conditions (no channel), source and drain are connected
by back to back diodes having 0 V bias (no conduction)
Hence, high resistance between source and drain (107 )
If now the gate voltage (VGS) is increased, gate and substrate form
plates of a capacitor with oxide as dielectric
+ve gate voltage causes +ve charge on gate and -ve charge
on the substrate side
In substrate it occurs in two steps (i) depletion of mobile
holes, (ii) accumulation of -ve charge (inversion)

At certain Vgs, potential at the interface reaches a critical

value, where surface inverts to n-type (start of strong inversion)
Further VGS increase does not increase the depletion width
but increases electrons in the inversion layer
Threshold Voltage
where

VT = VT 0 + [ 2F + VSB 2F ]
where

2qsiNA
COX

VT is +ve for NMOS and -ve for PMOS devices

Current-Voltage Relationship

When VGS >VT

Let at any point along the channel, the voltage is V(x) and
gate to channel voltage at that point is VGS -V(x)

If the Vgs -V(x) >VT for all x, the induced channel charge per
unit area at x

Qi ( x) = COX [Vgs V ( x) VT ]

Current is given by

I D = ( x ) Q i ( x )W
The electron velocity is given by

n = nE ( x ) = n
Therefore,

dV
dx

IDdx = nCOXW (Vgs V VT )dV

Integrating the equation over the length L yields

2

W
Vds
]
ID = K ' n [(Vgs VT )Vds
2
L
2

Vds
]
ID = Kn[(Vgs VT )Vds
2

or

Kn is known as the process trans-conductance parameter and

equals

K ' n = nCOX = n

ox
tox

If the VGS is further increased, then at some x, Vgs - V(x) <VT

and that point the channel disappears and transistor is said to
be pinched-off
Close to drain no channel exists, the pinched-off condition in
the vicinity of drain is VGS - VDS VT
Under these conditions, transistor is in the saturation region
If a complete channel exists between source and drain, then
transistors is said to be in triode or linear region
Replacing Vds by Vgs -VT in the current equation we get,
MOS current-voltage relationship in saturation region

K'n W
ID =
(Vgs VT ) 2
2 L

This equation is not entirely correct, the position of pinch-off

point and hence the effective channel length is a function of
Vds, a more accurate equation is given as

ID =

K'n W
(Vgs VT ) 2 [1 + Vds ]
2 L

ID (mA)

Triode

VGS = 5V

Saturation
VGS = 4V

VGS = 3V
VGS = 2V
VGS = 1V

0.0

1.0

2.0

3.0

4.0

VDS (V)
(a) ID as a function of V DS

5.0

0.020
ID

VDS = V GS-VT

Square Dependence

where is an empirical constant parameter called channel

length modulation factor

0.010

Subthreshold
Current

0.0

2.0
VT1.0
VGS (V)

(b) ID as a function of V GS
(for VDS = 5V).

3.0

Dynamic Behavior
G

CGS

CGD
D

CGB

CSB

CDB

Dynamic Behavior
MOS transistor is a unipolar (majority carrier) device, therefore,
its dynamic response is determined by time to (dis)charge various
capacitances
MOS capacitances
Gate oxide capacitance: COX = per unit area,
ox
gate
=
C
WL
for a transistor of width, W and length, L, the

tox

From current equation it is apparent that Cox should

be high or gate oxide thickness should be small
Gate capacitance consists of several components
Source and drain diffusions extend below the thin oxide (lateral
diffusion) giving rise to overlap capacitance

MOS Overlap Capacitance

Source and drain diffusions extend below the thin oxide (lateral
diffusion) giving rise to overlap capacitance
Xd is constant for a technology and this capacitance is linear
and has a fixed value CgsO = CgdO = CoxXdW = CoW

Average Gate Capacitance

Different distributions of gate capacitance for varying
operating conditions

Most important regions in digital design: saturation and cut-off

Diffusion Capacitance

The Sub-Micron MOS Transistor

Short Channel Effects
Threshold Variations
Parasitic Resistances
Velocity Sauturation and Mobility Degradation
Subthreshold Conduction
Latchup

Threshold Variations
VT

VT
Long-channel threshold

L
Threshold as a function of
the length (for low VDS )

Low VDS threshold

VDS
Drain-induced barrier lowering
(for low L)

Parasitic Resistances
Polysilicon gate
LD

Drain
contact

S
RS

VGS,eff

RD
Drain

With transistor scaling, junctions are made shallower & contacts

windows are made smaller while their depth is increased
Technology and design objective is to reduce source-drain
resistance
Often source drain regions are covered by titanium or tungsten
(silicidation) to reduce the resistance

sat = 107
constant velocity

Constant mobility (slope = )

Esat = 1.5

E (V/ m)

(a) Velocity saturation

n (cm2 /Vs)

n (cm/sec)

Variation in I-V Characteristics

700

n0

250
0

Et (V/ m)

100

(b) Mobility degradation

Variation in I-V Characteristics

While developing the I-V equation we assumed that carrier
velocity is proportional to E
However, as E = Esat (approx. 104/micron), the carrier velocity
saturates, as a consequence

IDSAT = satCoxW (Vgs VDsat VT )

In long channel MOSFET we also assumed that there is no
vertical electric field
However, as transistor scales, Evertical can not be ignored
Carrier mobility is decreased as vertical electric field is
increased

Variation in I-V Characteristics

1.5

0.5

ID (mA)

VG S = 3
0.5
VG S = 2
VG S = 1
0.0

1.0

2.0
3.0
VDS (V)

4.0

(a) ID a s a function of V DS

5.0

ID (mA)

VG S = 4

1.0

Line a r De p e n d e n c e

VG S = 5

0
0.0

1.0
2.0
V G S (V)

(b) ID a s a function of V G S
(for VDS = 5 V).

Line ar De pe ndence o n VGS

3.0

Sub-Threshold Conduction
102

ln(ID) (A)

104

Linear region

106
108
1010
10120.0

Subthreshold exponential region

VT 1.0

VGS (V)

2.0

3.0

Latchup
VDD
+

Rnwell

n-well
Rpsubs

VD D

p-source

Rnwell

p-substrate
(a) Origin of latchup

n-source

Rpsubs

(b) Equivalent circuit

SPICE MODELS
Level 1: Long Channel Equations - Very Simple
Level 2: Physical Model - Includes Velocity
Saturation and Threshold Variations
Level 3: Semi-Emperical - Based on curve fitting
to measured devices
Level 4 (BSIM): Emperical - Simple and Popular

MAIN MOS SPICE PARAMETERS

SPICE Parameters for Parasitics

Technology Scaling & CMOS

Ever since ICs were invented, dimensions are scaled to
Integrated more transistors in the same area
Allow higher operational speed
Scaling has profound impact on many aspects of ICs
Constant Voltage Scaling
All device dimensions are scaled by a factor S
Voltage (i.e., VDD) after the scaling is same as before
This method of scaling is followed till 0.8 micron
However for lower geometries, higher electric field resulted in
poor device reliability

Technology Evolution

Process Variations
Devices parameters vary between runs and even on
the same die!
Variations in the process parameters, such as impurity concentration densities, oxide thicknesses, and diffusion depths. These are caused by nonuniform conditions during the deposition and/or the diffusion of the
impurities. This introduces variations in the sheet resistances and transistor parameters such as the threshold voltage.
Variations in the dimensions of the devices, mainly resulting from the
limited resolution of the photolithographic process. This causes (W/L)
variations in MOS transistors and mismatches in the emitter areas of
bipolar devices.

Impact of Device Variations

2.10
2.10
Delay (nsec)

Delay (nsec)

1.90

1.90

1.70

1.70

1.50
1.10 1.20 1.30 1.40 1.50 1.60
Leff (in mm)

1.50
0.90

0.80

0.70

0.60 0.50

VTp (V)

Delay of Adder circuit as a function of variations in L and VT