C:/Users/ASIC/Desktop/Project/MIPI LLI/RttTimer.

//----------------------------------------------------------------------------------// Title : RttTimer // Project : Janus //-----------------------------------------------------------------------------------// File : RttTimer.v // Author : Vipul kumar <vipul_kumar@[Link]> // Created : [Link].2011 // Last modified : [Link].2011 //-----------------------------------------------------------------------------------// *******SVN Revision History************* // Change for specific Revision Tool // $Date: // $Author: // $HeadURL: // $Revision: //-----------------------------------------------------------------------------------// Description : // RTT timer generates self acknowledgement signal along with sequence number to evict packet from replay buffer. // Whenever a packet is being stored in Replay buffer, SyncFifo stores current time stamp. // The Packets that are transmitted have to be kept track of. There is no concept of Acks so no receive // of Nack until Round trip time of packet from sent time is inferred as Ack. After this time the entry for that packet // in transmit replay buffer is flushed // //-----------------------------------------------------------------------------------// Agilent Confidential // Copyright (c) 2010 by Agilent This model is the confidential and // proprietary property of Agilent and the possession or use of this // file requires a written license from Agilent. //-----------------------------------------------------------------------------------module RttTimer ( clkTxDll resetAsync_n rxPrepSync SW_MAX_RTT_TIME SnumfromInsrt pktEnable dataValidBuffer getNack bufferNotEmpty txPaHold selfAck seqNum TxDllHold fifoAlmostFull );

, , , , , , , , , , , , ,

parameter P_FREE_COUNT_MAX

= 16777215

;// Free counter maximum value ;// System clock ;// Async reset ;// Link is in PREPARE or SYNC ;// Maximum round trip time ;// sequence number from seq

//Input Ports declaration input clkTxDll input resetAsync_n input rxPrepSync state input [23:0] SW_MAX_RTT_TIME input [5:0] SnumfromInsrt inserter block

input pktEnable ;// Valid packet is coming (data valid due to TxTl data valid and data valid buffer)
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input input received properly) input replay buffer input

dataValidBuffer ;// Valid from replay buffer getNack ;// NACK is there (Packet not bufferNotEmpty txPaHold ;// Buffer not empty from ;// Hold signal from PA layer ;// Self acknowledgement ;// Self ack generated for this ;// Stop taking data from ;// Stop taking data from TL as

//Output Ports declaration output selfAck indicator output [5:0] seqNum sequence number packet output TxDllHold sequence inserter as buffer is full output fifoAlmostFull buffer is almost full

//------------Internal Variables------------------------------------------------reg selfAck ;// It Indicates to replay buffer to evicts its packet reg [5:0] seqNum ;// It Indicates to replay buffer to evicts its packet with specified sequence number reg [23:0] freeCntOut by comparator block wire [23:0] fromDpram compared with freerun count value wire reg reg wire reg wire wire wire ;// Counter output will be used ;// Dpram output , which is

[1:0]

empty ;// DPRAM empty indicaton stopDataWrite ;// stop taking data from TL getNack_d ;// delay getnack fifoFull ;// Dpram full status dataValidBuffer_d;// datavalidbuffer latched readEnable ;// Read enable for dpram incRdPtr ;// Read enable for dpram writeEnable ;// Write enable to DpRam

//---------------- Code starts here --------------------------------------------//Following block implements a counter which can run freely upto maximum limit //counter will be reset to zero value if link is in hibernate stste always @(posedge clkTxDll or negedge resetAsync_n) begin if (!resetAsync_n)begin freeCntOut <= 24'd0 ; end//(!resetAsync_n) else if (rxPrepSync | txPaHold) begin freeCntOut <= freeCntOut ; end else begin freeCntOut <= freeCntOut + 1'b1; end end//always // Stop taking data from TL, if link is in prep/sync state always @(posedge clkTxDll or negedge resetAsync_n) begin if (!resetAsync_n)
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stopDataWrite<= 1'b0; else if (rxPrepSync ) //else if (rxPrepSync | txPaHold) stopDataWrite<= 1'b1; else stopDataWrite<= 1'b0; end//always // Read enable for Dpram assign incRdPtr[0] = empty ? 1'b0: SW_MAX_RTT_TIME ) ; assign incRdPtr[1] = empty ? 1'b0: freeCntOut)) == SW_MAX_RTT_TIME) ; assign readEnable ((freeCntOut - fromDpram ) >= ((P_FREE_COUNT_MAX - (fromDpram -

= (!empty) & (|incRdPtr) & (!txPaHold) ;

// Stop taking data from TL, if link is hibernate state // Generate Hold if link is in hibernate sate or Dpram is full assign TxDllHold = stopDataWrite | fifoFull ; // Write and read pointer generation for Dpram // Write enable for Dpram assign writeEnable = pktEnable & (!TxDllHold) & (!txPaHold) & (!fifoFull) ; always @(posedge clkTxDll or negedge resetAsync_n) begin if (!resetAsync_n) getNack_d<= 1'b0; else getNack_d<= getNack; end//always

//**************************************************************************************

// SyncFifo stores free run counter value .Its ouput is used to generate self acknowledgement for packets// //**************************************************************************************

FifoSync64x24 inst_RttTimer_FifoSync64x24( .clock ( clkTxDll ), .data ( freeCntOut ), .rdreq ( readEnable ), .sclr ( getNack_d ), .wrreq ( writeEnable ), .almost_full ( fifoAlmostFull ), .empty ( empty ), .full ( fifoFull ), .q ( fromDpram ), .usedw ( ) ); // // // // following block generates self acknowlwdgement and sequence number for replay buffer to evict its stored packets. When data packet will spent RTT Max in buffer , self Ack will be generated for that seq no. data packet

always @(posedge clkTxDll or negedge resetAsync_n)begin if (!resetAsync_n) begin selfAck <= 1'b0 ; seqNum <= 6'd63 ;
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end// (!resetAsync_n) else if (getNack| getNack_d ) begin selfAck <= 1'b0 ; seqNum <= seqNum ; end else if(readEnable)begin selfAck <= 1'b1 ; seqNum <= seqNum + 1'b1 ; end// else begin selfAck seqNum end// else end endmodule //---------------- Code ends here --------------------------------------------<= 1'b0 <= seqNum ; ;

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