EC 507 Digital Electronics Laboratory Dept.
of Electronics &Communication Engineering
Exp No: 9 Date :
ASYNCHRONOUS COUNTER
AIM
To setup the following asynchronous counters and study their working 4 bit binary up counter 4 bit binary down counter decade counter 3 bit up/down counter using
ode control
COMPONENTS AND EQUIPMENTS REQUIRED
!"#$4$% !"#$4&& !" Trainer 'it
THEORY
( counter is a circuit that produces a set of a uni)ue output co bination in relation to the nu ber of applied input pulses* The nu ber of uni)ue outputs of a counter is known as its odulus or ode nu ber* !n asynchronous counters+ the flip flops are not gi,en the clock si ultaneously* Therefore the propagation delay increases with the nu ber of flip flops used* -our .#' flip flops ust be used to toggle ode to count /% states* 4 BIT BINARY UP COUNTER !n the circuit setup+ all flip flops were clocked by the 0 output of the preceding flip flop* .' inputs of the flip flops were connected to a high state* $4$% is a dual .' 1aster 2la,e -lip flop with preset and clear* ( ripple counter co prising of 3n4 flip flops can be used to count up to 35 n4pulses* ( circuit with 4 flip flops gi,es a axi u count of 54 6/%* The counter gi,es a natural binary count fro 3&4 to 3/74 and resets to initial condition on /%th pulse* 8ith the application of first clock pulse 0 & changes fro & to /* 0/+ 05 and 03 re ain unaffected* 8ith 5nd clock pulse 0& beco es 3&4 and 0/ beco es 3/4* (t the arri,al of /7th clock pulse all the 0 outputs will beco e 3/4* (t the /% th clock pulse all 0 outputs reset and the cycle repeats* 4 BIT BINARY DOWN COUNTER !n this circuit+ the succeeding flip flops were clocked by the 0 output of the preceding flip flops* The outputs were taken fro the 0 outputs* !nitially all 0 outputs were set* (t the arri,al of the /% th clock pulse all 0 outputs beco e reset and cycle continues*
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EC 507 Digital Electronics Laboratory Dept. of Electronics &Communication Engineering
THREE BIT UP/DOWN COUNTER The direction of the counting se)uence is ade dependent on a ode control input* ( logic circuit connected between flip flops does a ear:ob of connecting either of 0 or 0* ;utput of preceding flip flop is connected to the clock input of succeeding flip flop* 8hen ode control is /+ 0 outputs were connected to the clock inputs of the succeeding flip flop* !f ode control is 3&4+ 0 outputs were connected to clock inputs* DECADE COUNTER The !"#$49& is a decade counter < ode#/&= which consists of 4 1aster 2la,e flip flops internally connected to pro,ide a di,ide by 5 counter and di,ide by 7 counter as shown* >ated direction reset lines are pro,ided to inhibit count inputs to either a logic ?ero or a @"D count of 394* 2ince the output 0 ( fro --( is not internally connected to the succeeding stages+ the count ay be separated into 3 independent count odes* 4 BIT BINARY UP COUNTER "A' & / 5 3 4 7 % $ 9 9 /& // /5 /3 /4 /7 03 & & & & & & & & / / / / / / / / 03 & & & & / / / / & & & & / / / / 0/ & & / / & & / / & & / / & & / / 0& & / & / & / & / & / & / & / & / 4BIT BINARY DOWN COUNTER "A' & / 5 3 4 7 % $ 9 9 /& // /5 /3 /4 /7 03 / / / / / / / / & & & & & & & & 05 / / / / & & & & / / / / & & & & 0/ / / & & / / & & / / & & / / & & 0& / & / & / & / & / & / & / & / &
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EC 507 Digital Electronics Laboratory Dept. of Electronics &Communication Engineering
3 BIT BINARY UP COUNTER 1 05 0/ 0& / / / / / / / / & & & & / / / / & & / / & & / / & / & / & / & /
3 BINARY DOWN COUNTER 1 05 0/ 0& & & & & & & & & / / / / & & & & / / & & / / & & / & / & / & / &
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EC 507 Digital Electronics Laboratory Dept. of Electronics &Communication Engineering
03 & / 5 3 4 7 % $ 9 9 & & & & & & & & / /
03 & & & & / / / / & &
0/ & & / / & & / / & &
0& & / & / & / & / & /
PROCEDURE
/* 5* 3* 4* 7* Test all !"4s using a digital !" tester* (lso test all wires for continuity using a ulti eter or !" trainer 2etup the circuit for 4 bit ripple counter* connect all the preset pins toB7 C to disable it "lear the entire flip flop outputs initially connecting co on clear ter inal to logic&4* (fter the usage of clear pins+ connect the to logic 3/4* (pply ono pulses* "ounter starts counting up* 1o,e clock inputs of e,ery flip flop except --& fro output of pre,ious states* 2et up other counters in si ilar way and obser,e*
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EC 507 Digital Electronics Laboratory Dept. of Electronics &Communication Engineering
4 BIT BINARY UP COUNTER
4 BIT BINARY DOWN COUNTER
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EC 507 Digital Electronics Laboratory Dept. of Electronics &Communication Engineering
DECADE COUNTER
3 BIT UP/ DOWN COUNTER KMEA Engineering College, Coc in ! "#$ 5"% Page73
EC 507 Digital Electronics Laboratory Dept. of Electronics &Communication Engineering
RESULT
Designed and set up the following asynchronous counters using .' flip flop 4 bit binary up counter 4 bit binary down counter 3 bit binary up / down counter Decade counter DDDDDDDDDDDDDDDDDDDD
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