RISC - ARCHITECTURE
BITS Pilani, Pilani Campus
Complex instructions have certain disadvantages that a small percentage of such instructions can sometimes reduce a computers overall performance. Processors having small simple instructions each having k time units, it can execute 100 instructions in 100k time units If 5% of instructions are slow requiring 21K units each, to execute an average set of 100 instructions requires (5*21 +95)k = 200 time units.
--- double overall program execution time
BITS Pilani, Pilani Campus
Reduced Instruction Set Computer
- Relatively few instructions - Relatively few addressing modes - Memory access limited to load and store - Fixed length and easily decodable instruction format - Hardwired mostly - Relatively large number of registers in the processor - Efficient Instruction pipeline
BITS Pilani, Pilani Campus
Example - RISC Architectures -Hewlett Packard PA- RISC -IBM and MOTOROLA Power PC -SGI MIPS -SPARC Developed by SUN Microsystems -ARM Advanced RISC machine
BITS Pilani, Pilani Campus
Processor chosen for study
Register Set: 32 bit general purpose registers- 31 in number (R1-R31) Register R0 Special purpose , value always zero, used to synthesize a variety of functions.
Floating point registers (FPRs) used as single precision (32-bit) registers.
Data Types: 8-bit, 16-bit, 32-bit for integer data 32-bit single precision, 64-bit double precision
BITS Pilani, Pilani Campus
Addressing Modes:
Immediate and displacement both with 16-bit fields
(register + offset (displacement (or) based)
Since one register that has zero always when used in addressing mode can be synthesized using r0 as the base displacement addressing.
BITS Pilani, Pilani Campus
Instruction Formats:
To provide facility for pipelining in the architecture all instructions are made of size 32-bits with a 6-bit primary opcode.
Op 6
RS1 5
RS2 5
RD 5
OP X 11
RS1 source register 1 RS2 source register 2 Rd destination register OP operation details.
BITS Pilani, Pilani Campus
LW R1, 30(R2) - Load Word
Reg [R1] mem [30 + reg( R2)]
LW R1, 1000(RO) - Load Word Reg [R1] mem [1000+0] SH R3, 502(R2) - store halfword Mem [ 502 + reg [R2]] Reg [R3]
16--------32
BITS Pilani, Pilani Campus
Overview: Processor Implementation
Single Cycle
perform each instruction in 1 clock cycle clock cycle must be long enough for slowest instruction; therefore, disadvantage: only as fast as slowest instruction
Multi-Cycle
break fetch/execute cycle into multiple steps perform 1 step in each clock cycle advantage: each instruction uses only as many cycles as it needs
Pipelined
execute each instruction in multiple steps perform 1 step / instruction in each clock cycle process multiple instructions in parallel assembly line
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
Implementing MIPS
arithmetic-logic instructions: add, sub, and, or, slt memory-reference instructions: lw, sw control-flow instructions: beq, j
6 bits
5 bits
5 bits
5 bits
5 bits
6 bits
op
6 bits
rs
5 bits
rt
5 bits
rd
shamt
16 bits
funct
R-Format
op
6 bits
rs
rt
26 bits
offset
I-Format J-Format
op
address
BITS Pilani, Pilani Campus
Two types of functional elements in the hardware: elements that operate on data (called combinational elements) elements that contain data (called state or sequential elements)
BITS Pilani, Pilani Campus
An overview of Implementation:
For every Instruction
Send Program Counter(PC) to memory that contains code and fetch the instruction from that memory
Read one or two registers, using fields of the instruction to select the registers to read. For the load word instruction, we need to read only one register, but most other instructions require that we need two registers.
After these two steps actions required depend on instruction class.
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
All instruction classes except jump use arithmetic-logic unit (ALU) after reading the registers.
Memory reference instructions use ALU for an address calculation
Arithmetic-logical instruction for operation execution
Branch for comparison.
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
After using ALU, the actions required to complete various instruction classes differ A memory reference instruction will need to access memory either to write data for a store or read data for load An arithmetic/logical instruction write data from the ALU back into the register For branch instruction may need to change the next instruction address based on comparison.
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
Single Cycle Implementation
Add
4
Separate adder as ALU operations and PC increment occur in the same clock cycle
PC
Read address Instruction
Registers Read register 1 Read Read data 1 register 2 Read Write data 2 register Write data RegWrite 16
3 ALUSrc M u x
ALU operation
MemWrite MemtoReg
Zero ALU ALU result
Address
Read data
Instruction memory
Data memory Write data MemRead
M u x
Sign 32 extend
Separate instruction memory as instruction and data read occur in the same clock cycle
Adding instruction fetch
BITS Pilani, Pilani Campus
PCSrc Add 4 Shift left 2 Registers Read register 1 Read Read data 1 register 2 Write register Write data RegWrite 16 Read data 2 3 ALU operation Add ALU result M u x
New multiplexor
Extra adder needed as both adders operate in each cycle
MemWrite MemtoReg Address Read data
PC
Read address Instruction Instruction memory
ALUSrc
M u x
Zero ALU ALU result
Write data Sign extend 32
Data memory
M u x
Instruction address is either PC+4 or branch target address
MemRead
Adding branch capability and another multiplexor
BITS Pilani, Pilani Campus