10 - High Power Circuits

The information in this work has been obtained from sources believed to be reliable. The author does not guarantee the accuracy or completeness of any information presented herein, and shall not be responsible for any errors, omissions or damages as a result of the use of this information.

September 2008

2006 by Fabian Kung Wai Lee

References
[1]* G. Gonzalez, Microwave transistor amplifiers - analysis and design, 2nd Edition 1997, Prentice-Hall. [2] C. W. Sayre, Complete wireless design, 2001, McGraw-Hill. [3]* S. C. Cripps, RF power amplifier for wireless communications, 1999, Artech House (2nd edition 2005 is available). [4] G. D. Vendelin, A. M. Pavio, U. L. Rohde, Microwave circuit design - using linear and nonlinear techniques, 1990, John-Wiley & Sons (2nd edition 2005 is available). [5] S. A. Maas, Nonlinear microwave circuits, 1988, Artech House. [6] G. Massobrio, P. Antognetti, Semiconductor device modeling with SPICE, 2nd edition, 1993, McGraw-Hill. [7]* B. Razavi, RF microelectronics, 1998 Prentice Hall. [8] Gilmore R., Besser L., Practical RF circuit design for modern wireless systems, Vol. 1 & 2, 2003, Artech House. [9] Gray P. R., Meyer R. G., Analysis and design of analog integrated circuits, 3rd Edition, 1993, John-Wiley & Sons.
September 2008 2006 by Fabian Kung Wai Lee 2

1.0 Introduction

September 2008

2006 by Fabian Kung Wai Lee

Introduction
Thus far we have considered various aspects of small-signal amplifier design based on small-signal S-parameters. The small-signal S-parameters are not useful for large-signal or high power circuit design such as power amplifier, mixers, frequency converters because the active devices (i.e. transistor/FET/diode) in these circuits usually operate in the nonlinear regions (recall that Sparameters are obtained by assuming the BJT or FET to be linear). In large-signal circuits the voltage and current variation will be large, for BJT this means the variation of the transistor terminal voltages will be greater than VT. Here we will concentrate on aspects of large-signal circuit design concerning power amplifiers and mixers. This short note will focus on discrete design, using BJT or FET, although the concepts can be extended to integrated circuit design.
May 2009 2006 by Fabian Kung Wai Lee 4

Small-Signal Versus Large-Signal Operation

Consider a 2-port system:
2 3

Usually non-sinusoidal waveform

vo (t ) = a1vi (t ) + a2 vi (t ) + a3vi (t ) + H .O.T .

Large-signal
f

Small-signal
T

Zs

1/T

Sinusoidal waveform

Vs

vi(t)

ZL

vo(t)

September 2008

2006 by Fabian Kung Wai Lee

Large-Signal Model of Active Components (1)

Amplitude of the voltage and current in the transistor/FET of high power circuit is large so that small-signal linear model (such as hybrid pi model) cannot be employed. We must use large-signal model of the transistor, such as Eber-Molls model, the Gummel-Poon model, the VBIC model. For MOSFET, the BSIM model is popular. Design of high power circuits is more of an art. A lot of experience is needed. Usually nonlinear circuit simulator is used (such as SPICE based circuit simulator). Simulation algorithms such as nonlinear transient simulation for time-domain and harmonic-balance (HB) method for frequencydomain are usually employed, see [5] for a primer into the HB method. The active device model is very important, as it affects the accuracy of the simulation result.
September 2008 2006 by Fabian Kung Wai Lee 6

Large-Signal Model of Active Components (2)

Most bipolar junction transistor and field effect transistor manufacturers provide SPICE based model of their device online, these are usually Gummel-Poon model or VBIC model for BJT and BSIM model for FET. These models usually come in the form of a netlist of a sub-circuits, which we can easily incorporate into our schematic using commercial circuit simulators. Here a design example of Class A power amplifier will be shown. This can also be applied to Class AB and Class B. Class C, E, F and others will not be discussed in depth due to lack of time. Please refer to Cripps [3] for more details.

September 2008

2006 by Fabian Kung Wai Lee

Large-Signal Model for Bipolar Junction Transistor (BJT)

The most popular large-signal model for BJT is the SPICE Gummel-Poon (SGP) model (See Ref [6] for further details). A more recent alternative to the SGP model is the Vertical Bipolar Intercompany Model (VBIC) model which offers more accuracies as compared to SGP model. The SPICE Gummel-Poon model is based on the device physics of bipolar junction transistor. A simplified version is shown below.
C
rC VBC rB
I LC

C B
CC
ICC I EC

I EC

B
VBE
I LE

I CC

CE

rE
September 2008

As an example see [Link] and [Link]/docs/iccap2002/ MDLGBOOK/ 7DEVICE_MODELING/3TRANSISTORS/2VBIC for more information on VBIC models.
2006 by Fabian Kung Wai Lee 8

Relationship Between Large and Small-Signal Models

C rC VBC rB B VBE
I CC
I LE I LC

IB5
I EC

CC
I CC I EC

IC
D.C. load line
IB4 IB3 IB2 IB1

CE

rE E

VCE

Large-signal model Small-signal model

September 2008 2006 by Fabian Kung Wai Lee 9

Large-Signal Model for MOS Field Effect Transistor (1)

For MOSFET, the current industry standard is the BSIM (Berkeley Short-channel IGFET Model, IG stands for insulated-gate) model. BSIM is a physics-based threshold model of field-effect transistor. It is accurate, scalable, robust and predictive MOSFET SPICE model for circuit simulation and CMOS technology development. It is developed by the BSIM Research Group in the Department of Electrical Engineering and Computer Sciences (EECS) at the University of California, Berkeley. Optimized for modeling MOSFET in VLSI circuits, deep submicron technology (<0.25m channel length). Various flavors (in the order of increased complexities and accurracy) e.g. BSIM1, BSIM2, BSIM3, BSIM4 and BSIMSOI. Official homepage: [Link] See Massobrio & Antognetti [6] for more information on large signal field effect transistor modeling.
2006 by Fabian Kung Wai Lee

September 2008

10

Large-Signal Model for MOS Field Effect Transistor (2)

SPICE model for NMOS field-effect transistor.
D
RD CDB

D
CGD

G B
CGS iD

DDB

S
B
P+

G
G D
SiO2 N+ P

DSB

B
I CC I EC

S
N+

CSB RS CGB

Silicon substrate (semi-insulating)

September 2008

2006 by Fabian Kung Wai Lee

11

Large-Signal Model for MOS Field Effect Transistor (3)

In recent year there is an alternative to BSIM, based on physics-based surface potential or inversion charge based model. This model is called PSP MOSFET model and is jointly developed by Pennsylvania State University and Philips Semiconductor. PSP probably stands for (Pennsylvania or Philips Surface Potential). The PSP model includes an accurate description of all physical effects important for modern and future CMOS technologies. See [Link] p/ and [Link] for more information.

September 2008

2006 by Fabian Kung Wai Lee

12

2.0 Basic Power Amplifier Design

September 2008

2006 by Fabian Kung Wai Lee

13

Amplifier Classification (1)

According to signal level: Small-Signal Amplifier. Power Amplifier (Large-Signal Amplifier). According to dc biasing scheme: Class A. Class B. Almost all small-signal amplifiers are Class A Class AB. Class C.

September 2008

2006 by Fabian Kung Wai Lee

14

Amplifier Classification (2)

IC D.C. load line Vcc

Vcc = VCE + I C Rc
Class A Class AB Class B IB=0 Class C VCE IC D.C. Load Vcc Line equation
Rc

Rc

IC VCE

or

VCE
Re
15

Vcc = VCE + I C (Rc + Re )

September 2008 2006 by Fabian Kung Wai Lee

Important Parameters for Power Amplifier

Maximum output power. Efficiency (%). Harmonic Distortion or Linearity.
Large-signal power gain (dB) / maximum power rating (W).
Operating voltage (V). Bandwidth (Hz). Isolation.

September 2008

2006 by Fabian Kung Wai Lee

16

Class-A Power Amplifier Schematic Template

Vcc
vb vc

Cd
t

Rb1 L3 L1 Cc1 L2 Rb2 Re Ce Cc2

Input Matching Network

Output Matching Network

RL

Low efficiency (<50%). High linearity. Suitable for wideband system. Suitable for low voltage system.
September 2008 2006 by Fabian Kung Wai Lee

Note that most power amplifiers are of CE or CC configurations.

17

Class-B Power Amplifier Schematic Template (Push-Pull Configuration)

Vcc
v
b

ic

Cd L1

Rb

The active device is only active half the time, or 180o D1 D2 Cc2

Input Matching Network

Cc1

Output Matching Network

RL
-ic

High efficiency (<78%). High linearity. Suitable for wideband system. Need higher operating voltage.
September 2008

L2 Rb

2006 by Fabian Kung Wai Lee

18

Class-C Power Amplifier Schematic Template

Vcc
v
b

Cd
t

The active device is only active less than half the time, or <180o L1 Cc2

Input Matching Network Can also connect to negative supply

Cc1 L2 Rb
ic

Output Matching Network/ Band-pass Filter

RL

High efficiency (<90%). Poor linearity. Suitable for narrowband system. Suitable for low voltage system.
September 2008

f
2006 by Fabian Kung Wai Lee 19

A Short Summary on Other Classes

Class F Amplifier The Class F amplifier is a special variant of Class B. This class of amplifier achieves even higher efficiency than Class B by reactively tune the harmonics to ensure no dissipation at harmonic frequencies and also to minimize power dissipation by keeping the active device voltage as low as possible when the current is high. Class E Amplifier (Switching Amplifier) Class E amplifier is similar to the Class B or F in that the active device is normally driven with a 180o conduction angle between saturation and cut-off. However it uses a switching principle so that any analog relationship between the input and output is lost. Class D Amplifier (Switching Amplifier) Class D amplifier utilizes the switching principle by driving two active devices in tandem, to ensure that when one device is conducting the other device is forced off. It can be regarded as a push-pull Class F amplifier.

September 2008

2006 by Fabian Kung Wai Lee

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10

Amplifier Large-Signal Response 1 Tone Excitation (1)

Consider an amplifier which can be characterized by a power series expansion of its input. If the input voltage is a sinusoidal signal (1 Tone), and considering up to cos( ) = (cos(2 ) + 1) 3rd order: 2 3 (2.1) cos( ) = (3 cos + cos(3 )) vo (t ) = 1vi (t ) + 2 vi (t ) + 3vi (t ) + H .O.T . Typically is negative |Vi(f)| vi (t ) = A cos(t )
2 1 2 3 1 4

|Vi(f)|

vi (t )

vo (t )

f f

= 1 A cos(t ) + 1 2 A2 [1 + cos(2t )] + 1 3 A3 [3 cos(t ) + cos(3t )] 2 4

vo (t ) 1 A cos(t ) + 2 A2 cos 2 (t ) + 3 A3 cos 3 (t )

= 1 2 A2 + 1 + 3 3 A2 A cos(t ) + 1 2 A2 cos(2t ) + 1 3 A3 cos(3t ) (2.2) 2 4 2 4

st Fundamental frequency 1 harmonic term (P1) term (Po) 2006 by Fabian Kung Wai Lee

DC term
September 2008

2nd harmonic term (P2)

21

Amplifier Large-Signal Response - 1 Tone Excitation (2)

Now converting all powers into dB scale, assuming the system impedance is Zo (real) and we are referencing with respect to 1mW. 2 Input power: Pin = 2 1 o A2 Pin _ dBm = 10 log 2A o / 0.001 (2.3a) Z Z Fundamental: Pin/1mW 2 2 A2 Po _ dBm = 10 log (1 + 3 3 A ) 2 Z o / 0.001 4
= Pin _ dBm + 20 log 1 + 3 3 A2 Pin _ dBm + 20 log(1 ) 4
Slope=1 Slope=2 Slope=3

(2.3b)

Similarly we can show that: 1st harmonic:

P _ dBm = 2 Pin _ dBm + 10 log 1

zo 2

2 2 30

2nd harmonic:

(2.3c)

Active component goes into saturation

Pin/dBm

P2 _ dBm = 3Pin _ dBm + 20 log

zo 2

3 60

(2.3d)
September 2008 2006 by Fabian Kung Wai Lee 22

11

Amplifier Large-Signal Response - 2 Tones Excitation (1)

vo (t ) = 1vi (t ) + 2 vi 2 (t ) + 3vi 3 (t ) + H .O.T .
|Vo| |Vi|

Note that we interchage f and freely

IMD f

vi (t )
f1 f2 f

vo (t )
f1-f2 2f1-f2 f1 f2

2f1 f1+f2 2f2-f1 2f2

3f1 2f1+f2

3f2 2f2+f1

vi (t ) = A1 cos(1t ) + A2 cos(2t ) (2.4)

Component of interest in implementing mixer circuit Undesirable components, cause Intermodulation Distortion (IMD).
September 2008

2 sinusoidal signal At f1 and f2

Component of interest in implementing amplifier

1 : 1 A1 + 3 3 A13 + 3 3 A1 A22 cos(1t ) 4 2

3 2 1

(2.5b) 2 1 2 3 3 A2 + 3 3 A2 A cos(2t ) 4 2 1 2 : 2 A1 A2 cos(1 + 2 )t + 2 A1 A2 cos(1 2 )t (2.5c) 3 A A 3 A A 21 2 : 4 cos(21 + 2 )t + 4 cos(21 2 )t (2.5d)

2 3 1 2 2 3 1 2

( : ( A +

(2.5a)

A A 22 1 : 3 3 4 2 A1 cos(22 + 1 )t + 3 3 4 2 A1 cos(22 1 )t (2.5e)

2 2

2006 by Fabian Kung Wai Lee

23

Amplifier Large-Signal Response - 2 Tones Excitation (2)

Let A1 = A2 = A, and 3 << 1. Now converting all powers into dB scale, assuming the system impedance is Zo (real) and we are referencing with respect to 1mW. As in 1 Tone excitation case, we again notice that: Fundamental Component: The output power at f1 and f2 (Po_f1, Po_f2) increases with slope = 1 with respect to Pin in dBm (for Pin sufficiently 2 small). : ( + 9 A2 )A cos( t ) P = 1 ( + 9 A2 ) A2 1 2 A 2
1 1 4 3 1

o _ 1

2 Zo

2 Zo

Mixing Component: The output power at f1-f2 and f1+ f2 increases with slope = 2 with respect to Pin in dBm. 2 1 Po _ = 2 Z ( 2 A2 ) 1 2 : 2 A2 cos(1 2 )t Intermodulation Component: The output power at 2f1f2 and 2f2f1 increases with slope = 3 with respect to Pin in dBm.
1 2 o
3 3 21 2 : 34A cos(21 + 2 )t + 34A cos(21 2 )t 3 3

Po _ 21 2 =

1 2Zo

(A)
3 4 3
24

3 2

September 2008

2006 by Fabian Kung Wai Lee

12

Amplifier Large-Signal Response - 2 Tones Excitation (2)

For amplifier design, Po_f1 , Po_ 2f1-f2 and Po_ 2f2-f1 (or related components) versus Pin are off interest. These can be plotted in dB scale are shown in the next slide. Po_ 2f1-f2 and Po_ 2f2-f1 are typically very close to the fundamental terms, thus are difficult to remove via band-pass filtering, and result in distorted output signals. For mixer design, Po_ f1f2 versus Pin are off interest.

September 2008

2006 by Fabian Kung Wai Lee

25

Dynamic Range, 1dB Gain Compression and Third Order Intercept Point
Plotting P22-1, P1 versus Pin in log scale, a few parameters can be defined:
Pout (dBm) 30 20 10 0 -10 -20 -30 -40 -50 Po,mds -60 -70
September 2008

1dB Gain compression Point PIP P1dB Power gain Gp = Pout(dB) - Pin(dB) Dynamic range (DR)
1

Third-order Intercept Point (TOI) Burn out Note: Spurious free dynamic range is important, for within Saturation this range the 3rd order component power is less than the noise power, 2 2 1 thus distortion due to this component is negligible.

P1
1

P
3

Spurious free dynamic range (DRf)

1

Noise Floor

-60

-50

-40

-30

-20

-10

1dB compression point (Pin_1dB) Pin (dBm) 10 20

26

2006 by Fabian Kung Wai Lee

13

Some Useful Relations for LargeSignal Parameters

Please refer to Chapter 2 of [7] and Chapter 4 of [1] for derivation. All parameters are in dB scale.

PIP P dB + 10dB 1
P21 2 = 3P1 2 PIP
IMD

P1 P21 2 =

2 3

(P

IP

P21 2 (2.2a)

2 PIP = 2 P1 + P1 P21 2
where IMD = P 1 P21 2

Po/dBm
10dB PIP P1dB

PIP = P1 + 1 IMD (2.2b) 2

P1

P21 2
DRf

DR f =

2 3

(P

IP P , mds ) (2.2c) o

Po,mds

Pin/dBm
27

September 2008

2006 by Fabian Kung Wai Lee

Relationship between TOI, DR, DRf and Linearity (1)

Levels of input and output TOI, DR and DRf indicate the linearity of the power amplifier. Highly linear power amplifier has small 2 and 3 compare to 1. Large DR implies small 2/ 1 ratio. Large DRf and TOI levels imply small 2/ 1 and 3/ 1 ratios.* In essence, a linear power amplifier - Has larger DR and DRf. - Has larger TOI levels.
*Here we ignore the effect of higher order terms (H.O.T.) and time delay effect.

vo (t ) = 1vi (t ) + 2vi (t ) + 3vi (t ) + H .O.T .

2 3
Undesirable, suppress these

September 2008

2006 by Fabian Kung Wai Lee

28

14

Relationship between TOI, DR, DRf and Linearity (2)

The 1dB Gain Compression point (P1dB) and the TOI point (PIP) are important as both determine the dynamic range DR and the spuriousfree dynamic range DRf. The DRf is usually taken as the output power range where the largesignal amplifier is considered linear.
Po/dBm

Suppose we have 2 amplifiers, with different 3 values. Typically |3| <<1, so its logarithm is negative. One with larger |3| (blue) and the other with smaller |3| (red).
3 3 A3 4 2 10 log10 P

P21 2 P1
Po,mds
3 in _ dBm + 20 log10 ( 4 Z o 3 ) 60

Smaller DRf (larger |3|) Larger DRf (smaller |3|)

P22 1 =

1 2 Zo

( ) ( ) 3P
0.001

Pin/dBm

September 2008

2006 by Fabian Kung Wai Lee

29

Measuring TOI Level

Equation (2.2b) provides a convenient way to measure the third-order intercept point (IP) output power PIP. Power/dBm A typical setup is shown below:
CW Generator 1 at f1 CW = Continuous sine Wave Output power level for both generators must be similar
2f1-f2 f1 f2 2f2-f1

IMD

Power Combiner CW Generator 2 at f2 Amplifier under test

Note that cable and connector loss has to be accounted for.
P1

Spectrum Analyzer

Po

PIP = P1 + 1 IMD 2
Note that the IMD level will decrease as CW generator output is increased. 30

PIP

P21 2

September 2008

Pin 2006 by Fabian Kung Wai Lee

15

For Class A, AB and B Power Amplifier- Constant P1dB Contour

Typical Power contour for FET at a fixed frequency. The power contour is obtained by varying the load impedance while ensuring conjugate match at the input, then the input power is slowly increased until 1dB gain compression is observed. ZL with similar P1B are then joint together. P1dB Contour

L Plane At fixed frequency !

September 2008

2006 by Fabian Kung Wai Lee

31

For Class A, AB and B Power Amplifier - Large-Signal Reflection Coefficients

Large-signal L

Large-signal s

Typical s and L as a function of frequency for an FET amplifier

September 2008 2006 by Fabian Kung Wai Lee 32

16

Large-Signal Parameters Measurement Setup

A typical setup as shown below is used to obtain the large-signal data on the previous slides.
Power Meter B For measuring Input power RF choke Input tuning Stub A For measuring Output power Power Meter C Directional coupler Output tuning Stub
2006 by Fabian Kung Wai Lee 33

Power For measuring the amount of mismatch Meter A at input Variable Attenuator

Signal Generator

D.C. Supply A

Transistor Amplifier Under Test B B

Load
May 2009

Example 2.1 Class-A Power Amplifier Design

In this example we would like to design a single transistor Class-A power amplifier for a battery operated device at operating frequency fo = 868.0 MHz. The amplifier is driven by a source with 50 source impedance and with available power level of PA= -5.0 dBm or 0.32 mW. The output power into a 50 load is required to be 10.0 mW or 10 dBm. The transistor chosen for the job is BFG520 from Philips Semiconductors. This is an NPN wideband transistor, with fT = 9 GHz, IC(max) = 70 mA and maximum power dissipation of 300 mW. Using a transistor with fT > 5fo allows us to reduce the dc collector current (IC), thereby reducing idle power dissipation. Here we rely on Agilent Technologies ADS 2003C software for the analysis.

September 2008

2006 by Fabian Kung Wai Lee

34

17

Example 2.1 - Class A Power Amplifier Design Cont

The basic amplifier core circuit. DC analysis is performed to find the transistor quiescent point.
3.30 V

DC analysis results: Vcc = 3.3 V Ic = 10.8 mA VCE = 2.14 V Ideal voltage swing = 2.14 V

-11.6 mA V_DC VCC Vdc=3.3 V

11.6 mA R RC R=100 Ohm 2.14 V 2.14 V 2.14 V 0A C CD2 C=22.0 pF 2.14 V 2.14 V 2.14 V 10.7 mA 0A C L CD1 L1 L=100.0 nH C=100.0 pF R= 2.14 V 10.8 mA 2.14 V 2.14 V DC DC1

DC

Pdc = I ccVcc = 11.5mA 3.3V = 38.0mW

38 Theoretical Power Added Efficiency

2.14 V 885 uA R RB1 R=1.5 kOhm

Output Terminal
Port P2 Num=2

Theoretical Efficiency ( ) = 10 100 = 26.3%

811 mV 811 mV 74.9 uA L 811 mV LB 811 uA 811 mV 811 mV 74.9 uA 10.7 mA pb_phl_BFG520_19921215 Q1 -10.8 mA

(PAE) = 10 0.32 100 = 25.5%

38

L=100.0 nH R= R RB2 R=1 kOhm

This is within the limit of ideal efficiency of 50% for Class-A PA

September 2008

Input Terminal

811 mV Port P1 Num=1

A compromise has to be made in terms of voltage swing and IC, owing to the dc biasing circuit chosen.
35

2006 by Fabian Kung Wai Lee

Example 2.1 Class-A Power Amplifier Design Cont

Performing a load pull test to find the optimum load impedance ZL.
HARMONIC BALANCE
HarmonicBalance HB1 Freq[1]=RFf req Order[1]=Max_Harmonic SweepVar="TLmag" Start=0 Stop=Max_Rho Step=0.1

PARAMETER SWEEP
ParamSweep Sweep1 SweepVar="TLphase" SimInstanceName[1]="HB1" SimInstanceName[2]= SimInstanceName[3]= SimInstanceName[4]= SimInstanceName[5]= SimInstanceName[6]= Start=0 Stop=360 Step=5 I_Probe ISupply

Var Eqn

Nonlinear HB analysis is applied. This is a single-tone analysis since there is only one source. Up to 5th harmonic is considered. (Max_Harmonic = 5)

VAR Stimulus_User_Settings Zo=50 User can change the RFf req=868 MHz parameters in the Max_Harmonic=5 Variable Equation "Stimulus_User_Setting" Max_Rho=0.9 Ps_dBm=-5

Source available power = -5dBm into 50 load.

Var Eqn

V_DC Vcc Vdc=3.3 V

VSupply

Amplifier core circuit (see previous slide)

Vin I_Probe ISource C Cc1 C=100.0 pF PA_core X1 C Cc2 C=100.0 pF I_Probe ILoad

VL
Var Eqn

VAR Load_Source_Impedance_at_Harmonics ZL_dc=1000000 This def ines the load and ZL_2=1+j*0 source impedance at the ZL_3=1+j*0 f undamental and harnomics. ZL_4=1+j*0 Here we assume the circuit parasitics will short out the ZL_5=1+j*0 higher harmonics ZL_6=1+j*0 ZL_7=1+j*0 Zs_dc=Zo Zs_1=Zo Zs_2=1+j*0 Zs_3=1+j*0 Zs_4=1+j*0 Zs_5=1+j*0 Zs_6=1+j*0 Zs_7=1+j*0 VAR Load_Ref lection_Coef f icient_Sweep TLmag=0 TLphase=0 r(x)=(x-Zo)/(x+Zo) TLcenter=0 TL=TLcenter+TLmag*exp(j*(TLphase/180)*pi)

Expressions to set the load and source impedance at the harmonics. Expression to sweep L across the Smith Chart in polar form.

one tone source (at 868 MHz) PA = Ps_dBm or -5 dBm in this instance.

P_1Tone PORT1 Num=1 Z=Zs Ohm P=polar(dbmtow(Ps_dBm),0) Freq=RFf req

NOTE: Depending on the v alue of the internal v ariable 'f req', the v ariable TLArray Index will assume the integer v alue 0 if f req = dc, 1 if f req = f undamental, 2 if f req = 1st harmonic etc. This prov ides the index to the one dimensional array TLArray [ ]. Thus ef f ectiv ely the Harmonic Balance solv er will 'see' dif f erent load impedance/ref lection coef f icient at dif f erent f requencies. Similar action is perf ormed f or Source_Impedance Variable Equation.

S1P_Eqn S1P1 S[1,1]=TLoad Z[1]=Zo

Var Eqn

VAR Load_Ref lection_Coef f ient TLArray Index=int(min(abs(f req)/RFf req + 1.5, length(TLArray ))) TLArray =list(r(ZL_dc),TL,r(ZL_2),r(ZL_3),r(ZL_4),r(ZL_5),r(ZL_6),r(ZL_7)) TLoad=TLArray [TLArray Index] VAR Source_Impedance ZsArray Index=int(min(abs(f req)/RFf req + 1.5, length(TLArray ))) ZsArray =list(Zs_dc,Zs_1,Zs_2,Zs_3,Zs_4,Zs_5,Zs_6,Zs_7) Zs=ZsArray [ZsArray Index]

Expressions to generate the correct L and Zs at each frequency component during HB analysis
September 2008

Var Eqn

2006 by Fabian Kung Wai Lee

36

18

Example 2.1 Class-A Power Amplifier Design Cont

Method of sweeping L to cover the Smith Chart.
Im Sweeping the angle of L from 0 to 360o, at 5o interval and the magnitude |L| from 0 to 0.9 at 0.1 step. Of course we could refine this by using smaller steps at the expense of greater computational resources needed.

||

Re

September 2008

2006 by Fabian Kung Wai Lee

37

Example 2.1 Class-A Power Amplifier Design Cont

The expressions on the ADSs Data Display required to generate a contour plot of load power PL at fundamental frequency on the Smith Maximum load Chart.
power (9.151 dBm) at fundamental frequency, with input Compute Load power and Creating Load Power Contour power -5 dBm into VL[::,::,1] extracts the fundamental component of the load voltage, for all (as indicated by the symbol '::') TLmag and TLphase. Same can be said for ILoad.i[::,::,1] 50 load, input not match condition. Eqn PL1_watt = re(0.5*VL[::,::,1]*conj(ILoad.i[::,::,1]))
Eqn PL_step = 0.2 Eqn NumLine = 6 Eqn Distortion_step = 0.05 Eqn N_step = 3 Eqn PL1_dBm = 10*log10(PL1_watt) + 30
0 1 2 3 4 5 0 1 2 3 4 5 0 1 2 3 4 5

Note: Plotting out the variable Mix in the Data Display shows the index to the frequency components
freq TLphase=0.000, TLmag=0.000 0.0000 Hz 868.0MHz 1.736GHz 2.604GHz 3.472GHz 4.340GHz TLphase=0.000, TLmag=0.100 0.0000 Hz 868.0MHz 1.736GHz 2.604GHz 3.472GHz 4.340GHz TLphase=0.000, TLmag=0.200 0.0000 Hz 868.0MHz 1.736GHz 2.604GHz 3.472GHz 4.340GHz Mix

Eqn PL1_dBm_max = max(max(PL1_dBm))

PL1_dBm_max 9.151

Create a contour plot for load power. This actually produces a 3D array. The indexes to the array corresponds to 1) the Power 2) TLmag and 3) TLphase. This can be plotted on X-Y plot where TLmag forms the x-axis, and TLphase forms the y-axis. Eqn contour_PL1_dBm = contour(PL1_dBm, PL1_dBm_max-0.01-[0::NumLine-1]*PL_step) Change the contour plot into polar form. The function indep( ) returns the independent variable associated with the datatype contour_PL1_dBm. There are two independent variables associated with contour_PL_dBm, since we varies the magnitude and phase of TL. The innermost independent variable is TLmag, since it is embedded in the Harmonic Balance simulation control. So this is returned by the indep( ) function. Datatype contour_PL1_dBm itself is simply the phase in degrees. So this can be easily converted in polar form. Eqn contour_PL1_dBm_polar = indep(contour_PL1_dBm)*exp(i*(contour_PL1_dBm/180)*pi)

September 2008

2006 by Fabian Kung Wai Lee

38

19

Example 2.1 Class-A Power Amplifier Design Cont

The expressions on the ADSs Data Display required to generate a contour plot of total load power PL at the harmonics and Efficiency on the Smith Chart. Compute Harmonic Power and Creating the Harmonic Distortion Contour
Eqn PL2_watt=re(0.5*VL[::,::,2]*conj(ILoad.i[::,::,2])) Eqn PL3_watt=re(0.5*VL[::,::,3]*conj(ILoad.i[::,::,3])) Eqn PL4_watt=re(0.5*VL[::,::,4]*conj(ILoad.i[::,::,4])) Eqn PL5_watt=re(0.5*VL[::,::,5]*conj(ILoad.i[::,::,5]))

Maximum Total Harmonic Distortion (ratio of 0.212)

Distortion_max 0.212

Eqn PL_harmonic_watt = PL2_watt + PL3_watt + PL4_watt + PL5_watt Eqn Distortion_Ratio = PL_harmonic_watt/PL1_watt Eqn Distortion_max = max(max(Distortion_Ratio)) Eqn contour_DR=contour(Distortion_Ratio, Distortion_max-0.05-[0::NumLine-1]*Distortion_step) Eqn contour_DR_polar=indep(contour_DR)*exp(i*(contour_DR/180)*pi)

Computing the Efficiency and Creating the Efficiency Contour Eqn Pdc_watt = re(VSupply[::,::,0]*ISupply.i[::,::,0]) Eqn Pin_watt = 0.5*re(Vin[::,::,1]*ISource.i[::,::,1]) Eqn N = ((PL1_watt-Pin_watt)/Pdc_watt)*100 Eqn Nmax = max(max(N)) Eqn contour_N=contour(N,Nmax - 0.1-[0::NumLine-1]*N_step) Eqn contour_N_polar = indep(contour_N)*exp(j*(contour_N/180)*pi)
Nmax 20.259

Maximum Efficiency (20.259 %)

September 2008

2006 by Fabian Kung Wai Lee

39

Example 2.1 Class-A Power Amplifier Design Cont

Superimposing the PL(at 868 MHz), Efficiency and Total Harmonic Distortion Ratio contours on the Smith Chart.
Point of max PL (9.14 dBm), ZLopt
m1 TLmag= 0.357 m1=0.357 / 45.000 level=9.140921, number=1 impedance = Z0 * (1.402 + j0.811) m2 m1 m2 TLmag= 0.440 m2=0.440 / 110.000 level=0.012150, number=2 impedance = Z0 * (0.540 + j0.553)

PL(868 MHz) step = 0.2 dBm Efficiency (N) step = 3% Harmonic Distortion Ratio step = 0.05
contour_N_polar contour_DR_polar contour_PL1_dBm_polar

We observe that ZL needed for highest output power and highest efficiency are similar, thus we choose ZLopt to be given by the PL(868MHz) contour
September 2008

Point of max Efficiency (20.26%)

TLmag (0.073 to 0.687) TLmag (0.375 to 0.900) TLmag (0.053 to 0.900)

2006 by Fabian Kung Wai Lee

From the plot: ZLopt = 70.1+j40.55 at 868 MHz, and close to 0 at harmonics.
40

20

Example 2.1 Class-A Power Amplifier Design Cont

The output transformation network design, approximated to standard L and C values.
AC
AC AC1 Start=0.1 GHz Stop=4.0 GHz Step=5.0 MHz Vin I_Probe I_in V_AC SRC1 Vac=polar(1,0) V Freq=freq C C1A C=4.7 pF L L1 L=8.2 nH R=

Narrowband transformation
VL

Eqn Zin = Vin/I_in.i

160

140

120

100

80

imag(Zin) real(Zin)

C C1B C=0.47 pF

C C2 C=8.2 pF

R RL R=50 Ohm

60

Real part of Zin Imaginary part of Zin

40

20

-20

-40

-60

A low-pass pi network, to suppress the harmonics.

-80

-100

-120 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0

freq, GHz

September 2008

2006 by Fabian Kung Wai Lee

41

Example 2.1 Class-A Power Amplifier Design Cont

After connecting the load network, we measure the large-signal input impedance Zin at the fo of 868 MHz. We then design a low-pass impedance transformation network that transforms 50 Zs into Zin* at fo = 868 MHz.
HARMONIC BALANCE
HarmonicBalance HB1 Freq[1]=RFfreq Order[1]=Max_Harmonic SweepVar= Start= Stop= Step=
Var Eqn

VAR Stimulus_User_Settings Zo=50 RFfreq=868 MHz Max_Harmonic=5 Max_Rho=0.9 Ps_dBm=-5

User can change the parameters in the Variable Equation "Stimulus_User_Setting"

Var Eqn

V_DC Vcc Vdc=3.3 V

I_Probe ISupply

VAR Load_Source_Impedance_at_Harmonics ZL_dc=1000000 This defines the load and ZL_2=1+j*0 source impedance at the ZL_3=1+j*0 fundamental and harnomics. ZL_4=1+j*0 Here we assume the circuit parasitics will short out the ZL_5=1+j*0 higher harmonics ZL_6=1+j*0 ZL_7=1+j*0 Zs_dc=Zo Eqn Zin = Vin/ISource.i Zs_1=Zo Zs_2=1+j*0 Zs_3=1+j*0 Zs_4=1+j*0 freq Zs_5=1+j*0 0.0000 Hz Zs_6=1+j*0 868.0MHz Zs_7=1+j*0
Var Eqn

The results:

VSupply

Vin I_Probe C ISource Cc1 P_1Tone C=100.0 pF PORT1 Num=1 Z=Zs Ohm P=polar(dbmtow(Ps_dBm),0) Freq=RFfreq

VL PA_core X1 C Cc2 C=100.0 pF L L1 L=8.2 nH R= C C1B C=0.47 pF

Var Eqn

VAR Load_Reflection_Coefficient_Sweep TLmag=0 TLphase=0 r(x)=(x-Zo)/(x+Zo) TLcenter=0 TL=TLcenter+TLmag*exp(j*(TLphase/180)*pi)

1.736GHz 2.604GHz 3.472GHz 4.340GHz

Zin <invalid> 10.838 - j12.335 -1.000 + j0.000 -1.000 + j0.000 -1.000 + j0.000 -1.000 + j0.000

C C1A C=4.7 pF

C C2 C=8.2 pF

R RL R=50 Ohm
Var Eqn

VAR Load_Reflection_Coeffient TLArrayIndex=int(min(abs(freq)/RFfreq + 1.5, length(TLArray))) TLArray=list(r(ZL_dc),TL,r(ZL_2),r(ZL_3),r(ZL_4),r(ZL_5),r(ZL_6),r(ZL_7)) TLoad=TLArray[TLArrayIndex] VAR Source_Impedance ZsArrayIndex=int(min(abs(freq)/RFfreq + 1.5, length(TLArray))) ZsArray=list(Zs_dc,Zs_1,Zs_2,Zs_3,Zs_4,Zs_5,Zs_6,Zs_7) Zs=ZsArray[ZsArrayIndex]

Large-signal Zin at fo = 868 MHz

42

Zin
September 2008 2006 by Fabian Kung Wai Lee

21

Example 2.1 Class-A Power Amplifier Design Cont

Finally, upon adding the input and output transformation networks. Note that we are performing conjugate matching at the input.
HARMONIC BALANCE
HarmonicBalance HB1 Freq[1]=RFfreq Order[1]=Max_Harmonic SweepVar= Start= Stop= Step=
Var Eqn

VAR Stimulus_User_Settings Zo=50 RFfreq=868 MHz Max_Harmonic=5 Max_Rho=0.9 Ps_dBm=-5

User can change the parameters in the Variable Equation "Stimulus_User_Setting"

Var Eqn

VAR Load_Source_Impedance_at_Harmonics ZL_dc=1000000 This defines the load and ZL_2=1+j*0 source impedance at the ZL_3=1+j*0 fundamental and harnomics. ZL_4=1+j*0 Here we assume the circuit parasitics will short out the ZL_5=1+j*0 higher harmonics ZL_6=1+j*0 ZL_7=1+j*0 Zs_dc=Zo Zs_1=Zo Zs_2=1+j*0 Zs_3=1+j*0 Zs_4=1+j*0 Zs_5=1+j*0 Zs_6=1+j*0 Zs_7=1+j*0
Var Eqn

Input transformation network

V_DC Vcc Vdc=3.3 V

I_Probe ISupply

ZLopt
VSupply

Zin
C Cc1 C=100.0 pF C C3 C=5.6 pF

Output transformation network

VL L L1 L=8.2 nH R= C C1B C=0.47 pF

VAR Load_Reflection_Coefficient_Sweep TLmag=0 TLphase=0 r(x)=(x-Zo)/(x+Zo) TLcenter=0 TL=TLcenter+TLmag*exp(j*(TLphase/180)*pi) VAR Load_Reflection_Coeffient TLArrayIndex=int(min(abs(freq)/RFfreq + 1.5, length(TLArray))) TLArray=list(r(ZL_dc),TL,r(ZL_2),r(ZL_3),r(ZL_4),r(ZL_5),r(ZL_6),r(ZL_7)) TLoad=TLArray[TLArrayIndex] VAR Source_Impedance ZsArrayIndex=int(min(abs(freq)/RFfreq + 1.5, length(TLArray))) ZsArray=list(Zs_dc,Zs_1,Zs_2,Zs_3,Zs_4,Zs_5,Zs_6,Zs_7) Zs=ZsArray[ZsArrayIndex]

Vin

I_Probe ISource

P_1Tone PORT1 Num=1 Z=Zs Ohm P=polar(dbmtow(Ps_dBm),0) Freq=RFfreq

C C4A C=10.0 pF

L L2 L=4.7 nH R= C C4B C=0.68 pF

PA_core X1

C Cc2 C=100.0 pF

Var Eqn

C C1A C=4.7 pF

C C2 C=8.2 pF

R RL R=50 Ohm
Var Eqn

Zin*

September 2008

2006 by Fabian Kung Wai Lee

43

Example 2.1 Class-A Power Amplifier Design Cont

The results at PA = -5 dBm:

Eqn Zin = Vin/ISource.i

freq 0.0000 Hz 868.0MHz 1.736GHz 2.604GHz 3.472GHz 4.340GHz Zin <invalid> 36.417 + j17.783 -1.000 + j0.000 -1.000 - j7.016E-17 -1.000 + j0.000 -1.000 + j0.000

Eqn VLt = ts(VL)

Eqn Vint = ts(Vin)

Time-domain waveform at input and load resistor

1.5 1.0

Eqn PL = (mag(VL)*mag(VL))/(2*50)
freq 0.0000 Hz 868.0MHz 1.736GHz 2.604GHz 3.472GHz 4.340GHz PL 0.000 0.013 3.031E-6 5.878E-9 1.475E-9 2.244E-10
VLt, V Vint, V

0.5 0.0 -0.5 -1.0 -1.5 0.0 0.5 1.0 1.5 2.0 2.5

time, nsec
September 2008 2006 by Fabian Kung Wai Lee 44

22

Example 2.1 Class-A Power Amplifier Design Cont

Now we sweep the source PA to perform a gain compression test:
HARMONIC BALANCE
HarmonicBalance HB1 Freq[1]=RFfreq Order[1]= Max_Harmonic SweepVar="Ps_dBm" Start=-20 Stop= 5 Step= 1
Var Eqn

VAR Stimulus_User_Settings Zo= 50 RFfreq= 868 MHz Max_Harmonic=5 Max_Rho=0.9 Ps_dBm=-5

User can change the parameters in the Variable Equation "Stimulus_User_Setting"

Var Eqn

VAR Load_Source_Impedance_at_Harmonics ZL_dc= 1000000 This defines the load and ZL_2= 1+j*0 source impedance at the ZL_3= 1+j*0 fundamental and harnomics. ZL_4= 1+j*0 Here we assume the circuit parasitics will short out the ZL_5= 1+j*0 higher harmonics ZL_6= 1+j*0 ZL_7= 1+j*0 Zs_dc= Zo Zs_1= Zo Zs_2= 1+j*0 Zs_3= 1+j*0 Zs_4= 1+j*0 Zs_5= 1+j*0 Zs_6= 1+j*0 Zs_7= 1+j*0
Var Eqn

We sweep the variable Ps_dBm

Vin I_Probe ISource L L2 L=4.7 nH R= C C4B C=0.68 pF

V_DC Vcc Vdc= 3.3 V

I_Probe ISupply

VSupply

VL C C4A C= 10.0 pF C Cc1 C=100.0 pF C C3 C=5.6 pF PA_core X1 C Cc2 C= 100.0 pF L L1 L= 8.2 nH R= C C1B C=0.47 pF
Var Eqn

VAR Load_Reflection_Coefficient_Sweep TLmag= 0 TLphase=0 r(x)= (x-Zo)/(x+ Zo) TLcenter= 0 TL= TLcenter+ TLmag*exp(j*(TLphase/180)*pi) VAR Load_Reflection_Coeffient TLArrayIndex=int(min(abs(freq)/RFfreq + 1.5, length(TLArray))) TLArray=list(r(ZL_dc),TL,r(ZL_2),r(ZL_3),r(ZL_4),r(ZL_5),r(ZL_6),r(ZL_7)) TLoad=TLArray[TLArrayIndex] VAR Source_Impedance ZsArrayIndex=int(min(abs(freq)/RFfreq + 1.5, length(TLArray))) ZsArray=list(Zs_dc,Zs_1,Zs_2,Zs_3,Zs_4,Zs_5,Zs_6,Zs_7) Zs= ZsArray[ZsArrayIndex]

P_1Tone PORT1 Num= 1 Z= Zs Ohm P= polar(dbmtow(Ps_dBm),0) Freq= RFfreq

C C1A C= 4.7 pF

C C2 C= 8.2 pF

R RL R=50 Ohm
Var Eqn

September 2008

2006 by Fabian Kung Wai Lee

45

Example 2.1 Class-A Power Amplifier Design Cont

1dB Gain Compression test result.
15

m1
10

Slope of 1

Thus, P1dB 10.74 dBm meeting our specs.

PL_dBm

m1 Ps_dBm=-6.000 m1=10.738

-5 -20 -15 -10 -5 0 5

Ps_dBm

September 2008

2006 by Fabian Kung Wai Lee

46

23

Example 2.1 Class-A Power Amplifier Design Cont

Snapshot of the completed hardware.

September 2008

2006 by Fabian Kung Wai Lee

47

Example 2.1 Class-A Power Amplifier Design Cont

Measurement at 868 MHz.

Freq. = 868 MHz +10.5 dBm

1st harmonic -11.0 dBm

Output of the amplifier when driven with a frequency synthesizer with Pin = -3.0 dBm into 50 load, fin = 868.0 MHz. Averaging = 10
September 2008 2006 by Fabian Kung Wai Lee 48

24

Example 2.1 Class-A Power Amplifier Design Cont

P1dB gain compression measurement.

1 dB Gain Compression point

+16 dB +15 dB

September 2008

2006 by Fabian Kung Wai Lee

49

Typical Parameters for Medium Power Amplifiers

Operating frequency range: 0.1-10GHz. Output power at 1dB gain compression: +15Bm (31.6mW) to +30dBm (1000mW). Power gain at 1dB gain compression: 12 - 20 dB. Furthermore VCE and IC will be specified for BJT and VDS and ID will be specified for FET. For MMIC, the supply voltage and current will be specified. Noise Figure: 3.0dB or greater. TOI input level: +10 to +15 dBm. TOI output level: +20 to +40 dBm. For MMIC, most of the time the source and load impedance is internally matched to 50.

September 2008

2006 by Fabian Kung Wai Lee

50

25

3.0 Basic Mixer Design

September 2008

2006 by Fabian Kung Wai Lee

51

Mixers
A mixer uses the nonlinearity of a diode, transistor or FET under largesignal operation to generate an output spectrum consisting of the sum and difference frequencies of two input signals. A mixer used for RF receiver usually consists of three ports, the RF, LO (Local Oscillator) and IF (Intermediate Frequency) ports. There are several types of mixers, the simplest being the Single-Ended Mixer. The single ended mixers are often used as components for more sophisticated mixers. The Balanced Mixer combines two or more identical single-ended mixer to give better input SWR or matching and higher isolation between the RF/LO ports.
RF Symbol and terminals of a mixer
September 2008 2006 by Fabian Kung Wai Lee

LO

IF
52

26

Block Diagram of Single-Ended Mixer

RF PRF RF
Input Matching Network Power supply Biasing

LO

IF
f IF = f RF f LO or

Power Combiner

Nonlinear Element

f IF = f LO f RF IF Low-pass
Filter And Output Matching Network

PIF

LO PLO

Input Matching Network

Conversion Gain:

GC =

Available PIF PRF

September 2008

2006 by Fabian Kung Wai Lee

53

Example of Single-Ended Diode Mixer

Lumped version of Wilkinson Power Divider/ Combiner (narrow band) Vcc
Cd

RFin1

Rbias

Low-pass filter

RFC
Cc1 L2

L1 Cc2

RFC

RL

RFin2

Input matching network

September 2008

2006 by Fabian Kung Wai Lee

54

27

Simplified Analysis of the Diode Mixer

CC Under DC condition the diode voltage and current are VD and ID. Cd Imagine the RF chokes (RFC) DC: present a high impedance to the VD RFC L1 I D = I s e nVT 1 AC voltage and current. V D + vd ID High The input AC voltage vd will impedance High modulate the diode junction impedance id ID + id voltage, which results in variation L2 of the diode current id. DC with RF RFC v = A cos( t ) v = A cos( t ) and LO: The current flowing across the vd = v1 + v2 RFC is assumed constant, thus the I D + id I s e 1 change in current id is forced 2 v v id = I s e e 1 I s e (nV ) + 1 (nV ) + L 2 through the output of the mixer. Causes mixing effect Due to the nonlinear nature of the Affects conversion 2 + + PN junction, id contains the sum gain id I s e (vnVv ) + 1 (vnVv ) + L 2 and difference components. 2006 by Fabian Kung Wai Lee December 2010 55
1 1 1 2 2 2

VD +vd nVT

VD nVT

vd nVT

VD nVT

VD nVT

Mixer Types (1)

Following the definition by [4], mixer can be classified depending on the signaling type on the RF terminals. By signaling type we imply whether the RF input signal is single-ended or differential (double-ended). Sometimes two or more mixers can be combined to form a Balanced architecture.
Differential RF input RF RF LO IF LO IF
+ -

Single-Ended Mixer

Note: The LO input can be single-ended or differential.

Double-Ended Mixer
May 2009 2006 by Fabian Kung Wai Lee 56

28

Mixer Types (2)

RF

Balanced type mixers.

+ Power Splitter Power Splitter with balun

RF

LO

Power Combiner Power Splitter

IF
Power Combiner with balun

IF

LO

Power Splitter

Single-Ended Balanced Mixer (Single-balanced)

Double-Ended Balanced Mixer (Double-balanced)

2006 by Fabian Kung Wai Lee 57

May 2009

Conversion Gain and Leakage (1)

If a diode is used for the nonlinear element, there is no gain, i.e. the conversion gain GC (dB) is negative. Sometimes this negative value is called conversion loss instead. If BJT or FET is used as the nonlinear element, there is usually a positive conversion gain GC (dB). A major issue with single-ended mixer is the leakage between the two RF inputs. This is due to the fact that the power combiner used is usually narrowband, and the frequency difference between RF and LO input is usually substantial.
Power Leakage

RF
Power Leakage Power Leakage

RF
Power Leakage Electrical energy into LO terminal leaks out at RF and IF terminals.

LO

IF

LO

IF

Electrical energy into RF terminal leaks out at LO and IF terminals.

58

May 2009

2006 by Fabian Kung Wai Lee

29

Conversion Gain and Leakage (2)

The simplicity and performance of single-ended mixer make it very attractive in terms of cost, productivity and conversion loss. However this type of mixer usually exhibits higher leakage (e.g. lower isolation between ports), spurious products and low operating bandwidth. Leakage due to LO can be reduced by using differential RF input and differential IF output. Balanced mixers have better isolation between ports (lower leakage), lower spurious products. But this comes in terms of higher complexity, and usually larger conversion loss. A single-ended signal can be converted into differential signal and vice versa by using a Balun (balanced-unbalanced converter). Examples of balun are center-tapped transformer, and various type of directional couplers (see notes on RF Passive Circuits Design).

May 2009

2006 by Fabian Kung Wai Lee

59

Example 3.1 430 MHz Single-Ended Discrete BJT Mixer Design

DC
DC DC1

HARMONIC BALANCE
HarmonicBalance HB1 MaxOrder=7 Freq[1]=freq_LO Freq[2]=freq_RF Order[1]=7 Order[2]=5 NLNoiseMode=yes FreqForNoise=freq_RF-freq_LO NoiseInputPort=1 NoiseOutputPort=2 Other=OutVar="RF_pow"

Var Eqn

VAR VAR1 freq_LO=410 Mhz freq_RF=430 Mhz RF_pow=-20

V_DC SRC1 Vdc=3.0 V

R R2 R=1000 Ohm

C Cdec C=1000.0 pF

NOTE: By convention for a successful analysis of mixer: 1. Set the RF input to PORT 1, IF output to PORT 2 and LO input to PORT 3 (by editing the NUM property). 2. Set the signal with largest amplitude to Freq[1] to ensure convergence of the HB method.

RF = 430 MHz LO = 410 MHz IF = 20 MHz IF

OPTIONS
Options Options1 Temp=23.85 TopologyCheck=yes V_RelTol=1e-6 I_RelT ol=1e-6 GiveAllWarnings=yes MaxWarnings=10 I_Probe ILoad C Cm3 C=270.5 pF

R C Rb Cbyp1 R=47 kOhm C=1000.0 pF L Lb L=220.0 nH R=

C Cc3 C=330.0 pF

L Lm3 L=800.0 nH C Cm2 R= C=97.0 pF

Term Term3 Num=2 Z=50 Ohm

I_Probe ISource

P_1Tone Prf Num=1 Z=50 Ohm P=polar(dbmtow(RF_pow),0) Freq=freq_RF

L Lm1 L=68.0 nH R=

C Cm1 C=0.33 pF

C Cc1 C=330.0 pF

pb_phl_BFR92A_19921214 Q1 Output matching network R Re R=330 Ohm C Cc2 C=15.0 pF P_1Tone PLO Num=3 Z=50 Ohm P=polar(dbmtow(0),0) Freq=freq_LO

RF

LO

Input matching network

Adding a series LC network (from E to Gnd) tuned to IF frequency will boost the conversion gain, at the expense of larger LO leakage through RF input.
September 2008

For more information, please refer to the document entitled: Designing A Single-Ended UHF BJT Mixer Using the ADS Software Sep 2001 by [Link]. [Link]
60

2006 by Fabian Kung Wai Lee

30

Example 3.1 Cont...

RF source: frequency = 430.0MHz, Power = -20dBm into 50 load. LO source: frequency 410 MHz , Power = -5.48dBm into 50 load. Power supply for mixer: 3.0V.
Local Oscillator Input 1.57mm thick FR4 printed circuit board SMA to PCB adapter

IF Output

RF Input

BNC to PCB adapter

60ns

To 2.7-3.3V D.C. Source

Measurement at IF output, around 17MHz

September 2008 2006 by Fabian Kung Wai Lee 61

Simplified Analysis of the BJT Mixer

Let VBE be the DC bias, vRF and vLO are the A similar analysis as in the AC RF and LO voltages: diode mixer can be applied to the single-ended BJT mixer. High impedance ICQ Since there is current High ic impedance amplication (), there is the ICQ+ic vRF possibility of conversion gain VBE+vRF-vLO vLO greater than unity. At DC: VBE The variation in the BE I C = I EO e nVT 1 voltage can be injected by the DC with RF approach shown on the I C + ic I EO e 1 and LO: diagram or using a power 2 + + I C + ic I EO e 1 + (v nVv ) + 1 (v nVv ) + L 1 combiner. 2
VBE +vLO +vRF nVT
VBE nVT

December 2010

Transistors VBE and VBE affects the ic I EOe nVT conversion gain 2006 by Fabian Kung Wai Lee

T Considering only the AC term (ic):

RF

LO

RF

LO

[(

vRF +vLO nV T

)+ (

2 1 vRF +vLO 2 nVT

) +L]
62

Causes mixing effect

31

Example 3.2 868 MHz Single-Ended Discrete BJT Mixer Design

Power Supply
Port VCC Num=4 R RD1 R=100 Ohm C CD0 C=2.2 uF R RD2 R=4.7 kOhm Diode DD2 Model=LSR976 C CD1 C=100.0 pF R RC R=470 Ohm

RF = 868 MHz LO = 818 MHz IF = 50 MHz

Diode DD1 Model=BZX284-C3V3 R RB2 R=1.8 kOhm

R RB1 R=470 Ohm R RB3 R=100 Ohm

C L CB1 LC C=470.0 pF L=100.0 nH R=

IF Output
C Port IF_out Num=2

LO Input
Port LO_in Num=3 C Cc1 C=3.3 pF

C CB2 C=100.0 pF

L LB L=100.0 nH R=

pb_phl_BFR92A_19921214Cc2 C=470.0 pF Q1

RF Input
Port RF_in Num=1 C C1A C=1.5 pF C C2 L C=22.0 pF L1 L=33.0 nH R=

C C3 C=4.7 pF

L L2 L=10.0 nH R=

C C5 C=100.0 pF

C C4 C=1.5 pF

C C1B C=1.5 pF

Power combiner
2006 by Fabian Kung Wai Lee 63

September 2008

Example 3.2 Cont

Snapshot of the Mixer prototype.

September 2008

2006 by Fabian Kung Wai Lee

64

32

Example 3.2 Cont

Measurement setup.
50.0 MHz, -22 dBm

A RF signal generator, IFR2023B supplies the RF signal to the mixer RF input, at 868.0 MHz and -20.0 dBm power level (into 50 load). The frequency synthesizer built for this project drives the LO input, at 818.0 MHz and -2.4 dBm power level (into 50 load).

September 2008

2006 by Fabian Kung Wai Lee

65

Example 3.2 Cont

LO leakage at the RF terminal output.

818.0 MHz, -12 dBm

September 2008

2006 by Fabian Kung Wai Lee

66

33

Block Diagram of Single-Balanced Mixer (1)

RF and LO power is divided equally to the two identical single-ended mixer. Hence the term balanced
Cd

Vcc

The RF and LO inputs are split into 2 equal halves and imposed on the 2 diodes. This type of configuration is better known as Single-Balanced Mixer.
Rbias L1

RF
3dB Hybrid (90o or 180o) Input
matching network Input matching network Cc1 L2 Cc3

Cc2

Low-pass filter

Cc4 Low-pass filter L3

Power Combi -ner RL

LO
September 2008 2006 by Fabian Kung Wai Lee 67

Block Diagram of Single-Balanced Mixer (2)

3dB hybrid directional coupler or junction (either 90o or 180o) are used to combine two identical single-ended mixers. 90o hybrid junction gives better wideband input SWR at the RF and LO inputs (this principle is also used in balanced amplifier). 180o hybrid junction gives better RF/LO isolation. This balanced mixer can also suppress even harmonics of LO input. Both types can also give cancellation of AM noise from the local oscillator. For details of mathematical analysis see chapter 10 of Pozar [8].

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More on Mixer Types

Double-Balanced Mixer - suppresses even harmonics of both LO and RF inputs. Give good conversion gain. Also has good RF/LO isolation. Can be implemented using diode ring or using differential amplifier on integrated circuit. Image Rejection Mixer. In integrated circuit, a double-balanced mixer can be implemented using the Gilbert Cell, which is a modification of the two-quadrant analog multiplier. The two-quadrant analog multiplier is essentially an emitter (or source coupled) differential amplifier. See Gray & Meyer [7]. Most commercial integrated circuit mixer uses this method.

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Example 3.3 - Double-Ended Balanced Mixer in Integrated Circuit

This type of mixer is called the Gilbert Cell/Mixer.
R
Ic1

Vcc
Ic2

Differential input: Hence the term double-ended. v1 + + v2 -

R + Vout = R(Ic1 - Ic2) -

IEE
September 2008 2006 by Fabian Kung Wai Lee

Popular General purpose Gilbert cell mixer ICs: MC1496 100 MHz SA602AD 200 MHz SA612AD 500 MHz AD8342 500 MHz

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Example 3.4 - Discrete Double-Ended Balanced Mixer Using Diode Ring Another
Implemented on the PCB itself

varactor-tuned BPF
C C5017-18

Implemented on the PCB itself

L L5004a

L L5005a C JUNCAP C5030 D5005 Model=JUNCAPM1 C CL5005 L L5005b C C5032 C=8.2 pF MLIN T L1 Subst="MSub1" W=25.0 mil L L=100.0 mil L5009 L=1.0 nH R=

C C5029

Port PRFE2 Num=1

C C5055 L L5004b

JUNCAP D5004 Model=JUNCAPM1

RF power flow
R R5012 R=100 kOhm C C5024 C=1.0 nF

C C5031 C=1.0 pF

C C5019-23 C=77.0 pF

Diode ring Balun

Diode DIODE2 Model=DIODEM1 Diode DIODE3 Model=DIODEM1 Diode DIODE1 Model=DIODEM1 XFERP T505b1 XFERP T5051a

Port FECTRL Num=2

R R5060 R=330 kOhm

Port RXINJ Num=4

L L5053 L=15.0 nH R=

L L5054 C L=15.0 nH C5054 R= C=16.0 pF

C C5053 C=6.8 pF

XFERT AP T5052

Diode DIODE4 Model=DIODEM1 R R5052 R=0 Ohm

Port T P5003 Num=5

Bottom Side
L L5008 L=470.0 nH R=

MSub
MSUB MSub1 Er=4.5 Cond=5.8E+7 T=1.38 mil

Juncap_Model JUNCAPM1

Diode_Model DIODEM1

L L5051 L=150.0 nH R=

C C5052 C=82.0 pF

R R5051 R=51 Ohm

IF power flow
Port PIF Num=3

September 2008

2006 by Fabian Kung Wai Lee

IF trap, tuned to 44.85MHz , shunts IF leakage to ground71

Typical Performance Parameters for Commercial Mixers

Parameters for an integrated circuit mixer in the 1-3GHz range (for RF power = -20dBm, LO power = -5dBm, Zo=50Ohm, VCC = 5.0V). Power supply: single polarity, 4.0-8.0V. Typical LO power requirement: -5dBm. Conversion gain GC: 6.5 - 10dB. Single Sideband (SSB) noise figure: 17dB. LO leakage at IF port: -25dBm. LO leakage at RF port: -30dBm. VSWR: RF - 1.5, LO - 2.0, IF - 1.5.

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