Module-I
Introduction and Micro operation
Module-I Course Outcome :
CO-1: Identify various functional aspects of computer hardware.
Module-I Syllabus Content
➢Computer functional units
➢Von – Neumann Architecture
➢Harvard architecture.
➢Register transfer
➢Bus and memory transfer
➢Arithmetic micro operations
➢Logic micro operations [Link]
➢Shift micro operations
➢Arithmetic logic and shiftunit Professor
➢Data Representation
➢Fixed point and Floating point Deparment of CSE(AI&ML)
Vardhaman College of Engineering
Text Books:
1. M. Moris Mano., Computer System Architecture,3rd Edition,
Pearson Publication, India,2006.
2. Stallings William., Computer Organization and Architecture,9th
Edition, Pearson Education,India, 2012.
Computer Functional Units
A computer consists of five functionally independent main parts they are:
➢Input Unit
➢Memory Unit
➢Arithmetic logic unit (ALU),
➢Output Unit
➢Control unit
Input Unit :
➢Input device accepts the coded information as source program i.e. high level language.
➢This is either stored in the memory or immediately used by the processor to perform
the desired operations.
➢The program stored in the memory determines the processing steps.
➢Basically the computer converts one source program to an object program. i.e. into
machine language.
Primary memory: -
➢ Is the one exclusively associated with the processor and operates at the electronics speeds programs
must be stored in this memory while they are being executed.
➢ The memory contains a large number of semiconductors storage cells.
➢ Each capable of storing one bit of information.
➢ These are processed in a group of fixed site called word. To provide easy access to a word in memory,
a distinct address is associated with each word location.
➢ Addresses are numbers that identify memory location. Number of bits in each word is called word
length of the computer.
➢ Programs must reside in the memory during execution. Instructions and data can be written into the
memory or read out under the control of processor. Memory in which any location can be reached in a
short and fixed amount of time after specifying its address is called random access memory (RAM).
Arithmetic logic unit (ALU):-
➢Most of the computer operators are executed in ALU of the processor like addition,
subtraction, division, multiplication, etc. the operands are brought into the ALU from
memory and stored in high speed storage elements called register.
➢Then according to the instructions the operation is performed in the required
sequence.
➢The control and the ALU are may times faster than other devices connected to a
computer system.
➢This enables a single processor to control a number of external devices such as key
boards, displays, magnetic and optical disks, sensors and other mechanical controllers.
Output unit:-
➢These actually are the counterparts of input unit.
➢Its basic function is to send the processed results to the outside world.
➢Examples:- Printer, speakers, monitor etc.
Control unit:-
➢It effectively is the nerve center that sends signals to other units and senses their
states.
➢The actual timing signals that govern the transfer of data between input unit,
processor, memory and output unit are generated by the control unit.
Von – Neumann Architecture
This model was proposed by John von Neumann in 1945 and is the foundation for most
modern computer.
The Von Neumann architecture is a computer architecture model that describes a
system where:
➢Instructions and data share the same memory.
➢Instructions are executed sequentially, unless explicitly altered by control
instructions.
Key Components
Here’s a breakdown of the major components of Von Neumann architecture:
1. Memory Unit
➢ Stores both data and program instructions.
➢ Organized as a linear address space.
➢ Accessible via memory addresses.
➢ Usually RAM in modern systems.
2. Control Unit (CU)
➢ Fetches instructions from memory.
➢ Decodes the instructions.
➢ Directs the operation of the other units using control signals.
➢ Executes instructions in a sequential order, unless a jump/branch is encountered.
3. Arithmetic Logic Unit (ALU)
• Performs arithmetic operations (e.g., addition, subtraction) and logical operations (e.g., AND, OR, NOT).
• Receives data from memory or registers.
• Outputs the result back to memory or a register.
4. Registers
• Small, fast storage locations inside the CPU.
• Used to store intermediate data, instruction addresses, and status flags.
• Common registers include:
• Program Counter (PC) – Holds address of next instruction.
• Instruction Register (IR) – Holds the current instruction.
• Accumulator (ACC) – Holds intermediate arithmetic and logic results.
5. Input/Output (I/O) System
➢Used to interact with the external world.
➢Devices like keyboard, mouse (input), and monitor, printer (output).
6. System Bus
➢A set of parallel lines used for data transfer between components.
➢Three main types:
➢ Data Bus – Carries data.
➢ Address Bus – Carries address of memory location.
➢ Control Bus – Carries control signals.
Von Neumann Cycle (Instruction Cycle)
➢Fetch – The control unit gets the instruction from memory using the PC.
➢Decode – The instruction is decoded to determine the operation.
➢Execute – The ALU or other components perform the operation.
➢Store – Result is written back to memory or register.
Harvard Architecture
The Harvard Architecture is a computer architecture with separate
memory spaces and buses for:
➢Instructions (program code)
➢Data
➢This contrasts with the Von Neumann Architecture, where instructions
and data share the same memory and bus.
Buses
Buses are used as signal pathways.
Harvard architecture, there are separate buses for both instruction and data.
Types of Buses:
➢Data Bus: It carries data among the main memory system, processor, and I/O devices.
➢Data Address Bus: It carries the address of data from the processor to the main memory
system.
➢Instruction Bus: It carries instructions among the main memory system, processor, and
I/O devices.
➢Instruction Address Bus: It carries the address of instructions from the processor to the
main memory system.
➢Operational Registers
There are different types of registers involved in it which are used for storing addresses of
different types of instructions.
For example,
➢Memory Address Register and
➢Memory Data Register are operational registers.
➢Program Counter: It has the location of the next instruction to be executed. The program
counter then passes this next address to the memory address register.
➢Arithmetic and Logic Unit: The arithmetic logic unit is part of the CPU that operates all the
calculations needed. It performs addition, subtraction, comparison, logical Operations, bit
Shifting Operations, and various arithmetic operations.
Control Unit:
➢The Control Unit is the part of the CPU that operates all processor control signals.
➢It controls the input and output devices and also controls the movement of
instructions and data within the system.
Input/Output System:
➢ Input devices are used to read data into main memory with the help of CPU input
instruction.
➢ The information from a computer as output is given through Output devices. The
computer gives the results of computation with the help of output devices.
Features of Harvard Architecture
➢Separate memory spaces: Harvard architecture uses distinct memory spaces for
instructions and data, enabling simultaneous access for faster processing.
➢Fixed instruction length: In Harvard architecture, instructions are of fixed length,
which simplifies the instruction fetch process and allows for faster instruction
processing.
➢Parallel instruction and data access: The separation of instruction and data
memories allows parallel access, improving overall efficiency.
➢More efficient memory usage: Harvard architecture allows for more efficient use
of memory as the data and instruction memories can be optimized independently,
which can lead to better performance.
➢Suitable for embedded systems: Harvard architecture is commonly used
in embedded systems because it provides fast and efficient access to both
instructions and data, which is critical in real-time applications.
➢Limited flexibility: The separate memory spaces restrict tasks like modifying
instructions at runtime, reducing flexibility.
Comparison of Von Neumann and Harvard Architectures
Register Transfer
➢Information transfer from one register to another is designated in symbolic form by means
of a replacement operator.
➢The statement R2← R1 denotes a transfer of the content of register R1 into register R2.
➢It designates a replacement of the content of R2 by the content of R1.
➢By definition, the content of the source register R 1 does not change after the transfer.
➢ If we want the transfer to occur only under a predetermined control condition then it can
be shown by an if-then statement.
➢ if (P=1) then R2← R1
➢P is the control signal generated by a control section.
➢We can separate the control variables from the register transfer operation by
specifying a Control Function.
➢ Control function is a Boolean variable that is equal to 0 or 1.
➢Control function is included in the statement as P: R2← R1
➢Control condition is terminated by a colon implies transfer operation be executed by
the hardware only if P=1.
➢Every statement written in a register transfer notation implies a hardware
construction for implementing the transfer
The Following figure shows the block diagram that depicts the transfer from R1 to R2.
➢The n outputs of register R1 are connected to the n inputs of register R2.
➢The letter n will be used to indicate any number of bits for the register.
➢It will be replaced by an actual number when the length of the register is known.
➢Register R2 has a load input that is activated by the control variable P.
➢It is assumed that the control variable is synchronized with the same clock as the
one applied to the register.
➢As shown in the timing diagram, P is activated in the control section by the rising
edge of a clock pulse at time t.
➢The next positive transition of the clock at time t + 1 finds the load input active and
the data inputs of R2 are then loaded into the register in parallel.
The basic symbols of the register transfer notation are listed in below table
Bus and Memory Transfers
➢Bus and memory transfer are fundamental concepts in computer architecture,
particularly related to how data moves within a computer system(registers).
➢A more efficient scheme for transferring information between registers in a
multiple-register configuration is a Common Bus System.
Different ways of constructing a Common Bus System
➢Using Multiplexers
➢Using Tri-state Buffers
Multiplexer
➢A multiplexer (often abbreviated as MUX) is a digital device that selects one
input from multiple input signals and forwards it to a single output line.
➢It acts like a switch that allows only one data line to pass through at a time, based
on control signals.
Key Points:
➢ Function: Selects one input from several inputs.
➢ Output: Only one line is active at a time.
➢ Control signals (selectors): Decide which input to pass to the output.
Common bus system is with multiplexers
➢ The multiplexers select the source register whose binary information is then placed on the bus.
➢ The construction of a bus system for four registers is shown in below Figure.
➢The bus consists of four 4 x 1 multiplexers each having four data inputs, 0 through 3, and
two selection inputs, S1 and S0.
➢For example, output 1 of register A is connected to input 0 of MUX 1 because this input is
labelled A1.
➢The diagram shows that the bits in the same significant position in each register are
connected to the data inputs of one multiplexer to form one line of the bus.
➢Thus MUX 0 multiplexes the four 0 bits of the registers, MUX 1 multiplexes the four 1 bits of
the registers, and similarly for the other two bits.
➢The two selection lines Si and So are connected to the selection inputs of all four multiplexers.
➢The selection lines choose the four bits of one register and transfer them into the four-line
common bus.
➢When S1S0 = 00, the 0 data inputs of all four multiplexers are selected and applied
to the outputs that form the bus.
➢This causes the bus lines to receive the content of register A since the outputs of this
register are connected to the 0 data inputs of the multiplexers.
➢Similarly, register B is selected if S1S0 = 01, and so on.
➢The following Table shows the register that is selected by the bus for each of the four
possible binary value of the selection lines.
Common bus system is with Three-State Bus Buffers
➢A bus system can be constructed with three-state gates instead of multiplexers.
➢A three-state gate is a digital circuit that exhibits three states.
➢Two of the states are signals equivalent to logic 1 and 0 as in a conventional gate.
➢The third state is a high-impedance state.
➢The high-impedance state behaves like an open circuit, which means that the output
is disconnected and does not have logic significance.
➢Because of this feature, a large number of three-state gate outputs can be connected
with wires to form a common bus line without compromising loading effects.
The graphic symbol of a three-state buffer gate is shown in the following Figure
➢The outputs of four buffers are connected together to form a single bus line.
➢The control inputs to the buffers determine which of the four normal inputs will
communicate with the bus line.
➢No more than one buffer may be in the active state at any given time. The
connected buffers must be controlled so that only one three-state buffer has access
to the bus line while all other buffers are maintained in a high impedance state.
Memory Transfer
➢The transfer of information from a memory word to the outside environment is called
a read operation.
➢The transfer of new information to be stored into the memory is called a write
operation.
A memory word will be symbolized by the letter M.
➢The particular memory word among the many available is selected by the memory
address during the transfer.
➢It is necessary to specify the address of M when writing memory transfer operations.
➢This will be done by enclosing the address in square brackets following the letter M.
➢The data are transferred to another register, called the data register, symbolized by DR.
➢The read operation can be stated as follows:
➢ Read: DR<- M [AR]
➢This causes a transfer of information into DR from the memory word M selected by the
address in AR.
➢The write operation transfers the content of a data register to a memory word M selected by
the address. Assume that the input data are in register R1 and the address is in AR.
➢The write operation can be stated as follows:
➢Write: M [AR] <- R1
Microoperations
➢ Microoperations are the basic, low-level operations that are performed on the data stored in
registers during the execution of an instruction in a computer.
➢ They represent the elementary operations that a processor performs on data, such as transferring
data between registers, performing arithmetic operations, or modifying the contents of memory.
Types of Microoperations:
➢ Register Transfer Microoperations – Moving data between registers
➢ Example: R1 ← R2 (copy data from R2 to R1)
➢ Arithmetic Microoperations – Performing arithmetic on binary data
➢ Example: R1 ← R1 + R2
➢ Logic Microoperations – Performing logical operations (AND, OR, NOT)
➢ Example: R1 ← R1 AND R2
➢ Shift Microoperations – Shifting data in a register left or right
➢ Example: R1 ← R1 >> 1 (right shift)
Arithmetic Micro-operations
The basic arithmetic micro-operations are
• Addition
• Subtraction
• Increment
• Decrement
• Shift
The arithmetic Micro-operation defined by the statement below specifies the add micro-operation.
R3 ← R1 + R2
• It states that the contents of R1 are added to contents of R2 and sum is transferred to R3.
• To implement this statement hardware requires 3 registers and digital component that performs addition
• Subtraction is most often implemented through complementation and addition.
• The subtract operation is specified by the following statement
R3 ← R1 + R2 + 1
• instead of minus operator, we can write as
• R2 is the symbol for the 1’s complement of R2
• Adding 1 to 1’s complement produces 2’s complement
• Adding the contents of R1 to the 2's complement of R2 is equivalent to R1-R2.
Binary Adder:
• Digital circuit that forms the arithmetic sum of 2 bits and the previous carry is called
FULL ADDER.
• Digital circuit that generates the arithmetic sum of 2 binary numbers of any lengths is
called BINARY ADDER.
• The following Figure shows the interconnections of four full-adders (FA) to provide a 4-
bit binary adder.
• The augends bits of A and the addend bits of B are designated by subscript numbers
from right to left, with subscript 0 denoting the low-order bit.
• The carries are connected in a chain through the full-adders. The input carry to the
binary adder is Co and the output carry is C4. The S outputs of the full-adders generate
the required sum bits.
• An n-bit binary adder requires n full-adders.
Binary Adder – Subtractor
• The addition and subtraction operations can be combined into one common circuit by
including an exclusive-OR gate with each full-adder.
• A 4-bit adder-subtractor circuit is shown in the following Figure.
➢The mode input M controls the operation. When M = 0 the circuit is an adder and
when M = 1 the circuit becomes a subtractor.
➢Each exclusive-OR gate receives input M and one of the inputs of B
➢When M = 0, we have B xor 0 = B. The full-adders receive the value of B, the input
carry is 0, and the circuit performs A plus B.
➢When M = 1, we have B xor 1 = B' and Co = 1.
➢The B inputs are all complemented and a 1 is added through the input carry.
➢The circuit performs the operation A plus the 2's complement of B.
Binary Incrementor
• The increment microoperation adds one to a number in a register.
• For example, if a 4-bit register has a binary value 0110, it will go to 0111 after it is
incremented.
• This can be accomplished by means of half-adders connected in cascade.
• The diagram of a 4-bit 'combinational circuit incrementor is shown in the following
Figure.
• One of the inputs to the least significant half-adder (HA) is connected to logic-1 and
the other input is connected to the least significant bit of the number to be
incremented.
• The output carry from one half-adder is connected to one of the inputs of the next-
higher-order half-adder.
• The circuit receives the four bits from A0 through A3, adds one to it, and generates the
incremented output in S0 through S3.
• The output carry C4 will be 1 only after incrementing binary 1111. This also causes
outputs S0 through S3 to go to 0.
Decrement
• When S1S0= 11, all l's are inserted into the Y inputs of the adder to
produce the decrement operation D = A -1 when Cin = 0.
• This is because a number with all 1's is equal to the 2's complement of 1
(the 2's complement of binary 0001 is 1111). Adding a number A to the
2's complement of 1 produces F = A + 2's complement of 1 = A — 1. When
Cin = 1, then D = A -1 + 1=A, which causes a direct transfer from input A to
output D.
Logic Micro-operations
• Logic microoperations specify binary operations for strings of bits stored in registers.
• These operations consider each bit of the register separately and treat them as binary
variables.
• For example, the exclusive-OR microoperation with the contents of two registers RI
and R2 is symbolized by the statement
• It specifies a logic microoperation to be executed on the individual bits of the registers
provided that the control variable P = 1.
List of Logic Microoperations
• There are 16 different logic operations that can be performed with two binary variables.
• They can be determined from all possible truth tables obtained with two binary variables as shown in
Table 4-5.
Hardware Implementation
• Figure 4-10 shows one stage of a circuit that
generates the four basic logic
microoperations.
• It consists of four gates and a multiplexer.
Each of the four logic operations is generated
through a gate that performs the required
logic.
• The outputs of the gates are applied to the
data inputs of the multiplexer. The two
selection inputs S1 and S0 choose one of the
data inputs of the multiplexer and direct its
value to the output.
Hardware Implementation
• Figure 4-10 shows one stage of a circuit that
generates the four basic logic
microoperations.
• It consists of four gates and a multiplexer.
Each of the four logic operations is generated
through a gate that performs the required
logic.
• The outputs of the gates are applied to the
data inputs of the multiplexer. The two
selection inputs S1 and S0 choose one of the
data inputs of the multiplexer and direct its
value to the output.
Shift Microoperations
• Shift microoperations are used for serial
transfer of data.
• The contents of a register can be shifted to
the left or the right.
• During a shift-left operation the serial
input transfers a bit into the rightmost
position.
• During a shift-right operation the serial
input transfers a bit into the leftmost
position.
• There are three types of shifts: logical,
circular, and arithmetic.
• The symbolic notation for the shift
microoperations is shown in Table 4-7.
Arithmetic Logic Shift Unit
Instead of having individual registers performing the microoperations directly,
computer systems employ a number of storage registers connected to a common
operational unit called an arithmetic logic unit, abbreviated ALU.
• The ALU is a combinational circuit so that the entire register transfer operation from
the source registers through the ALU and into the destination register can be
performed during one clock pulse period.
• The shift microoperations are often performed in a separate unit, but sometimes the
shift unit is made part of the overall ALU.
• The arithmetic, logic, and shift circuits introduced in previous sections can be
combined into one ALU with common selection variables. One stage of an arithmetic
logic shift unit is shown in Fig. 4- 13.
• Particular microoperation is selected with
inputs S1 and S0. A 4 x 1 multiplexer at the
output chooses between an arithmetic
output in Di and a logic output in Ei.
• The data in the multiplexer are selected
with inputs S3 and S2. The other two data
inputs to the multiplexer receive inputs Ai-1
for the shift-right operation and Ai+1 for the
shift-left operation.
• The circuit whose one stage is specified in
Fig. 4-13 provides eight arithmetic
operation, four logic operations, and two
shift operations.
• Each operation is selected with the five
variables S3, S2, S1, S0 and Cin.
• The input carry Cin is used for selecting an
arithmetic operation only.
• Table 4-8 lists the 14 operations of the ALU.
The first eight are arithmetic operations and
are selected with S3S2 = 00.
• The next four are logic and are selected with
S3S2 = 01.
• The input carry has no effect during the logic
operations and is marked with don't-care x’s.
• The last two operations are shift operations
and are selected with S3S2= 10 and 11.
• The other three selection inputs have no
effect on the shift.
Data Representation
➢ Registers contain either data or control information
➢ Control information is a bit or group of bits used to specify the sequence of command signals needed for
data manipulation
➢ Data are numbers and other binary-coded information that are operated on Possible data types in
registers.
Types of Data Representation
Number Representation
➢ Decimal (Base-10)
➢ Regular human-readable form (e.g., 45)
➢ Binary (Base-2)
➢ Used internally by computers (e.g., 101101)
➢ Octal (Base-8)
➢ Hexadecimal (Base-16)
➢ Shorthand representations for binary
➢ Hex: 1 Hex digit = 4 binary bits
1. Fixed Point Representation
• Fixed-point representation is a method of representing real numbers using a fixed
number of bits for the integer and fractional parts.
• It is suitable for systems where floating point hardware is not available or where high
performance and low power consumption are needed (e.g., embedded systems).
• Structure: [Sign Bit][Integer Bits][Fractional Bits]
• Assuming an 8-bit fixed-point format with:
- 1 sign bit
- 3 integer bits
- 4 fractional bits
Format: [S][III].[FFFF]
Example 1: +5.5
Integer = 5 → Binary: 101
Fraction = 0.5 → Binary: 1000 (0.5 = 2⁻¹)
Sign bit = 0
Binary Representation: 0 101.1000 → 01011000
Result: +5.5
Example 2: -2.75
Integer = 2 → Binary: 010
Fraction = 0.75 → Binary: 1100 (0.5 + 0.25 = 2⁻¹ + 2⁻²)
Sign bit = 1
Binary Representation: 1 010.1100 → 10101100
Result: -2.75
Floating-Point Representation
➢The floating number representation of a number has two part:
➢the first part represents a signed fixed point number called mantissa.
➢The second part of designates the position of the decimal (or binary) point and is
called the exponent.
➢The fixed point mantissa may be fraction or an integer.
➢Floating -point is always interpreted to represent a number in the following form:
Mxre
Only the mantissa m and the exponent e are physically represented in the register
Example
Suppose number is using 32-bit format:
The 1 bit sign bit, 8 bits for signed exponent, and 23 bits for the fractional part.
The leading bit 1 is not stored (as it is always 1 for a normalized number) and is
referred to as a “hidden bit”.
• Then −53.5 is normalized as -53.5=(-110101.1)2=(-1.101011)x25 , which is
represented as following below,