If consecutively/ continuously used overlapping
Default overlapping
Specifically mentioned non overlapping go with non overlapping
Bubbled Or gate == NAND GATE
$display and $monitor print stm
Synthesizable converted into real hardware
Non Synthesizable can’t be converted into hardware (Testbenches
and Debugging)
module priority_encoder_8to3 (
input [7:0] d,
output reg [2:0] y,
output reg valid
);
always @(*) begin
valid = 1'b1;
if (d[7]) y = 3'b111;
else if (d[6]) y = 3'b110;
else if (d[5]) y = 3'b101;
else if (d[4]) y = 3'b100;
else if (d[3]) y = 3'b011;
else if (d[2]) y = 3'b010;
else if (d[1]) y = 3'b001;
else if (d[0]) y = 3'b000;
else begin
y = 3'b000;
valid = 1'b0; // no input active
end
end
endmodule
module alu (
input [3:0] a, b,
input [2:0] sel,
output [3:0] y
);
assign y = (sel == 3'b000) ? (a + b) :
(sel == 3'b001) ? (a - b) :
(sel == 3'b010) ? (a + 1) :
(sel == 3'b011) ? (a * b) :
(sel == 3'b100) ? (a ^ b) :
(sel == 3'b101) ? (a - 1) :
(sel == 3'b110) ? (~a) :
(sel == 3’b111) ? (a>>2):
8’b00000000;
endmodule
module mux_logic_implementation (
input A, B, C, D,
output reg F
);
// Intermediate wires for MUX data inputs
wire i0, i1, i2, i3;
// Logic for each data input line based on B and D
assign i0 = (~B) | D; // B' + D
assign i1 = B & (~D); // B D'
assign i2 = B | D; // B + D
assign i3 = B ^ D; // B ^ D (XOR)
// 4:1 Multiplexer logic using selection lines A (s1) and C (s0)
always @(*) begin
case ({A, C})
2'b00: F = i0;
2'b01: F = i1;
2'b10: F = i2;
2'b11: F = i3;
default: F = 1'bx;
endcase
end
endmodule
// Behavioral Verilog Code for 4-bit Universal Shift Register
module Universal_Shift_Register (
input clk,
input clear_b, // Active-low asynchronous reset
input [1:0] s, // Mode selection: {s1, s0}
input [3:0] I_par, // Parallel data input
input MSB_in, // Serial input for shift right
input LSB_in, // Serial input for shift left
output reg [3:0] A_par // Parallel data output
);
always @(posedge clk or negedge clear_b) begin
if (!clear_b) begin
// Asynchronous Reset: Clear the register to 0
A_par <= 4'b0000;
end else begin
case (s)
2'b00: A_par <= A_par; // No change
2'b01: A_par <= {MSB_in, A_par[3:1]}; // Shift Right
2'b10: A_par <= {A_par[2:0], LSB_in}; // Shift Left
2'b11: A_par <= I_par; // Parallel Load
default: A_par <= A_par;
endcase
end
end
endmodule
// Testbench for Universal Shift Register
module tb_Universal_Shift_Register;
// Inputs
reg clk;
reg clear_b;
reg [1:0] s;
reg [3:0] I_par;
reg MSB_in;
reg LSB_in;
// Output
wire [3:0] A_par;
// Instantiate the Unit Under Test (UUT)
Universal_Shift_Register uut (
.clk(clk),
.clear_b(clear_b),
.s(s),
.I_par(I_par),
.MSB_in(MSB_in),
.LSB_in(LSB_in),
.A_par(A_par)
);
// Clock Generation: 10ns period
always #5 clk = ~clk;
initial begin
// Initialize Inputs
clk = 0;
clear_b = 0;
s = 0;
I_par = 4'b1010;
MSB_in = 0;
LSB_in = 0;
// Reset the system
#10 clear_b = 1;
// Test Parallel Load (s = 11)
#10 s = 2'b11; I_par = 4'b1101;
// Test Shift Right (s = 01)
#10 s = 2'b01; MSB_in = 1; // Expected: 1110
#10 MSB_in = 0; // Expected: 0111
// Test Shift Left (s = 10)
#10 s = 2'b10; LSB_in = 1; // Expected: 1111
#10 LSB_in = 0; // Expected: 1110
// Test No Change (s = 00)
#10 s = 2'b00;
// Finish simulation
#50 $finish;
end
initial begin
$monitor("Time=%0t | s=%b | I_par=%b | MSB_in=%b | LSB_in=%b |
A_par=%b",
$time, s, I_par, MSB_in, LSB_in, A_par);
end
endmodule
MULTIPLICATION BY 4 LEFT SHIFT BY2 (for 8 shift by 3, 2 shift by 1 and so
on)
The 2’s complement can be obtained by keeping the lsbs as such until the
first 1, and then complement the remaining bits
[Link]
A iii && is logical and not bitwise and so the result will be in 1 bit (1/0)
B 4{a} 1111, 2{b}0000, c10 :: 1111_0000_10
Use 2 3:8 decoder (in notes)
Vv confusing
module seq_counter (
input clk,
input reset,
output reg [3:0] q
);
always @(posedge clk or posedge reset) begin
if (reset)
q <= 4'b0000;
else begin
case (q)
4'b0000: q <= 4'b0010; // 0 → 2
4'b0010: q <= 4'b0011; // 2 → 3
4'b0011: q <= 4'b0111; // 3 → 7
4'b0111: q <= 4'b1000; // 7 → 8
4'b1000: q <= 4'b1011; // 8 → 11
4'b1011: q <= 4'b1111; // 11 → 15
4'b1111: q <= 4'b0000; // 15 → 0
default: q <= 4'b0000;
endcase
end
end
endmodule
Q Design a 1 x 8 demultiplexer circuit using 1 x 4 demultiplexers and
implement the full adder logic using the same
Q Design a T flip flop using SR flip flop and write Verilog code for the same
using behavioural modelling
module sr_to_t (
input clk,
input S, R,
output reg Q,
output T
);
// T equation
assign T = (S & ~Q) | (R & Q);
// Flip-flop behavior (SR FF)
always @(posedge clk) begin
case ({S,R})
2'b00: Q <= Q; // No change
2'b01: Q <= 0; // Reset
2'b10: Q <= 1; // Set
2'b11: Q <= 1'bx; // Invalid
endcase
end
endmodule
Q Design an Excess-3-to-BCD code converter using (a)PLA and (b) PAL
module boolean_function (
output F,
input A, B, C, D
);
wire a_n, b_n, c_n, d_n;
wire t1, t2, t3, t4;
// Inverters
not n1 (a_n, A);
not n2 (b_n, B);
not n3 (c_n, C);
not n4 (d_n, D);
// Minterms
// t1 = A'B'C'D'
and g1 (t1, a_n, b_n, c_n, d_n);
// t2 = A'BC'D
and g2 (t2, a_n, B, c_n, D);
// t3 = AB'CD'
and g3 (t3, A, b_n, C, d_n);
// t4 = ABCD
and g4 (t4, A, B, C, D);
// Final OR gate
or g5 (F, t1, t2, t3, t4);
endmodule
module tb_boolean_function;
reg A, B, C, D;
wire F;
// Instantiate the design
boolean_function uut (
.F(F),
.A(A),
.B(B),
.C(C),
.D(D)
);
initial begin
$display("A B C D | F");
$display("---------");
// Loop through all 16 combinations
{A, B, C, D} = 4'b0000;
repeat (16) begin
#10 $display("%b %b %b %b | %b", A, B, C, D, F);
{A, B, C, D} = {A, B, C, D} + 1;
end
$finish;
end
endmodule
1st write mux eqn for bottom one ::
imp
ANS: J2: Q1Q0X , K2: 1 , J1: (Q0+Q2)X- , K1: Q0+X , J0: Q1+X , K0:
Q1+X- , Z=Q2
Q design a synchronous MOD-12 counter using d ff. Write a behavioural
code and testbench to verify the design
module mod12_counter (
input clk,
input reset,
output reg [3:0] q
);
always @(posedge clk or posedge reset) begin
if (reset)
q <= 4'b0000;
else if (q == 4'd11)
q <= 4'b0000; // reset after 11
else
q <= q + 1; // increment
end
endmodule
module tb_mod12;
reg clk, reset;
wire [3:0] q;
mod12_counter uut (
.clk(clk),
.reset(reset),
.q(q)
);
// Clock generation
always #5 clk = ~clk;
initial begin
clk = 0;
reset = 1;
#10 reset = 0;
// Run for some cycles
#200;
$stop;
end
initial begin
$monitor("Time=%0t | q=%d", $time, q);
end
endmodule
For this Q, memorize the characteristic eqn to find q+ quickly
Simplification error
Do from b1 (skip g1)