COMPUTER ORGANIZATION

Chapter 2
DNCS
I NT RODUCT ION TO COMPUT E R ORGANIZAT ION
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NCS) SEMESTER 1 10/23/2025
JONATHAN WALLAS
 Ta b l e o f C o n te n t
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In this course you will learn about;

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 Introduction to Computer Organization
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In this session, you will cover the following:

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 Introduction to Computer Organization
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Introduction to Computer Organization

Computer Organization is the study of the internal operational units and functional arrangement of the various components of a computer system and how they are
interconnected to execute instructions efficiently. In simpler terms, while computer architecture defines what a computer does, computer organization defines how the
computer does it—how the CPU, memory, input/output devices, and buses are physically connected and operate to execute instructions.
Evolution and Generations of Computers
Evolution of computers is driven by the need for faster computation, increased reliability, reduced cost, and better efficiency. Earlier, computers were mechanical,
then electromechanical, and eventually fully electronic. Key milestones in the evolution include:.
[Link] Computers
Mechanical computers are computing devices that operate purely thru mechanical components e.g., gears, levers, shafts, and wheels. They perform calculations
by physical movement of these parts without using electricity or electronic signals. No electricity involved (manual or steam-powered). Used gears, cams, and levers
for operations. Slow and less accurate compared to modern computers. Mostly designed for arithmetic and tabulation purposes. Abacus, Pascaline (1642), Leibniz
Calculator (Step Reckoner), Difference Engine (1822), Analytical Engine (1837), Slide Rule, Monroe Calculator
[Link] Computers
Electromechanical computers use both electrical and mechanical components. They employ switches, relays, and motors to automate mechanical processes,
enabling faster and more reliable computation. Combination of mechanical motion and electrical control. Used relays (electrically controlled switches). Faster
than purely mechanical computers but slower than electronic ones. Commonly used in the 1930s–1940s for scientific and military calculations. Zuse Z1 (1938),
Zuse Z3 (1941), Harvard Mark I (1944), Harvard Mark II (1947), Bell Labs Model I Complex Calculator (1939), Heath Robinson Machine (1943)

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Electronic Computers
Electronic computers use electronic circuits instead of mechanical or electromechanical parts. They rely on vacuum tubes, transistors, and integrated circuits
(ICs) to perform calculations at very high speeds. No moving mechanical parts. Use of electrical signals through semiconductors. Extremely fast, reliable, and efficient.
Divided into generations based on technology (Vacuum tubes → Transistors → ICs → Microprocessors). ENIAC (1946), EDVAC (1949), EDSAC (1949), UNIVAC
I (1951), IBM 701 (1952), IBM System/360 (1964), Apple I (1976), IBM PC (1981) First Generation (Vacuum Tubes):
Generations of Computers Huge in size; filled rooms. Programmed using machine language.
Limited reliability and speed.
The history of electronic computers is divided into five main generations, based on the
technology used in the processing unit. Second Generation (Transistors):
Smaller and more reliable than vacuum tubes.
Introduced assembly language programming.
Reduced heat generation and cost.
Third Generation (Integrated Circuits):
Enabled multiprogramming and time-sharing systems.
Faster processing, smaller size, lower cost.
High-level languages like COBOL and FORTRAN widely used.
Fourth Generation (Microprocessors):
Entire CPU on a single silicon chip.
Rise of personal computers and graphical interfaces.
Mass production led to widespread accessibility.
Fifth Generation (VLSI and AI):
Uses Very Large Scale Integration (VLSI) technology.
AI and neural networks integrated for intelligent computing.
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Portable, low-power, high-performance devices with parallel and
distributed processing.
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Functional Units of a Computer System

A computer system is designed to receive, process, store, and output data. To perform these tasks efficiently, a computer is divided into several functional units,
each responsible for a specific set of operations. Understanding these units is fundamental to computer organization and architecture.

[Link] Unit: The input unit is responsible for receiving data and instructions from
external sources (such as keyboards, mice, scanners) and converting them into a form
that the computer can process. Key Functions:
• Accepting data from the user or external devices.
• Converting input into binary code (machine-readable format).
• Sending data to the memory or processor for further processing.
Examples of Input Devices: Keyboard, Mouse, Scanner, Microphone, Barcode Reader.
o Touchscreens. Sensors, Stylus pens. Voice Assistants (e.g., Siri, Alexa).
o Biometric devices (face/fingerprint recognition). Iot-based inputs from smart devices

[Link] Unit: The output unit is responsible for presenting processed data to the
user in a human-readable or usable form. Key Functions:
• Receiving processed information from memory or CPU.
• Converting binary results into user-understandable formats.
• Displaying results through output devices.
Examples of Output Devices: Monitor, Printer, Speaker, Projector.

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[Link] Processing Unit (CPU)

A CPU is rectangular chip where all the computer computation and control
take place. It has three main components:
[Link] and Logic Unit (ALU)
• Performs all arithmetic operations (addition, subtraction, multiplication, division).
• Performs logical operations (AND, OR, NOT, comparisons).
• Works on data received from registers and memory.
[Link] Unit (CU)
• Directs and coordinates all operations within the computer.
• Fetches instructions from memory, decodes them, and executes them.
• Generates control signals to regulate data flow between ALU, memory, and I/O
units.
[Link]
• Small, fast storage units inside the CPU.
• Temporarily hold data, instructions, or addresses during processing.
• Types: General-purpose registers, Special-purpose registers (Instruction Register,
Program Counter, Accumulator, Status Registers).

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[Link] Unit 5. Buses and Interconnection Systems

The memory unit stores data, instructions, and intermediate results required for Buses are communication pathways that connect different functional units of a
processing. Key Features: computer. Types of Buses:
• Allows quick access to data by the CPU. • Data Bus: Transfers data between CPU, memory, and I/O devices.
• Stores both program instructions and data temporarily or permanently. • Address Bus: Specifies memory locations for read/write operations.
• Organized in a hierarchy for speed, capacity, and cost optimization. • Control Bus: Carries control signals (read, write, interrupt) to coordinate
Memory Hierarchy: operations.
[Link] – Inside CPU, very fast, small capacity. Function:
[Link] Memory – Faster than RAM, stores frequently used data. • Enables data transfer between input, output, CPU, and memory.
[Link] Memory (RAM, ROM) – Stores currently running programs and data. • Ensures synchronized communication between components.
[Link] Storage (HDD, SSD) – Permanent storage for large volumes of data.

[Link] and Auxiliary Storage

While not always considered part of the core functional units, secondary storage provides permanent storage for data and programs. Examples: Hard disks, Solid-
state drives (SSD), Optical disks (CD/DVD), USB drives. Functions: ●Stores programs and data long-term. ●Acts as a backup for main memory.
Key Points
●Input Unit: Data acquisition. ●Output Unit: Results presentation.
●CPU: Processing and control. ●Memory Unit: Storage and retrieval.
●Buses: Communication pathways. ●Secondary Storage: Long-term data retention.

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 C o m p u t e r S ys t e m B l o c k D i a g r a m a n d t h e C P U
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Importances of Computer Organization

Understanding How Computers Work: Computer organization provides insight into how data flows thru a computer system, how instructions are executed, and
how hardware components interact to perform tasks. For example, Instruction Fetching and Execution: Knowing how the central processing unit fetches, decodes,
and executes instructions helps in debugging assembly code or optimizing compilers.
Optimizing Software Performance: By understanding computer organization, programmers can proficiently write software that efficiently utilizes resources, such as
memory and CPU, to improve execution speed and responsiveness. For example, Loop Unrolling: A developer can optimize loops in a program to properly use CPU
instruction pipelining. Cache Optimization: Software is made to use data locality principles, ensuring that frequently accessed data stays in faster memory (cache).
Designing Efficient Algorithms: Knowing hardware abilities helps in designing algorithms that capably control specific processor features, like pipelining or parallel
processing, for enhanced performance. For example, Sorting Algorithms: Implementing quicksort ably involves controlling memory hierarchies to cut cache misses.
Building and Designing Hardware: For computer hardware engineers, computer organization knowledge is important for designing processors, memory systems,
input/output devices, and additional hardware components. For example, Custom Processors: Designing CPUs with specific instruction sets (e.g., RISC-V Reduced
Instruction Set Computer-V processors for embedded systems). Memory Controllers: Building efficient memory access mechanisms, such as DDR controllers, to
optimize data throughput. A DDR Controller (Double Data Rate Controller) is a hardware interface that manages communication amid a CPU (or other processing
units) and DDR memory modules.
Enabling Hardware-software Integration: Knowing computer organization links the gap between hardware and software, enabling smooth integration of the two for
optimized system performance. E.g., Device Drivers: Writing drivers that greatly enable software to communicate with hardware peripherals. System Boot Process:
Understanding BIOS or UEFI interaction with hardware during system initialization. BIOS (Basic Input/Output System) and UEFI (Unified Extensible Firmware
Interface) are firmware interfaces that initialize computer hardware and pass control to the operating system during the boot process. UEFI is the modern successor to
BIOS, offering more features, flexibility, and compatibility with modern computing needs.

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Improving System Performance: Computer organization Knowledge helps in computer system optimization, like tuning cache, scheduling processes, or improving
input/output operations. For example, Cache Tuning: Adjusting cache policies or sizes to improve data access speed in specific workloads.
Understand Instruction Execution: Learning instruction cycles, pipelining, and instruction set architecture (ISA) helps developers know how code is translated
into machine instructions, executed and debugged. E.g., Opcode Analysis: Writing assembly code that takes advantage of specific CPU instructions. Pipelining:
Designing software to reduce pipeline hazards in a multi-stage processor. CPU pipelining is a method used in computer processors to increase instruction amount,
allowing many instructions to overlap in execution. It divides the execution of instructions into separate stages, where each stage performs part of the work..
Exploring Emerging Technologies: Computer organization concepts are vital for exploring cutting-edge technologies such as quantum computing, neuromorphic
computing, and hardware acceleration. For example, Neuromorphic Chips: Developing chips inspired by neural networks for AI applications.
Understanding Memory Hierarchies: Learning about memory categories (e.g., cache, RAM, ROM, and secondary storage) and their hierarchies is important for
optimizing memory usage and performance. A very clear understanding of memory hierarchies helps in designing systems with balanced speed and cost. E.g., Cache
Hierarchy: Designing software to use205 L1 and L2 caches effectively. Memory Allocation: Using methods like memory pooling to reduce fragmentation in high-
performance apps. Memory fragmentation is a condition in computer memory management where available memory is divided into small, scattered blocks, making it
difficult or impossible to allocate memory efficiently. Fragmentation can reduce the performance of systems and lead to wastage of memory resources.
Preparing For Specialized Fields: Fields like embedded systems, robotics, and IoT need knowledge of PC organization to design and optimize low-level systems.
Such areas really rely on computer organization principles. Embedded Systems: Designing hardware-software co-designed solutions like automotive control units.
Robotics: Creating efficient systems for real-time sensor data processing. IoT Devices: Building low-power systems that optimize processing and communication.

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Basic Computer Operations

A computer performs its functions by following a set of basic operational concepts that define how data is processed, stored, and transferred. These concepts form
the basis of computer organization and architecture.
[Link], Processing, Storage, and Output Cycle
The fundamental operation of a computer is often described as the Input → Process → Storage → Output cycle:
[Link]: Accepts data and instructions from external devices. Converts input into machine-readable format (binary).
[Link]: Performed by the CPU (Central Processing Unit).
Includes arithmetic calculations, logical operations, and decision-making.
[Link]: Temporary storage occurs in registers and RAM.
Permanent storage occurs in secondary memory (HDD, SSD).
[Link]: Processed data is presented to the user in human-readable form.
Delivered through monitors, printers, speakers, etc.

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[Link]-Decode-Execute Cycle
The CPU operates by repeatedly performing the instruction cycle, which consists of:
[Link]: CPU fetches the next instruction from memory (main memory/RAM) based on the Program Counter (PC).
[Link]: Control Unit interprets the instruction and determines what operation is required.
[Link]: ALU performs arithmetic or logical operations. Data is transferred to memory or output devices if required.

The Fetch-Execute Cycle

Stored program computers are designed to fetch, decode and execute instructions in a
continuous cycle. This cycle is called the fetch-execute cycle.
Fetch: The Program Counter (PC) contains the address of the next instruction to be
fetched. The address contained in the PC is copied to the Memory Address Register (MAR).
The instruction is copied from the memory location contained in the MAR and placed in the
Memory
Buffer Register (MBR): The entire instruction is copied from the MBR and placed in the
Current Instruction Register (CIR). The PC is incremented so that it points to the next
instruction to be fetched
Execute: The address part of the instruction is placed in the MAR. The instruction is
decoded and executed
The processor checks for interrupts (signals from devices or other sources seeking the
attention of the processor) and either branches to the relevant interrupt service routine or
starts the cycle again.

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[Link] Hierarchy Concept

Computers use a hierarchical memory system to balance speed, cost, and capacity:
1. Registers: Fastest, smallest memory inside the CPU.
2. Cache Memory: Stores frequently accessed data to reduce CPU wait time.
3. Main Memory (RAM, ROM): Stores current programs and data.
4. Secondary Storage: Large capacity, permanent storage (HDD, SSD).
Principle: Faster memory is smaller and more expensive; slower memory is larger and cheaper.
[Link] Systems
Buses are communication pathways connecting CPU, memory, and I/O devices:
• Data Bus: Transfers actual data.
• Address Bus: Specifies memory or I/O locations.
• Control Bus: Sends control signals for read/write operations.
Buses enable synchronized and controlled data transfer in the computer system.
What is a System Bus? A bus is a set of electrical wires (lines) that connects the various
hardware components of a computer system. It works as a communication pathway thru
which data flows from one hardware component to another hardware component. A bus
that connects major components (CPU, memory and I/O devices) of a computer system
is called a System Bus. Why Do We Need Bus? A computer system is made of different
components for example memory, ALU, registers etc. Each component should be able to
communicate with each other for proper execution of instructions and information flow.
So, we use a common component to connect to every necessary component i.e. BUS.

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A System Bus is a communication pathway that connects the major components of a computer system such as the Central Processing Unit (CPU), Main Memory
(RAM), and Input/Output (I/O) devices — allowing them to transfer data, instructions, and control signals efficiently. A System Bus is a collection of parallel wires or
lines that carry information (data, addresses, and control signals) among the components of a computer. It acts as a shared transmission medium through which the
CPU communicates with memory and I/O devices. The system bus is divided into three primary types of buses, each serving a specific function: Main Components
of the System Bus
[Link] Bus: Purpose: Transfers actual data between PC components e.g., CPU, memory, and I/O devices. Direction: Bidirectional – data can flow both to and
from the CPU. Width: The width (e.g., 8-bit, 16-bit, 32-bit, 64-bit) determines how much data can be transferred at once. E.g., A 64-bit data bus can transfer 64 bits of
data simultaneously.
[Link] Bus: Purpose: Carries the memory addresses of data or instructions that the CPU wants to read or write. Direction: Unidirectional – only from the CPU
to memory or I/O. Width: Determines the maximum addressable memory space.
[Link] Bus: Purpose: Carries control signals that coordinate and manage operations between the CPU and other components. Direction: Bidirectional – used
by both CPU and peripherals. Common control signals include: Memory Read (MEMR), Memory Write (MEMW), I/O Read (IOR), I/O Write (IOW), Clock signals,
Interrupt signals and Bus request/acknowledge signals

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Functions of the System Bus

[Link] Transfer Between CPU and Memory: The system bus enables the movement of data from the CPU to memory or from memory to the CPU for processing.
Examples: Transferring data from RAM to the CPU register during instruction execution. Storing computed results from the CPU back into a memory location.
[Link] Transmission: The address bus sends the memory or I/O address from the CPU to identify where data should be read or written. E.g., CPU sends
address 0x2050 to fetch an instruction from memory. CPU sends address 0x3F8 to access the COM1 serial port.
[Link] Fetching: A system bus allows the CPU to fetch program instructions stored in memory through coordinated use of data, address, and control lines.
Examples: Fetching the next instruction from the instruction register in RAM. Fetching a machine code instruction like MOV A, B from memory address 0x2000.
[Link] Read Operation: It facilitates reading data or instructions from the memory to the CPU through the Read control signal. E.g., CPU reads a variable
value from the memory address 0x3000. CPU reads an operand needed for an arithmetic operation.
[Link] Write Operation: It enables the CPU to store (write) data into the memory using the Write control signal. E.g., Writing the result of an addition operation
to memory address 0x4000. Saving a program counter value during a function call.
[Link]/Output Communication: The bus supports data exchange between the CPU and external I/O devices like keyboards, printers, or disks. E.g., CPU reads
input data from the keyboard. CPU sends processed data to a display device.
[Link] Control and Coordination: The system bus carries control signals to start, stop, or synchronize operations among connected devices. E.g., Control
signal instructs the printer to start printing data. Disk controller receives a signal to begin reading data blocks.
[Link] Handling: The bus transmits interrupt requests from peripherals to the CPU, allowing devices to gain attention when necessary. E.g., Keyboard sends
an interrupt when a key is pressed. Timer chip sends an interrupt to signal the end of a time interval.
[Link] Memory Access (DMA): It supports high-speed data transfer between memory and peripherals without CPU intervention, managed by a DMA controller.
Examples: Transferring a block of data from the disk to RAM using DMA. Sending data directly from memory to a network card.

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System Bus Characteristics

[Link] Width: Refers to the number of bits that can be transmitted at the same time. Determines how much data or address information can travel at once. E.g., A
32-bit data bus transfers 32 bits of data in one operation. A 64-bit address bus allows addressing up to 264memory locations.
[Link] Speed (Clock Frequency): Indicates how fast data travels across the bus, measured in MHz or GHz. Higher speed means faster communication between
components. Examples: A 100 MHz front-side bus (FSB) in older CPUs. A 3200 MHz system bus in modern processors for high-speed operations.
[Link]: Refers to the amount of data the bus can transfer per second. It depends on bus width × clock speed. E.g., A 64-bit bus at 100 MHz = 800 MB/s
bandwidth. A 128-bit bus at 133 MHz = 2.1 GB/s bandwidth.
[Link] Architecture (Structure): Defines how buses are organized and connected within a system. Common types: Single bus, Multiple bus, or Hierarchical bus
systems. Examples: A single-bus structure where all devices share one communication line. A dual-bus architecture separating memory and I/O buses.
[Link] Direction: Describes whether communication is unidirectional or bidirectional. Determines if signals can move one way or both ways. E.g., Address bus –
unidirectional (from CPU to memory). Data bus – bidirectional (CPU ↔ Memory).
[Link] Multiplexing: Allows shared use of bus lines for multiple purposes (e.g., address and data). Reduces pin count and cost but may require additional control
logic. Examples: Intel 8085 microprocessor uses multiplexed address/data bus (AD0–AD7). PCI bus multiplexes address and data on the same lines.
[Link] Arbitration: Mechanism to decide which device gets control of the bus when multiple devices request it simultaneously. E.g., DMA controller gains priority
over CPU for direct memory access. PCI bus arbitration where multiple cards compete for bus access.
[Link] Timing: Defines how bus activities are coordinated in time using clock signals. Ensures proper synchronization during data transfers. E.g., Synchronous bus
– all devices operate with a common clock. Asynchronous bus – devices communicate with handshaking signals.
[Link] Protocol: Refers to a set of rules and standards governing how devices communicate over a bus. Defines signal timing, data validity, and acknowledgment.
E.g., PCI Express protocol defines packet-based serial communication. USB protocol specifies host-device communication and power delivery.
[Link] Capacity (Load Handling): The number of devices or nodes that can be connected without degrading performance. Too many devices can cause signal
delay or noise. E.g., SCSI bus supports up to 16 connected devices. I²C bus can support multiple slave devices but is limited by capacitance.
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Advantages of the System Bus

[Link] Communication Architecture: A system bus provides a single, shared communication channel, reducing the need for multiple separate connections
among devices. E.g., Instead of separate lines for CPU–RAM and CPU–I/O, one bus system handles both. In a PC, one bus links the processor, memory, and chipset.
[Link] Efficiency: A single bus structure is economical since fewer physical lines and connectors are required. E.g., Designing a motherboard with a single system
bus reduces material costs. Embedded systems use shared bus lines to minimize production expenses.
[Link] System Expansion: A system bus allows adding new hardware components without redesigning the entire architecture. E.g., Adding a new printer or
scanner via the I/O bus (e.g., USB or PCIe). Installing extra RAM modules connected through the memory bus.
[Link] Sharing Between Components: A system bus allows direct data transfer between CPU, memory, and I/O devices efficiently. E.g., CPU fetching instructions
from RAM via the data bus. CPU sending processed data to a disk controller for storage.
[Link]: Buses follow universal communication standards, allowing components from different manufacturers to work together. E.g., USB standard allows
keyboards, mice, and drives from any vendor to connect. PCI Express (PCIe) supports GPUs and network cards across different brands.
[Link] System Performance: A high-speed bus allows faster data transmission, improving overall system performance. E.g., 64-bit system bus handles
more data per clock cycle than a 32-bit bus. High-speed PCIe 5.0 bus transfers data at up to 32 GT/s.
[Link]: The bus system can accommodate technological upgrades (faster CPUs, more RAM, newer devices) without changing the architecture.
Examples: Upgrading from DDR3 to DDR5 RAM using the same system bus design. PCIe slots support faster cards with each generation.
[Link] in Device Interconnection: Multiple devices can be connected through a single bus, providing flexibility and modular design. E.g., Connecting
external drives, webcams, and keyboards through USB. Using a shared I²C bus for multiple sensors in microcontroller systems.
[Link] Data Flow Control: A control bus manages read, write, and timing operations, ensuring smooth and conflict-free communication. E.g., The RD (Read)
signal coordinates memory read operations. The WR (Write) signal ensures data is properly stored to memory.
[Link] Multiple Communication Types: A system bus supports data, address, and control transmissions simultaneously, making operations more efficient.
Examples: Address bus specifies the location while data bus transmits
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Disadvantages of the System Bus

[Link] Limitation: The system bus has a fixed bandwidth, limiting the amount of data that can be transferred at a time. When multiple devices request access,
performance drops. Examples: When multiple USB devices and the GPU share the same bus, data transfer slows down. In older Pentium systems, the FSB (Front
Side Bus) limited CPU-memory speed.
[Link] Contention: Multiple devices trying to use the bus simultaneously cause contention, resulting in delays or data collisions. Examples: Two I/O devices trying to
access main memory at the same time. CPU and DMA controller requesting bus access concurrently.
[Link] Effect: All data passes through a single shared bus, creating a “traffic jam” known as the Von Neumann bottleneck. Examples: High-speed CPU
waiting for slow memory access. GPU processing delayed because system bus cannot transfer data fast enough.
[Link] Scalability: As more components are added, the shared bus becomes overloaded, limiting system expansion. Examples: Adding multiple network cards in
a PC reduces overall performance. Expanding RAM beyond bus design capacity leads to reduced throughput.
[Link] Degradation: As bus length or number of connected devices increases, signal integrity decreases, leading to data errors. Examples: Long motherboard
traces cause timing mismatches in signal transmission. Poor bus termination causes reflection and noise in data lines.
[Link] Issues: Bus communication introduces delay in transmitting signals between components. E.g. CPU waiting for memory read due to long propagation delay.
Peripheral devices experience lag during data transfer operations.
[Link] Consumption: A shared system bus increases power use, especially when driving long lines or multiple loads. Examples: Server motherboards with multiple
connected cards consume high bus power. Mobile devices drain batteries faster due to high-frequency bus switching.
[Link] Parallelism: Only one device can communicate on the bus at a time, reducing parallel processing potential. Examples: CPU cannot access memory while a
DMA transfer is in progress. Disk controller halts CPU operations during large data transfers.
[Link] Problems: Bus timing coordination among many devices can be difficult, especially at high clock speeds. Examples: Devices with different clock
rates cause synchronization delays. Mismatched timing between CPU and RAM leads to bus wait states.

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[Link] Signals and Timing

Control signals and timing in computer organization determine how and when operations occur between the CPU, memory, and input/output (I/O) devices. They
ensure that all components of a computer system communicate and perform actions in a synchronized and coordinated manner. Control Signals: These are electrical
signals generated by the Control Unit (CU) of the CPU to manage, coordinate, and direct the operations of all parts of the computer — such as reading or writing
data, executing instructions, or controlling the buses. Timing: Refers to the sequence and synchronization of control signals in relation to clock pulses. Timing
ensures that each operation occurs at the correct moment during instruction execution. Role of Control Signals: Control signals are responsible for: Controlling data
flow between the CPU, memory, and I/O. Coordinating fetch, decode, and execute cycles. Managing read and write operations. Ensuring synchronization among
all components. Controlling bus operations and device communication. Types of Control Signals: Control signals are typically divided into three major groups:
A. CPU to Memory and I/O Control Signals B. Internal CPU Control Signals
These signals are issued by the CPU to manage data transfers and device These signals control internal CPU operations — for example, movement of data between
communication. registers and ALU operations.
Control Signal Meaning / Purpose Control Signal Function
MEMR (Memory Read) CPU requests data from memory. Clock Signal Synchronizes all CPU activities.
MEMW (Memory Write) CPU writes data into memory. Instruction Decode Signal Activates decoding of instruction opcode.
IOR (I/O Read) CPU reads data from an I/O device. Register Select Signal Chooses which register to read/write.
IOW (I/O Write) CPU sends data to an I/O device. ALU Control Signal Directs ALU operation (ADD, SUB, AND, OR, etc.).
INTR (Interrupt Request) I/O device requests CPU attention. Flag Control Signal Sets or resets status flags (Zero, Carry, Sign, etc.).
INTA (Interrupt Acknowledge) CPU acknowledges an interrupt request. C. Bus Control Signals
HOLD Peripheral requests control of system bus. These manage access to the system bus among multiple components.
HLDA (Hold Acknowledge) CPU grants bus control to a peripheral. Control Signal Purpose
Bus Request (BR) Device requests control of the system bus.
Bus Grant (BG) CPU grants bus access to a requesting device.
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Clock Enable (CE) Enables or disables clock operation.
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[Link] in Computer Organization: Timing determines when control signals are asserted and how long they remain active. It ensures that all devices operate in
harmony with each other.
[Link] System Clock: A clock is an electronic oscillator that generates regular pulses. These pulses define the timing intervals (called clock cycles or T-states)
that control signal operations. The frequency of the clock (measured in MHz or GHz) determines the speed of CPU operations.
[Link] Machine Cycle: A machine cycle is the basic unit of time required to execute one low-level operation, such as reading or writing data. Each instruction may
take one or more machine cycles to complete.
[Link] and Timing During Instruction Execution: Each instruction passes through phases managed by control signals and timing:
Phase Activity Control Signals
Fetch Instruction fetched from memory. MEMR, Address Enable
Decode Opcode is interpreted by control unit. Decode Enable
Execute ALU performs operation. ALU Control, Flag Set
Store Result written to memory or register. MEMW or Register Write
[Link] of Control Signals and Timing
Aspect Importance
Synchronization Ensures components act in correct sequence.
Coordination Controls interactions between CPU, memory, and I/O.
Accuracy Prevents data corruption during transfers.
Efficiency Optimizes CPU cycle utilization.
Reliability Guarantees correct instruction execution order.

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[Link] Execution Types
[Link] Operations: Addition, subtraction, multiplication, division. [Link] Operations: AND, OR, NOT, XOR, comparisons. [Link] Transfer Operations:
Moving data between memory, registers, and I/O. [Link] Operations: Branching, jumping, or calling subroutines.
Instruction Execution Types in Computer Organization
Instruction execution is the process by which a CPU interprets and carries out instructions stored in main memory. Each instruction directs the CPU to perform a
specific operation such as moving data, performing arithmetic, or controlling program flow. Each instruction execution typically involves the following phases: [Link]
– Retrieve the instruction from memory. [Link] – Interpret the instruction (determine the operation and operands). [Link] – Perform the operation (e.g.,
addition, move, compare). [Link]/Write Back – Save the result to a register or memory location.
Types of Instruction Execution: Instruction types are generally classified according to the function they perform within the CPU. The major types include:
[Link] Transfer (or Data Movement) Instructions: Purpose: Move data between CPU registers, memory, and I/O devices.
Operation Description Examples
Load (MOV, LD) Transfer data from memory to a register. MOV A, B (Copy B into A)
Store (ST, STA) Transfer data from register to memory. STA 2000H
Input/Output (IN, OUT) Transfer data between CPU and I/O port. IN 00H, OUT 01H
Exchange (XCHG) Swap data between two registers. XCHG A, B
Example in Action: Instruction MOV A, B — the CPU copies the contents of register B into A during execution.
[Link] Instructions: Purpose: Perform mathematical calculations such as addition, subtraction, multiplication, and division.
Operation Description Examples
Addition (ADD) Add contents of two registers or memory locations. ADD A, B
Subtraction (SUB) Subtract contents of one register from another. SUB A, B
Increment (INC) Add 1 to the operand. INC A
Decrement (DEC) Subtract 1 from the operand. DEC B
Multiply (MUL/IMUL) Multiply two operands. MUL B
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Example in Action: Instruction ADD A, B — the CPU adds contents of A and B, stores result in A.
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[Link] Instructions: Purpose: Perform bitwise logical operations for decision-making or data manipulation.
Operation Description Examples
AND Bitwise AND between operands. AND A, B
OR Bitwise OR operation. OR A, B
XOR Bitwise exclusive OR operation. XOR A, B
NOT/COMPLEMENT Inverts all bits in operand. NOT A
Test (TEST) Perform AND operation but do not store result (used for checking flags). TEST A, B
Example in Action: Instruction AND A, B — the CPU performs a bitwise AND of A and B, stores result in A.
[Link] (Branching or Jump) Instructions: Purpose: Alter the sequence of program execution used for looping, conditional branching, and subroutine control.
Operation Description Examples
Jump (JMP) Unconditional transfer to another address. JMP 2050H
Conditional Jump (JZ, JNZ, JC, JNC) Transfer control if a certain flag condition is met. JZ 3050H
Call (CALL) Jump to a subroutine (procedure). CALL 4000H
Return (RET) Return from a subroutine. RET
Interrupt (INT) Call an interrupt service routine. INT 21H
Example in Action: Instruction JZ LABEL — if the Zero flag = 1, the CPU jumps to LABEL, else continues sequentially.
[Link] and Test Instructions: Purpose: Compare data values or test bit conditions to set CPU status flags.
Operation Description Examples
Compare (CMP) Subtract operands to set flags, without changing operands. CMP A, B
Test (TEST) Perform bitwise AND to set flags. TEST A, 01H
Example in Action: CMP A, B — if A == B → Zero flag set; if A < B → Carry flag set; if A > B → Carry cleared.

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[Link] and Rotate Instructions: Purpose: Shift or rotate bits in a register or memory location for logical or arithmetic operations.
Operation Description Examples
Shift Left (SHL/SAL) Shift bits left (multiply by 2). SHL A, 1
Shift Right (SHR/SAR) Shift bits right (divide by 2). SHR B, 1
Rotate Left (ROL) Rotate bits left through carry flag. ROL A
Rotate Right (ROR) Rotate bits right through carry flag. ROR A
Example in Action: SHL A, 1 shifts bits in A left by one position — doubles the value.
[Link]/Output Instructions: Purpose: Facilitate communication between CPU and peripheral devices.
Operation Description Examples
IN Read data from an input port. IN 00H
OUT Send data to an output port. OUT 01H
Example in Action: IN 01H — CPU reads data from device connected to port address 01H.
[Link] and Subroutine Control Instructions: Purpose: Manage subroutines and stack memory (used for temporary storage of data and return addresses).
Operation Description Examples
PUSH Store register contents on stack. PUSH A
POP Retrieve data from stack to register. POP A
CALL Transfer control to a subroutine. CALL 2000H
RET Return from subroutine. RET
Example in Action: PUSH A saves the contents of A onto the stack memory.
[Link] Control Instructions: Purpose: Control overall system operation, power management, or interrupt handling.
NOP No operation; CPU does nothing for one cycle. NOP
HLT Stop CPU execution until reset or interrupt. HLT
DI / EI Disable or enable interrupts. DI, EI
RESET
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Example in Action: HLT halts CPU execution until an interrupt or reset signal occurs.
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[Link]/Output Operations
Input devices send data to memory or CPU. Output devices display processed results. I/O operations may be programmed, interrupt-driven, or DMA-based.
Input/Output (I/O) operations are vital processes that enable a computer system to communicate with external devices such as keyboards, mice, printers, displays, and
storage devices. These operations are responsible for transferring data between the CPU, memory, and peripheral devices, ensuring that input data can be
processed and output results can be delivered. Input/Output Operations are mechanisms and procedures by which a computer system receives data (input) from
external sources and sends data (output) to external devices. They form a bridge between the computer’s internal components (CPU, memory) and the external
environment. Basic Components of I/O Operations: CPU (Central Processing Unit): Controls and coordinates data transfer between memory and I/O devices.
Memory: Stores data temporarily during transfer amid a processor and peripheral devices. I/O Modules (Controllers): Act as intermediaries amid the CPU/memory
and peripheral devices. They handle device-specific operations such as data buffering, control signal generation, and status reporting. Peripheral Devices: External
devices such as keyboards, mice, printers, disks, and monitors that provide input or receive output.
[Link] in an I/O Operation
[Link] Initiates I/O Request: The CPU issues a command to an I/O controller to perform an operation (read/write). 2.I/O Device Performs the Task: The controller
translates CPU commands into device-specific actions. [Link] Transfer: Data is transferred between the device and memory (either directly or through the CPU).
[Link] Notification: The I/O controller signals the CPU that the operation is complete, often using an interrupt.
[Link] of I/O Operations
A. Programmed I/O (Polling): The CPU continuously checks the device status to see if it is ready to send/receive data. Simple but inefficient — the CPU is busy
waiting for I/O completion. Steps: CPU issues an I/O command. CPU polls the device until it is ready. Data is transferred. CPU resumes other tasks. Used in: Simple
embedded systems or low-speed devices.
B. Interrupt-Driven I/O: The device sends an interrupt signal to the CPU when it is ready for data transfer. The CPU can perform other tasks until interrupted.
Steps: [Link] issues I/O command and continues executing other instructions. [Link] signals interrupt when ready. [Link] temporarily suspends current task to
handle I/O via an interrupt service routine (ISR). Advantages: Efficient CPU utilization. Faster response to I/O readiness.

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[Link] Memory Access (DMA): Allows data transfer directly between memory and I/O devices, bypassing the CPU after initialization. Steps: CPU sets up the
DMA controller with memory address and byte count. DMA controller transfers data directly between device and memory. CPU is interrupted only after the transfer
completes. Advantages: Reduces CPU overhead. Increases data throughput for high-speed devices (e.g., disk drives).
5.I/O Addressing Methods
[Link]-Mapped I/O: I/O devices share the same address space as memory. CPU uses regular memory instructions (LOAD/STORE) for I/O.
[Link] I/O (Port-Mapped I/O): Separate address space for I/O devices. Special instructions (IN, OUT) are used for I/O operations.
6.I/O Control Techniques
Synchronous I/O: CPU waits for I/O completion before proceeding. Asynchronous I/O: CPU continues execution and is later informed when I/O is complete.
Buffered I/O: Data is temporarily stored in a buffer to handle speed differences between CPU and devices.
[Link] and Multiprogramming
Interrupts: Signals the CPU to briefly stop current execution to service an urgent task. Multiprogramming: Allows many programs to run concurrently by managing
CPU and memory efficiently. Interrupts and multiprogramming are two vital concepts in computer organization and operating systems that enhance CPU efficiency,
responsiveness, and system throughput. They allow a computer to perform many tasks well and handle external or internal events without wasting processing time.
[Link]: Definition and Concept
An interrupt is a signal sent to a CPU that briefly halts the current execution so that the processor can attend to an urgent task or event. After handling the interrupt, the
CPU resumes the earlier task from where it was interrupted. Interrupts are mechanisms that allow the CPU to respond quickly to important or time-critical events.
[Link] of Interrupts: Interrupts can be classified in several ways:
A. Based on Source
Type Description Example
Hardware Interrupt Generated by external devices to signal the CPU. Keyboard press, Mouse click, Printer ready
Software Interrupt Generated intentionally by software or a program instruction. System calls, exceptions (e.g., divide by zero)
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B. Based on Functionality
Type Description Example
Maskable Interrupt (IRQ) Can be enabled or disabled by software. Peripheral interrupts (timer, I/O device)
Non-Maskable Interrupt (NMI) Cannot be disabled; used for critical events. Hardware failure, Power failure
Internal Interrupt (Trap/Exception) Generated by CPU during instruction execution. Arithmetic overflow, Invalid opcode
C. Based on Priority
Vectored Interrupt Control is transferred to a specific address or vector associated with that interrupt.
Non-Vectored Interrupt Address of interrupt service routine (ISR) must be supplied externally or by software.
[Link] Handling Process: When an interrupt occurs, the CPU follows a sequence known as the Interrupt Cycle:
[Link] Signal Detection – CPU detects an interrupt request. [Link] Current Instruction – CPU completes the current instruction before servicing the
interrupt. [Link] Current Context – Contents of the CPU registers and program counter (PC) are stored. [Link] Control to ISR – CPU jumps to the Interrupt
Service Routine (ISR) address. [Link] ISR – The interrupt is handled (e.g., input is read, output is sent). [Link] Context – CPU restores saved register and PC
values. [Link] Normal Execution – Execution resumes from where it was interrupted.
[Link] of Interrupts
Increases efficiency: CPU doesn’t waste time polling devices. Improves responsiveness: Handles urgent events immediately. Supports multitasking: Many
devices or programs can signal the CPU. Facilitates error handling: Responds to faults like division by zero or invalid memory access.
[Link]: Definition and Concept
Multiprogramming is a method that allows multiple programs (jobs) to be loaded into memory and executed concurrently by the CPU. However, the CPU executes only
one program at a time, switching rapidly between programs to maximize utilization. When one program is waiting for I/O, another program uses the CPU.
[Link] Principle of Multiprogramming
[Link] programs are stored in main memory at once. [Link] executes one program, but when it encounters an I/O operation (e.g., reading from disk), it switches to
another program that is ready for execution. [Link] Operating System scheduler decides which job to run next based on priorities and availability. [Link] process
continues so that the CPU is never idle.
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[Link] of Interrupts in Multiprogramming: Interrupts are the backbone of multiprogramming, enabling the CPU to switch between jobs efficiently.
Action Interrupt Role
Job Switching When a running program waits for I/O, an interrupt allows another program to run.
I/O Completion Device sends an interrupt to signal that I/O operation has finished.
Time Sharing Timer interrupts ensure fair CPU time distribution among programs.
System Calls Software interrupts allow programs to request OS services.
[Link] of Multiprogramming
[Link] CPU Utilization: No idle CPU time during I/O waits. [Link] Throughput: Multiple programs progress simultaneously. [Link] Waiting Time : Users
experience shorter response times. [Link] System Reliability: If one program fails, others continue. [Link] Multiuser Environments: Multiple users can
share the same system resources.
[Link] of Multiprogramming
[Link] Operating System: Requires sophisticated scheduling and memory management. [Link] Management Overhead: Many programs compete for
memory space. [Link] and Protection Issues: One program could affect another’s data. [Link] Overhead: Frequent context switching may slightly reduce
performance.
[Link] Between Interrupts and Multiprogramming
Aspect Interrupts Multiprogramming
Purpose Handles events that require immediate attention. Allows multiple programs to share CPU efficiently.
Function Temporarily halts current process and runs ISR. Switches between processes for better CPU use.
Dependency Essential for asynchronous I/O handling. Relies on interrupts for job switching and resource management.
Result Fast response to events. Maximized CPU and resource utilization.

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[Link] and Retrieval Concepts

Storage and retrieval are vital processes in computer organization that define how data is stored, accessed, and managed within a computer system. They determine
how efficiently the system can save information (storage) and access it when needed (retrieval) — essential for processing speed, reliability, and performance.
[Link] of Storage and Retrieval
Storage: The process of saving or recording data and instructions in a computer system for immediate or future use. It involves writing data to memory or secondary
storage devices. Retrieval: The process of accessing or reading stored data from memory or storage devices when it is required for processing or display. Together,
storage and retrieval ensure that data and instructions are available for execution, manipulation, or reference by the CPU and other components.
2. Levels of Storage in a Computer System
Storage in a computer is organized in a hierarchical structure, known as the Memory Hierarchy, based on speed, cost, and capacity.
Level Type of Storage Speed Cost Capacity Volatility
Level 1 Registers Fastest Highest Smallest Volatile
Level 2 Cache Memory Very Fast High Small Volatile
Level 3 Main Memory (RAM) Fast Moderate Medium Volatile
Level 4 Secondary Storage (Hard Drive, SSD) Moderate Low Large Non-volatile
Level 5 Tertiary/Off-line Storage (CD, USB, Cloud, Tape) Slow Lowest Very Large Non-volatile
[Link] Devices
A. Primary Storage: Also known as main memory. Used by the CPU to store data and instructions temporarily during execution. Examples: RAM (Random Access
Memory) – Volatile; data lost when power is off. ROM (Read Only Memory) – Non-volatile; stores firmware and system boot instructions. B. Secondary Storage: Used
for long-term data storage. Non-volatile and large in capacity. Examples: Hard Disk Drives (HDD), Solid-State Drives (SSD). C. Tertiary and Off-line Storage: Used
for backup, archiving, and external data transfer. Examples: USB Flash Drives, Optical Discs (CD/DVD), Cloud Storage, Magnetic Tapes. 4. Data Storage Process
[Link]: Data is converted into a binary format (0s and 1s) that the computer can understand. [Link]: Each memory location is assigned a unique address
for data storage and retrieval. [Link]: The CPU issues a write command to store the binary data in a memory cell. [Link]: The system checks if the data
was correctly written to memory.
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[Link] Retrieval Process

[Link] Specification: The CPU provides the address of the memory location where the required data is stored. [Link] Command: A read request is sent to
memory to fetch the data. [Link] Transfer: Data is transferred from the memory cell to the CPU or requesting device. [Link]: The retrieved data is processed,
displayed, or used for computation.
[Link] and Retrieval in Different Storage Types
Storage Type Storage Mechanism Retrieval Mechanism Example
RAM Data stored in addressable memory cells. CPU reads from specific address locations. Program execution data.
Hard Disk Data stored magnetically in sectors and tracks. Disk head reads data blocks from the platter. File storage.
Optical Disc (CD/DVD) Data encoded using pits and lands on disc surface. Laser beam reads reflections to retrieve bits. Movies, software.
SSD Data stored in flash memory cells. Controller retrieves data electronically from blocks. Modern laptops.
Cloud Storage Data stored on remote servers. Retrieved through network protocols. Google Drive, OneDrive.
[Link] Access Methods
Access Type Description Examples
Sequential Access Data accessed in a linear sequence. Magnetic tape
Direct Access (Random Access) Data accessed directly by specifying its address. Hard disks, RAM
Indexed Access Uses an index table to locate data. Databases
Associative Access Data retrieved based on content, not address. Cache memory
[Link] Organization for Storage and Retrieval: Data can be organized in various structures to facilitate efficient retrieval:
[Link] and Records: Data stored in file systems as records. [Link]: Structured format using tables, rows, and columns. [Link]: Used to speed up retrieval
operations. [Link] and Caches: Briefly store frequently used data for faster access. [Link] and Pages: Physical units of data storage on secondary devices.

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[Link] Factors in Storage and Retrieval

[Link] Time: The time taken to locate and retrieve data. [Link] Rate: The speed at which data can be read or written. [Link]: The delay before data
transfer begins. [Link]: The ability of storage to preserve data without corruption. [Link] Integrity: Ensuring accuracy and consistency of stored and retrieved
data. [Link] and Backup: Storing duplicate copies for fault tolerance and disaster recovery.
10. Techniques for Efficient Storage and Retrieval
[Link]: Briefly stores frequently accessed data for faster retrieval. [Link]: Balances speed differences between CPU and I/O devices. [Link]:
Reduces data size to save storage space. [Link]: Uses lookup tables to access data faster. [Link] (Redundant Array of Independent Disks): Combines
multiple disks to improve speed and reliability. [Link] Allocation Table (FAT) / NTFS: File system structures that organize how files are stored and retrieved.
Example Scenario
When you open a document: [Link] Operating System locates the file in secondary storage (HDD/SSD). [Link] file allocation table (FAT) identifies the file’s location
(block numbers). [Link] controller retrieves data blocks into RAM. [Link] CPU processes the data and displays it on the screen. [Link] changes are later written back to
storage during a write-back operation.

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Thank you
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