RISC-V CPU Presentation Script
Presentation Script (Easy English)
RISC-V Single Cycle CPU
Target duration: ~10 minutes | Simple sentences, easy to memorize
Tip: Read each line slowly. Short sentences are easier to remember and pronounce.
Slide 1 — Title Slide (15 sec)
Good morning everyone.
My name is Dang Trieu Dang Khoa.
I study at the University of Science, student ID 23207069.
Today I will present my project: a 32-bit RISC-V CPU, single-cycle design, built in Verilog.
Slide 2 — Agenda (20 sec)
"Here is an agenda for my talk. My presentation has 8 parts, starting with the introduction and
motivation, followed by the system architecture, module breakdown, and supported instruction
sets. Finally, I will show you my simulation results, something I learned, and what I will do in the
future."
Slide 3 — Introduction and Motivation (1 min 15 sec)
First — why I chose RISC-V?
It is an open and free instruction set.
Many big companies use it — Google, SiFive, NVIDIA.
It is popular because it is flexible and easy to extend.
My goal: build a working 32-bit RISC-V CPU from scratch, using Verilog.
I test it with simulation.
I also try to build it on an FPGA.
Why single-cycle design?
Because each instruction runs in just one clock cycle.
It's the easiest way to see how an instruction actually works in hardware.
It helps me check my design is correct — before I try harder designs like pipelining.
Tools I used:
Verilog for hardware design.
Quartus Prime for synthesis.
Intel Cyclone V as the target chip.
ModelSim for simulation.
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RISC-V CPU Presentation Script
Slide 4 — System Architecture (1 min)
This is my system architecture.
It has two main parts: the Controller and the Datapath.
My design has 12 Verilog modules.
processor.v is the top module. It connects the Controller and the Datapath.
data_path.v creates all the datapath sub-modules.
Some key modules:
IFU and instruction memory — for fetching instructions.
Register file and immediate generator — for reading registers and decoding values.
ALU and branch comparator — for calculation and branch checking.
Data memory and multiplexers — for writing data back.
Slide 5 — Controller Unit (1 min)
"The Controller Unit decodes the opcode and other instruction fields, and creates a table of
control signals for each instruction group — R-type, I-type, Load, Store, Branch, JAL, and JALR.
For example, with an R-type instruction, the opcode is [...]. The Controller will generate control
signals like [...], and so on."
Slide 6 — Datapath Design (1 min)
The Datapath is responsible for moving and processing data.
The Controller tells it what to do.
Let me walk you through the data flow, step by step.
First, the PC sends an address to Instruction Memory.
The Controller Unit decodes the instruction.
At the same time, the Register File reads two values, in parallel.
Then, the ALU calculates the result — or a memory address.
If it's a Load or Store instruction, Data Memory is accessed.
A multiplexer selects the final result.
That result is written back to the Register File.
All of this happens in just one clock cycle.
PC → Instruction Memory → Controller Unit giải mã // Register File đọc song song → ALU
tính toán / địa chỉ → Data Memory (Load/Store) → chọn kết quả qua Mux → ghi lại Register
File — toàn bộ trong 1 chu kỳ clock.
Four key modules:
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RISC-V CPU Presentation Script
IFU — fetches instructions, holds the PC register.
Register File — 32 general-purpose registers.
Immediate Generator — creates immediate values for I, S, B, J type instructions.
Data Memory — reads and writes data.
The diagram shows the data flow:
Fetch instruction from PC.
Read source registers.
Calculate in the ALU.
Write the result back to a register or memory.
Slide 7 — Instruction Set Coverage (45 sec)
My design supports 29 instructions.
They cover 5 instruction types from RV32I — the base RISC-V instruction set.
I realized I'm still missing the U-type instructions.
I plan to add them in a future version.
Slide 8 — Testbench & Verification (1 min)
"With each module, I built a separate testbench, and all of them passed in ModelSim.
I verified each module by applying test inputs, and checking the outputs on the waveform.
For example, I checked if the ALU gives the correct result. I checked if the register file reads and
writes correctly. I checked if the PC jumps to the right address.
This shows that each module works correctly, before I connect them together.
It also proves that my full CPU design behaves exactly as expected — instruction by instruction,
cycle by cycle."
Slide 9 — Simulation Result (1 min 15 sec)
"Here is a real simulation. It runs an 11-instruction program.
Let me walk you through the PC flow.
First, it runs step by step — addi, sw, lw.
Then, at 0x000C, we have beq x1, x2, +8. The condition is true.
So the PC skips one instruction — the add instruction.
It jumps to 0x0014, and continues with the sub instruction.
It keeps running step by step — through 0x0018.
Then, at 0x001C, we have JAL x4, +8.
The PC jumps to 0x0024. It saves the return address into register x4.
Then, at 0x0028, we have JALR x7, x4, 0.
The PC jumps back to 0x0020 — exactly the address saved in x4.
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RISC-V CPU Presentation Script
Address 0x0020 is a NOP, so it's skipped.
The PC falls through to 0x0024 — and the program loops back here.
The waveform on the right shows the signals and register values.
Everything matches my design.
This confirms the CPU works correctly."
Slide 10 — Lessons Learned and Future Work (1 min)
I learned three main things from this project.
First, I understand the RV32I architecture better.
Second, I improved my Verilog RTL design skills.
Third, I learned how to verify hardware — using simulation and debugging.
For future work, I plan to:
Upgrade this design into a 5-stage pipeline CPU.
Add hazard detection and forwarding units.
Deploy the design on a real FPGA.
Support more RISC-V instruction extensions.
Slide 11 — Thank You (10 sec)
Thank you for listening.
I am happy to answer any questions.
Tips to Practice
Read each sentence out loud, one at a time. Don't rush.
Practice the hard words first: Verilog, opcode, multiplexer, pipeline, FPGA, ModelSim.
If you forget a sentence, just look at the slide — the slide already has the key words.
Practice 3 times fully, out loud, before the real presentation.
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