• Design for Testability (DFT) is a methodology in
VLSI design that simplifies the testing of integrated circuits.
• It involves adding test features during the design phase
to effectively detect manufacturing defects.
• DFT enhances the controllability and observability
of internal nodes, enabling easier fault detection.
• It helps identify whether a circuit is faulty or fault-free,
while reducing testing cost and time.
THE STAGES OF DFT:
>SCAN
>SCAN COMPRESSION
>ATPG
>SIMULATION
• The circuit consists of combinational logic
and flip-flops (FFs) connected in a chain
• Multiplexers are used to switch between
normal mode and test (scan) mode
• In scan mode, flip-flops act as a shift register
(scan chain)
• Test data is shifted in through Scan In (SI)
and shifted out through Scan Out (SO)
• The Scan Enable (SE) signal controls the
mode of operation
• This structure improves controllability and
observability for testing
Your Design
s2c_chiptop
DFT ATPG
2660 Flip-Flops | DFT Insertion | EDT (98% FC | Modus | Cadence
2660 2 97% 15
Total Flip-Flops Clock Domains Test Coverage Scan Chains
Scan Insertion Flow
Read Library & HDL Synthesize
1 read_libs / read_hdl / elaborate
5 syn_generic → syn_map → syn_opt
Configure DFT Insert Scan Chain
2 set_db dft_scan_style muxed_scan
6 define_scan_chain / connect_scan_chains
Define Clocks & Resets Write Outputs
3 define_dft test_clock / define_test_signal
7 write_hdl / write_sdc / write_scandef
Check DFT Rules
4 check_dft_rules
Violations Encountered
ASYNC Violation 0 — 1 Register — s2c_chiptop
Root: pin:.../g1767__5115/Y
Cause: chiptop_reset not defined as test signal
Fix: define_test_signal -name chiptop_reset -function async_set_reset -active low comparater_reset
ASYNC Violation 1 — 2660 Registers — s2c_chiptop
Root: pin:.../g774__6260/Y
Cause: Not defined as test signal
Fix: define_test_signal -name counter_reset -function async_set_reset -active low counter_reset
How You Fixed Them
BEFORE (Commented Out)
#define_dft test_clock counter_clock
-period 1000
#define_dft test_clock comparater_clock
-period 1000
#define_test_signal -name chiptop_reset
-function async_set_reset
-active low reset
#define_test_signal -name chiptop_reset
-function async_set_reset
-active low reset
AFTER (Uncommented)
define_dft test_clock _clock
-period 1000
define_dft test_clock r_clock
-period 1000
define_test_signal -name _reset
-function async_set_reset
-active low _reset
define_test_signal -name _reset
-function async_set_reset
-active low r_reset
>>report_scan_chains
Final Results
Scan Chain SDI Port
✓ top_chain
✓ scan_in
SDO Port Scan Enable
✓ scan_out
✓ SE (active high)
FFs in Chain Violations
✓ 2660 total
✓ 0 (all resolved)
Output Files Generated
write_hdl | write_sdc | write_sdf | write_dft_atpg | write_scandef
Decompressor
Compactor
ATE
Embedded Deterministic Test (EDT) is a DFT technique
used to reduce scan test time and data volume by
compressing test patterns
EDT significantly reduces the number of external scan
channels needed for testing. It operates by converting the
tester input channels to a larger number of internal scan
chains using a decompressor and a phase shifter.
[Link] reduces test time.
[Link] reduces the test data volume.
[Link] reduces chip-level pins.
[Link] reduces ATE memory requirements.
• One of the challenges of working with test patterns is that they often contain many random values
(X). These values can take up a lot of memory space and slow down the performance of the testing.
• To overcome this problem, we can use a compression technique that eliminates these “X” values
and reduces memory usage.
• Compression occurs by reducing the amount of data per test pattern & not by reducing the number
of test patterns generated.
• Compression ratio = No. Of Scan chains / No. of Scan channels
• Test Time = #Patterns * #Shift_cycles * #Time period
• It is a process of generating test patterns for a given
fault model (SA, TDF, BF, IDDQ)
• During ATPG, test patterns will be generated. These test
patterns will be used to test the chip after manufacturing.
After manufacturing, if suppose there are any defects,
these test patterns should have the capability to detect
most of the manufacturing defects.
• How are we sure that, our test patterns will be able to
detect most of the manufacturing defects ? It is because
our tool does fault simulation to generate the test patterns.
• During ATPG, the design is provided to the ATPG tool. The
ATPG tool keeps this design (good machine) and creates
another design by injecting all possible faults into it (faulty
machine).
• The tool generates patterns for good machine and keeps that
as expected response (good value).
• Then the tool applies patterns for faulty machine and tries to
see whether the pattern detects the fault.
• If good value is not the same as faulty value the fault is
detected and vice versa.
• Based on the result of fault simulation, the tool categorizes
the faults into various classes.