Approximate MAC Unit Using Static Segmentation

Abstract – Line-by-Line Explanation (Simple English)

Original Line:

In this paper we investigate a novel approximate multiply-and-accumulate (MAC) unit, that

computes Y = A × B + C using static segmentation.

Explanation:
The authors propose a new Approximate MAC (Multiply-Accumulate) unit. A MAC performs:

Y=A\times B+C

Instead of calculating the exact result, it uses a technique called static segmentation to simplify the
hardware and save power.

Original Line:

The proposed architecture uses a unique carry-propagate adder and performs segmentation on
the three operands A, B, and C, to reduce hardware cost.

Explanation:
The proposed design uses only one carry-propagate adder (CPA) instead of multiple adders.

It divides all three inputs:

 A (multiplier input)

 B (multiplier input)

 C (accumulator input)

into smaller segments and processes only the important parts.

Benefits:

 Less hardware area

 Lower power consumption

 Simpler circuit design

Original Line:

The circuit can be configured at design-time by two parameters.

Explanation:
Before manufacturing or implementing the circuit, the designer can adjust two settings
(parameters) to control the trade-off between:

 Accuracy

 Power consumption
  Area

Original Line:

The first one controls the segmentation on A and B, while the second one controls the
segmentation on C and the adder length.

Explanation:

Two parameters are used:

Parameter 1: m

Controls how much of inputs A and B are used.

 Larger m → higher accuracy

 Smaller m → lower power

Parameter 2: mC

Controls:

 Segmentation of input C

 Size of the adder

Smaller adder size means:

 Less area

 Less power consumption

Original Line:

An error compensation technique is also employed, to reduce the approximation error.

Explanation:

Because some bits are discarded during segmentation, errors occur.

To reduce these errors, the authors add a special error compensation circuit that estimates part of
the lost information and adds it back.

Result:

 Better accuracy

 Very small extra hardware cost

Original Line:

Error analysis and implementation results in 28nm CMOS for 8-bits multiplier with 20-bits and 24-
bits addition are presented.
Explanation:

The proposed MAC was tested using:

 28 nm CMOS technology

 8-bit multiplier

 20-bit accumulator

 24-bit accumulator

The authors measured:

 Error

 Area

 Power

 Delay

to evaluate performance.

Original Line:

The proposed approximate MACs outperform the state of the art, showing the largest power
saving when the mean relative error distance (MRED) is larger than 2 × 10−3 and 4 × 10−5 for 20
and 24-bits addition, respectively.

Explanation:

The new design was compared with previous approximate MAC circuits.

The proposed MAC achieved better results, especially when:

For 20-bit addition

MRED > 0.002

For 24-bit addition

MRED > 0.00004

This means that when a small amount of error is acceptable, the proposed MAC saves more power
than existing designs.

Original Line:

For MRED of about 6 × 10−3 the proposed approximate MAC with 20-bits addition exhibits a power
reduction larger than 60% compared to the exact MAC and larger than 27% compared to the state-
of-the-art approximate MACs.

Explanation:

For an error level of:

MRED ≈ 0.006

the proposed MAC achieved:

Compared with Exact MAC

 More than 60% power saving

Compared with Previous Approximate MACs

 More than 27% additional power saving

This is one of the most important results of the paper.

Original Line:

Application examples to image filtering and template matching show that proposed approximate
circuits are good candidates in applications where their error performances are acceptable.

Explanation:

The authors tested the MAC in real applications:

1. Image Filtering

Used in:

 Cameras

 Image enhancement

 Noise removal

2. Template Matching

Used in:

 Object detection

 Pattern recognition

 Computer vision

Even though the MAC is approximate, the output quality remained good.

Therefore, the design is suitable for applications where small errors do not significantly affect the
final result.

Index Terms Explanation

Approximate methods

 Techniques that intentionally allow small errors to save power and area.

Arithmetic and logic structures

 Digital circuits such as adders, multipliers, and MAC units.

Hardware architecture

 The overall design structure of the circuit.

Low-power design

 Designing circuits that consume less energy.

VLSI

 Very Large Scale Integration, the process of designing integrated circuits with millions of
transistors.

Abstract Summary in One Sentence

The paper introduces a Static Segmented Approximate MAC (SSMAC) that segments inputs A, B,
and C, uses only one carry-propagate adder, applies error compensation, and achieves up to 60%
power reduction while maintaining acceptable accuracy for image-processing applications.

Line-by-Line Explanation (Simple English)

Original Line:

The multiply-and-accumulate unit (MAC) implements the equation Y = A × B + C

Explanation:

A MAC (Multiply-Accumulate) unit performs two operations:

1. Multiply A and B

2. Add C to the multiplication result

Mathematically:

Y=A\times B+C

Example:

A=4

B=5

C=3

Y = (4 × 5) + 3

Y = 20 + 3

Y = 23

A MAC combines multiplication and addition into a single hardware block.

Original Line:
and has a central role in several applications, including image and audio processing [1], [2],
convolutional neural networks, and adaptive filtering [3], [4], [5].

Explanation:

MAC units are used very frequently in digital systems.

Examples:

Image Processing

 Image filtering

 Edge detection

 Noise removal

Audio Processing

 Sound filtering

 Speech processing

Convolutional Neural Networks (CNNs)

 Artificial Intelligence

 Image recognition

 Face detection

Adaptive Filters

 Echo cancellation

 Noise cancellation

Since these applications perform millions of multiply-add operations, MAC units are very
important.

Original Line:

This calls for optimized MAC implementations with reduced power and area.

Explanation:

Because MAC units are used so often, engineers want them to be:

 Faster

 Smaller

 Lower power

Goals:

Less Area

+
Less Power

High Speed

This is especially important for:

 Mobile phones

 AI chips

 Battery-powered devices

Original Line:

A MAC is usually realized by adding the row corresponding to the input C to the partial product
matrix (PPM) of the product A × B

Explanation:

When multiplying A and B, hardware first generates many partial products.

Example:

A = 1010

B = 1100

Partial products are generated:

1010

1010

0000

0000

This arrangement is called the:

Partial Product Matrix (PPM)

Instead of calculating:

(A × B)

and then later adding C,

the value C is inserted directly into the partial product matrix.

So the hardware performs:

A×B+C

in one combined operation.

This saves hardware resources.

Original Line:

to employ a unique carry-propagate adder for the computation of Y.

Explanation:

Normally:

Multiplier

Adder

Output

may require multiple adders.

Instead, designers combine everything so that only one Carry Propagate Adder (CPA) is used.

What is a Carry Propagate Adder?

An adder where the carry travels from one bit to the next.

Example:

1111

+ 0001

------

10000

The carry propagates through all bits.

Using only one CPA:

✅ Reduces area

✅ Reduces power

✅ Improves efficiency

Original Line:

For error-resilient applications, further improvements in terms of power, area, and delay can be
achieved by resorting to approximate computing

Explanation:

Some applications can tolerate small errors.

Examples:
Can tolerate small errors

 Images

 Videos

 AI inference

 Machine learning

Human eyes usually cannot notice tiny errors.

Therefore designers intentionally allow a small amount of error.

This technique is called:

Approximate Computing

Idea:

Small Error

Much Less Hardware

Less Power

Higher Speed

So instead of computing the exact answer every time, an approximate answer is produced that is
very close to the exact one.

The benefit is:

 Lower power consumption

 Smaller chip area

 Faster operation

Paragraph Summary

This paragraph says that:

1. A MAC computes Y = A × B + C.

2. MAC units are widely used in image processing, audio processing, CNNs, and adaptive
filters.

3. Since MACs are used millions of times, designers try to reduce their power and area.

4. Traditional MACs insert C directly into the Partial Product Matrix (PPM) so only one carry-
propagate adder is required.
 5. For applications that can tolerate small errors, Approximate Computing can further reduce
power, area, and delay.

Line-by-Line Explanation (Simple English)

Original Line:

achieved by resorting to approximate computing, a recent design paradigm aimed at improving the
hardware performance by intentionally introducing approximations into the design [6], [7], [8], [9].

Explanation:

To further reduce:

 Power consumption

 Chip area

 Delay (computation time)

engineers use a technique called Approximate Computing.

What is Approximate Computing?

Instead of always calculating the exact answer, the circuit allows a small error in the result.

Example:

Exact Result = 100

Approximate Result = 99

The error is very small, but the hardware becomes:

✅ Smaller

✅ Faster

✅ Lower power

This is useful in applications like:

 Image processing

 Video processing

 Artificial Intelligence

where tiny errors are usually not noticeable.

Original Line:

In literature, several efforts have been spent for investigating approximate multipliers.

Explanation:

Many researchers have studied different types of approximate multipliers.

The goal is:

Less Accuracy

Less Hardware

Less Power

Many designs have already been proposed before this paper.

Original Line:

Recursive multipliers, obtained by assembling approximate 2 × 2 or 4 × 4 sub-multipliers, are

reported in [10], [11].

Explanation:

One method is called a Recursive Multiplier.

Instead of building one large multiplier directly:

8 × 8 Multiplier

it is built using smaller blocks:

2 × 2 Multipliers

or

4 × 4 Multipliers

Example:

8×8 Multiplier

┌────┴────┐

4×4 4×4

│ │

2×2 2×2

If the small blocks are approximate, the whole multiplier becomes approximate and consumes less
power.

Original Line:

Approximate compressors to sum the PPM are studied in [12], [13], [14], [15]

Explanation:
During multiplication, many partial products are generated.

These form the:

Partial Product Matrix (PPM)

Example:

a0b0

a0b1 a1b0

a0b2 a1b1 a2b0

...

These bits must be added together.

Special circuits called compressors perform this addition.

Examples:

 3:2 Compressor

 4:2 Compressor

Researchers designed approximate compressors that:

 Ignore some less important bits

 Simplify logic

Benefits:

✅ Smaller area

✅ Lower power

❌ Small error

Original Line:

while logarithmic multipliers are investigated in [16], [17].

Explanation:

Another approach is called a Logarithmic Multiplier.

Normally:

A×B

requires complex multiplication hardware.

Using logarithms:

log(A × B)

=
log(A) + log(B)

So multiplication becomes addition.

Process:

A → log(A)

B → log(B)

Add logs

Convert back

Since addition is simpler than multiplication:

 Hardware becomes smaller

 Power decreases

But some approximation error is introduced.

Original Line:

The Static Segmented Multipliers (SSMs), described in [18], [19], show remarkably good power
reduction.

Explanation:

Among all approximate multipliers, the authors highlight:

Static Segmented Multiplier (SSM)

This multiplier is the foundation of the proposed MAC.

The previous research showed that SSM provides:

 Very low power consumption

 Small hardware area

 Acceptable accuracy

Therefore the authors chose SSM as the starting point for their new MAC design.

Original Line:

The SSMs extract a segment of m contiguous bits from each of the two n-bits operands (m < n)

Explanation:

Suppose:
A = 8 bits

B = 8 bits

Instead of using all 8 bits, SSM uses only:

m bits

where:

m<n

Example:

n=8

m=5

Input:

A = 10110110

Only a 5-bit segment is selected:

10110

The remaining bits are ignored.

This reduces hardware complexity.

Original Line:

use a small m × m multiplier for the two segments

Explanation:

Instead of using a large:

8 × 8 multiplier

the SSM uses a smaller:

5 × 5 multiplier

Example:

n=8

m=5

Traditional:

8×8

Proposed:

5×5

A smaller multiplier means:

  Fewer logic gates

 Less area

 Less power

Original Line:

and a left-shift to obtain the result.

Explanation:

Because only part of the original number is multiplied, the result must be placed back in its correct
position.

This is done using a left shift.

Example:

Suppose:

Segment Result = 1010

Shift left by 3 positions:

1010 << 3

1010000

This approximates the position of the discarded bits.

The final output becomes close to the actual multiplication result.

Paragraph Summary

This paragraph explains previous approximate multiplier techniques:

Technique Main Idea

Recursive Multiplier Build large multiplier using approximate 2×2 or 4×4 blocks

Approximate Compressor Simplify addition of partial products

Logarithmic Multiplier Convert multiplication into addition using logarithms

Static Segmented Multiplier (SSM) Use only m important bits and a small m×m multiplier

The paper focuses on Static Segmented Multipliers (SSMs) because they provide excellent power
savings with acceptable accuracy, making them a good choice for designing an approximate MAC.

Line-by-Line Explanation (Simple English)

Original Line:

The study of approximate MACs has received less interest in the scientific literature.

Explanation:

Many researchers have worked on:

 Approximate multipliers

 Approximate adders

But fewer researchers have focused on:

Approximate MAC (Multiply-Accumulate) Units

So, compared to multipliers, the number of research papers on approximate MACs is relatively
small.

Original Line:

An approximate MAC can be obtained simply by cascading a multiplier and an adder, and by
appropriately approximating one (or both) blocks.

Explanation:

The easiest way to build an approximate MAC is:

Approximate Multiplier

Approximate Adder

Output

or

Approximate Multiplier

Exact Adder

or

Exact Multiplier

Approximate Adder

The word cascading means connecting one circuit after another.

Since one or both blocks are approximate, the overall MAC also becomes approximate.

Benefits:
✅ Lower power

✅ Smaller area

❌ Some error in output

Original Line:

Better performance can be obtained by using customized approximate MACs

Explanation:

Instead of simply connecting an approximate multiplier and an approximate adder, researchers can
design a special MAC architecture from scratch.

Such a MAC is called:

Customized Approximate MAC

These designs are optimized specifically for MAC operations.

Advantages:

 Lower power consumption

 Smaller area

 Better speed

 Better accuracy-power tradeoff

Therefore, customized MACs usually perform better than simple cascaded designs.

Original Line:

as the one presented in [20] (using approximate counters)

Explanation:

Reference [20] proposes a MAC that uses:

Approximate Counters

What is a Counter?

In multiplier hardware, many bits from the partial product matrix (PPM) must be added together.

Counters help compress these bits.

Example:

5 input bits

Counter
 ↓

Sum + Carry

In [20], the counters are simplified (approximate).

Result:

✅ Less hardware

✅ Less power

❌ Small computation error

Original Line:

[21] (based on recursive approach)

Explanation:

Reference [21] uses a:

Recursive MAC Architecture

Recursive Means:

A large MAC is built from smaller MAC blocks.

Example:

Large MAC

┌──┴──┐

Small Small

MAC MAC

Similarly:

8×8 MAC

4×4 MACs

2×2 MACs

These smaller blocks may be approximate.

Advantages:

✅ Lower complexity

✅ Reduced power
✅ Easier design

Original Line:

and [22] (using a cascade of an approximate multiplier and a modified approximate adder with
opposite mean error).

Explanation:

Reference [22] uses:

Approximate Multiplier

Modified Approximate Adder

But there is a special idea.

Mean Error

Suppose:

Approximate multiplier usually produces:

Exact Result = 100

Approx Result = 98

Error = -2

It tends to underestimate.

Now the approximate adder is designed to produce:

Exact Result = 50

Approx Result = 52

Error = +2

It tends to overestimate.

So:

Multiplier Error = -2

Adder Error = +2

Total Error:

-2 + 2 = 0

The errors partially cancel each other.

This is why the paper says:

"opposite mean error"

The adder and multiplier are designed so that one compensates for the other's error.

Result:

✅ Better accuracy

✅ Still lower power than exact MAC

Paragraph Summary

The authors explain that:

1. Approximate MACs have been studied less than approximate multipliers.

2. A simple approximate MAC can be built by connecting an approximate multiplier and

adder.

3. Better results are achieved using specially designed MAC architectures.

4. Previous works include:

o [20]: MAC using approximate counters.

o [21]: Recursive MAC architecture.

o [22]: Approximate multiplier + modified approximate adder with opposite errors.

These are the main state-of-the-art approximate MAC designs that the proposed SSMAC is
compared against later in the paper.

Fig. 1: Segmentation for the Input A — Line-by-Line Explanation

This figure explains how the input A is divided into two parts in the Static Segmented Multiplier
(SSM).

Figure Explanation

Assume:

n = 8 bits

A = a7 a6 a5 a4 a3 a2 a1 a0

For example:

A = 10110110

The 8-bit input is divided into two segments.

Upper Segment: HA
HA = a7 a6 a5 a4

This contains the Most Significant Bits (MSBs).

For the example:

HA = 1011

The paper calls this:

HA (m MSBs)

because it contains m bits.

Lower Segment: LA

LA = a3 a2 a1 a0

This contains the Least Significant Bits (LSBs).

For the example:

LA = 0110

The paper calls this:

LA (m LSBs)

εA (Discarded Region)

Between HA and LA there may be some bits that are discarded.

These discarded bits are represented by:

εA

They are not used in the multiplication.

This helps reduce hardware complexity.

Paragraph Explanation

Original Line

The paper is organized as follows.

Explanation

The authors are explaining the structure of the paper.

Original Line

Section II briefly recalls the architecture of the static segmented multiplier.

Explanation

Section II reviews the previously proposed:

Static Segmented Multiplier (SSM)

which is the basic building block used in the new MAC design.

Original Line

Section III describes the proposed SSMAC, with segmentation extended to the addend C.

Explanation

Section III explains the new contribution.

Unlike previous SSMs that segment only:

A and B

the proposed SSMAC also segments:

This further reduces hardware.

Original Line

The results in terms of error metrics and hardware performance are reported in Section IV.

Explanation

Section IV presents:

Error Metrics

 NMED

 MRED

 PRED

 NmaxED

and hardware results such as:

 Power

 Area

 Delay

Original Line

while some applications for image filtering are reported in Section V.

Explanation

Section V shows practical applications.

The authors test the SSMAC in:

 Image filtering

 Image processing tasks

to verify that image quality remains acceptable.

Section II – Static Segment Multiplier

Original Line

The SSM described in [18], [19] employs an m × m multiplier for realizing an n × n product, with
n/2 ≤ m < n.

Explanation

Normally:

n-bit × n-bit

requires:

n × n multiplier

Example:

8 × 8 multiplier

The SSM instead uses a smaller:

m × m multiplier

Example:

5 × 5 multiplier

where:

n/2 ≤ m < n

For:

n=8

possible values are:

m = 4, 5, 6, 7

Smaller multiplier means:

✅ Less area

✅ Less power
Original Line

Let us consider the operand A.

Explanation

The authors now explain how one input, A, is segmented.

The same procedure is later applied to B.

Original Line

The signal is segmented in a lower portion (LA), comprising its m least significant bits (LSBs)

Explanation

The lower segment is:

LA

It contains:

m Least Significant Bits

Mathematically:

LA = A[m−1 : 0]

Example:

A = 10110110

m=5

LA = 10110

Original Line

and an upper portion (HA), comprising its m most significant bits (MSBs)

Explanation

The upper segment is:

HA

It contains:

m Most Significant Bits

Mathematically:

HA = A[n−1 : n−m]
Example:

A = 10110110

m=5

HA = 10110

Equation (1)

The paper defines:

L_A=A[m-1:0]

Meaning:

Take the lowest m bits.

And:

H_A=A[n-1

Meaning:

Take the highest m bits.

Original Line

The Fig. 1 shows an example for n = 8, m = 5.

Explanation

Example settings:

Input size n = 8 bits

Segment size m = 5 bits

So only 5-bit segments are used for multiplication.

Original Line

When the (n−m) MSBs of A are low, LA is selected for the multiplication.

Explanation

The circuit checks the upper bits.

If all upper bits are:

000
(for n=8, m=5)

then:

LA is used

because most of the useful information is already in the lower part.

Original Line

Otherwise, HA is chosen at the cost of an accuracy loss

Explanation

If any upper bit is:

then:

HA is selected

This may cause some error because the lower bits are ignored.

But it greatly reduces hardware cost.

Original Line

since the least significant part εA is discarded

Explanation

When HA is selected:

εA

(the discarded lower portion)

is removed completely.

Example:

A = 10110110

Selected HA = 10110

Discarded εA = 110

This discarded information creates approximation error.

Original Line
Let us define αA as the OR of the (n−m) MSBs of A

Explanation

The paper creates a control signal:

αA

It is generated by ORing the upper bits.

Example:

Upper bits = 000

Then:

αA = 0

Example:

Upper bits = 101

Then:

αA = 1

Original Line

and let us name Assm the segmented input

Explanation

The selected segment is called:

Assm

It is the actual value sent to the small multiplier.

Original Line

Assm = LA if αA = 0 and Assm = HA if αA = 1

Explanation

Selection rule:

If αA = 0

Assm = LA

If αA = 1

Assm = HA

This is exactly what the multiplexer does in the hardware.

Main Idea of Fig. 1

Input A (n bits)

┌─────┴─────┐

│ │

HA (MSBs) LA (LSBs)

│ │

└─────┬─────┘

Control αA

Select One Segment

Small m×m Multiplier

The key idea is:

Instead of multiplying all n bits, SSM selects only one m-bit segment (HA or LA), multiplies it using
a smaller multiplier, and later shifts the result to approximate the original multiplication. This
saves significant power and area at the cost of a small error.

Line-by-Line Explanation (Simple English)

This section explains how the Static Segmented Multiplier (SSM) works mathematically and how it
is extended to form the SSMAC.

Line 1

The Fig. 1 shows an example for n = 8, m = 5.

Explanation

The authors consider:

Input size (n) = 8 bits

Segment size (m) = 5 bits

Example:

A = a7 a6 a5 a4 a3 a2 a1 a0

Only a 5-bit segment will be used for multiplication.

Line 2

When the (n−m) MSBs of A are low, LA is selected for the multiplication.

Explanation

For:

n=8

m=5

we have:

n−m=3

The circuit checks:

a7 a6 a5

If:

a7 a6 a5 = 000

then:

LA is selected

because the number is small and most information is already in the lower bits.

Line 3

Otherwise, HA is chosen at the cost of an accuracy loss.

Explanation

If any of the upper bits is 1:

a7 a6 a5 ≠ 000

then:

HA is selected

Example:

A = 10110110

Upper bits:

101

Therefore:

HA is selected

Line 4
(since the least significant part εA is discarded, see Fig. 1).

Explanation

When HA is selected:

A = 10110110

Use:

HA = 10110

Discard:

εA = 110

Discarding bits causes approximation error.

Line 5

Let us define αA as the OR of the (n−m) MSBs of A

Explanation

The control signal αA is generated by ORing the upper bits.

Example 1:

Upper bits = 000

αA = 0 OR 0 OR 0

αA = 0

Example 2:

Upper bits = 101

αA = 1 OR 0 OR 1

αA = 1

Line 6

and let us name Assm the segmented input

Explanation

The selected segment is called:

Assm

This is the value actually sent to the small multiplier.

Line 7

(Assm = LA if αA = 0 and Assm = HA if αA = 1).

Explanation

Selection rule:

If αA = 0

Assm = LA

If αA = 1

Assm = HA

This is implemented using a multiplexer.

Equation (2)

The paper states:

A\approx A_{ssm}\cdot 2^{K_A}

Explanation

The original number A is approximated by:

Selected Segment × Shift Factor

where:

Assm

is either HA or LA.

Definition of KA

The paper defines:

KA = 0 if αA = 0

KA = n − m if αA = 1

Case 1

If:

αA = 0

then:

A ≈ Assm × 2^0

Since:
2^0 = 1

No shifting is needed.

Case 2

If:

αA = 1

then:

A ≈ Assm × 2^(n−m)

For:

n=8

m=5

n−m = 3

Therefore:

A ≈ Assm × 2^3

which means:

Left shift by 3 bits

Line 8

where an approximation error occurs when αA = 1, due to discarding εA.

Explanation

Error occurs only when:

αA = 1

because some lower bits are removed.

Example:

A = 10110110

Approximation:

Use only HA

Discarded bits:

εA = 110

This causes error.

Line 9

A similar segmentation is applied to B

Explanation

Exactly the same process is used for:

The circuit generates:

Bssm

αB

KB

just like A.

Equation (3)

The paper writes:

P_{SSM}=A\times B\approx (A_{ssm}2^{K_A})\times(B_{ssm}2^{K_B})

Explanation

Replace A and B with their segmented versions.

Then:

P_{SSM}=A_{ssm}\times B_{ssm}\times 2^{K_S}

Explanation

Instead of:

8×8 multiplier

the circuit performs:

5×5 multiplier

and then shifts the result.

This greatly reduces hardware.

Equation (4)

The shift amount KS is:

KS = 0

if (αA,αB)=00
Meaning

Both operands use lower segments.

No shift required.

KS = n−m

if (αA,αB)=01 or 10

Meaning

One operand uses HA and the other uses LA.

Shift by:

n−m

bits.

KS = 2(n−m)

if (αA,αB)=11

Meaning

Both operands use HA.

Shift twice.

Example:

n=8

m=5

KS=2×3=6

Shift left by 6 bits.

Line 10

The (3) clearly shows that the SSM requires only a small m × m multiplier

Explanation

Instead of using:

8×8 multiplier

the SSM uses:

5×5 multiplier
or any m×m multiplier.

This reduces:

 Area

 Power

 Delay

Line 11

to compute the inner product Assm × Bssm.

Explanation

The small multiplier calculates only:

Assm × Bssm

which is much simpler than multiplying the complete operands.

Line 12

The SSM implementation is reported in the dashed box of Fig. 2(a).

Explanation

The hardware block implementing this SSM is shown in Figure 2(a) of the paper.

Extending SSM to MAC

Line 13

To obtain a multiplier-accumulator we can simply add the operand C to the output of the SSM, as
follows:

Explanation

To convert the multiplier into a MAC:

Simply add C.

Equation (5)

Y_{SSMAC}=(A_{ssm}\times B_{ssm}\cdot 2^{K_S})+C

Explanation

The output of the SSM is added with C.

Thus:
Approximate Product

gives the MAC result.

Line 14

Note that the word length of C is nC ≥ 2n

Explanation

C is usually larger than A and B.

Example:

A = 8 bits

B = 8 bits

Product:

16 bits

Therefore:

C ≥ 16 bits

The paper uses:

20-bit C

24-bit C

Line 15

since in most applications the multiply-accumulate unit is used sequentially to accumulate the
output of several multiplications.

Explanation

A MAC usually works repeatedly:

Y1 = A1×B1 + C

Y2 = A2×B2 + Y1

Y3 = A3×B3 + Y2

The accumulated value keeps growing.

Therefore C must have more bits than A and B to avoid overflow.

Key Idea of This Page

Input A ──► Segmentation ──► Assm

Input B ──► Segmentation ──► Bssm

Small m×m

Multiplier

Shift KS

+C

SSMAC Output

The main contribution here is showing how a large n×n multiplication can be approximated using a
small m×m multiplier plus shifting, and then extended into a MAC operation by adding operand C.

Line-by-Line Explanation (Simple English)

This section explains why the simple SSMAC design is inefficient and how the authors improve it
using a single adder architecture.

Original Line

The implementation of the above equation is shown in Fig. 2(a).

Explanation

The MAC equation from Equation (5):

Y_{SSMAC}=(A_{ssm}\times B_{ssm}\cdot 2^{K_S})+C

is implemented in Figure 2(a).

Figure 2(a) shows the basic (naive) SSMAC architecture.

Original Line

The left-shift needed to calculate PSSM does not allow to merge the final adder with the inner m ×
m multiplier Assm × Bssm.
Explanation

To obtain the approximate product, the SSM performs:

Small Multiplication

Left Shift

The shift operation occurs after multiplication.

Because of this shift, the multiplier and the final addition with C cannot be combined into one
hardware block.

So the architecture becomes:

Multiplier

Shift

Adder

instead of a single fused unit.

Original Line

Therefore, two cascaded carry-propagate adders are required

Explanation

Because the operations cannot be merged:

Adder 1

Adder 2

are needed.

This is called:

Cascaded Carry-Propagate Adders

"Cascaded" means connected one after another.

Problem:

❌ More area

❌ More power

❌ More delay
Original Line

a first 2m-bits adder is used to compute Assm × Bssm

Explanation

The first adder belongs to the multiplier section.

Example:

m=5

Then:

2m = 10

So a:

10-bit adder

is needed to combine partial products and generate:

Assm × Bssm

Original Line

while a second nC-bits adder sums the operand C.

Explanation

After multiplication:

(Assm × Bssm) × 2KS

must be added to:

using another adder.

If:

nC = 20

then a:

20-bit adder

is required.

Therefore:

Multiplier

10-bit Adder
 ↓

Shift

20-bit Adder

Two adders are needed.

Section III: Proposed Static Segmented MAC

Original Line

The presence of the two adders in cascade negatively affects the performance of the circuit in Fig.
2(a).

Explanation

Having:

Adder 1

Adder 2

causes:

Higher Power

More switching activity.

Larger Area

More logic gates.

Higher Delay

Signal must pass through two adders.

Thus performance becomes worse.

Original Line

To solve this problem, we rewrite (5) as follows:

Explanation

Instead of computing Equation (5) directly, the authors mathematically rearrange it.

This is the key innovation of the paper.

Equation (6)

The paper rewrites the equation as:

Y_{SSMAC}=(A_{ssm}\times B_{ssm}+C\cdot2^{-K_S})\cdot2^{K_S}

Explanation of Equation (6)

Originally:

Product → Shift → Add C

Now:

Shift C Right

Add inside multiplier

Final Shift

This changes the order of operations.

Original Line

According to (6), we right-shift the input C, before left shifting the product Assm × Bssm.

Explanation

Instead of shifting the multiplication result first,

the authors shift:

to the right.

Example:

C = 100000

Right shift by 2:

100000 >> 2

001000

Now C can participate directly in the multiplication structure.

Original Line
This allows to eliminate the multiplexer between multiplier and adder

Explanation

In the previous design:

Multiplier

MUX

Adder

A multiplexer was required.

Using Equation (6):

Multiplier + Adder

can be merged.

Therefore the multiplexer is removed.

Benefits:

✅ Less area

✅ Less power

Original Line

and to merge the term C · 2−KS in the PPM of the multiplier.

Explanation

PPM means:

Partial Product Matrix

Normally:

Partial Products

Adder

Now the shifted version of C:

C × 2−KS

is inserted directly into the Partial Product Matrix.

So multiplication and addition happen together.

Original Line

The Fig. 2(b) shows the architecture that implements (6)

Explanation

Figure 2(b) shows the improved hardware architecture based on Equation (6).

This is the actual proposed SSMAC architecture.

Original Line

highlighting in red the differences with respect to the MAC of Fig. 2(a).

Explanation

The red-colored blocks in Figure 2(b) indicate:

 Newly added hardware

 Modified hardware

compared with Figure 2(a).

Original Line

The two OR-gates compute the flags αA and αB

Explanation

The circuit checks A and B.

Two OR gates generate:

αA

αB

These indicate whether:

HA or LA

should be selected.

Example:

Upper bits = 000

αA = 0

Upper bits = 101

αA = 1

Original Line
that in turn program two 2-1 multiplexers used to segment A and B.

Explanation

The control signals:

αA

αB

control two multiplexers.

Each multiplexer selects:

HA

or

LA

for multiplication.

Original Line

A third multiplexer, marked in red in the figure, applies the right-shift on C

Explanation

An additional multiplexer is introduced.

Its job:

Shift C

according to the required value of KS.

Original Line

choosing between the portions C[nC−1:0], C[nC−1:n−m], and C[nC−1:2(n−m)].

Explanation

Depending on KS, the multiplexer selects different portions of C.

Case 1

No shift:

C[nC−1:0]

Entire C is used.

Case 2

Shift by:
n−m

Use:

C[nC−1:n−m]

Case 3

Shift by:

2(n−m)

Use:

C[nC−1:2(n−m)]

Original Line

The multiplexer on the output rearranges the result

Explanation

After computation, another multiplexer restores the result to its correct bit position.

This performs the equivalent of the final left shift.

Original Line

Thus, the architecture in Fig. 2(b) allows to merge the inner multiplication and the final sum in a
fused MAC structure

Explanation

This is the main achievement.

Instead of:

Multiplier

Adder

the design becomes:

Multiplier + Adder

inside a single structure.

This is called a:

Fused MAC

Benefits:
✅ Less hardware

✅ Lower power

✅ Faster operation

Original Line

requiring a unique nC-bits adder.

Explanation

The new design needs only:

One nC-bit Adder

instead of:

One 2m-bit Adder

One nC-bit Adder

This significantly reduces hardware complexity.

Original Line

There is a small overhead due to the introduction of the multiplexer on C input

Explanation

A new multiplexer is added to process C.

This slightly increases hardware.

Original Line

but this overhead is more than compensated by the elimination of the 2m-bits adder required in
Fig. 2(a).

Explanation

Although one extra multiplexer is added:

+ Small MUX

the design removes:

− Large 2m-bit Adder

The removed adder is much larger than the added multiplexer.

Therefore:
Total Area ↓

Total Power ↓

Total Delay ↓

Main Idea of This Section

Old Design (Fig. 2a)

Small Multiplier

2m-bit Adder

Shift

nC-bit Adder

Two adders → Higher power and area

Proposed Design (Fig. 2b)

Segment A

Segment B

Shifted C

Fused MAC

Single nC-bit Adder

One adder only → Lower power, smaller area, and better performance.

A. Segmentation of the Addend C — Line-by-Line Explanation

This section introduces the second major innovation of the paper:

👉 Not only are A and B segmented, but the addend C is also segmented.

This further reduces the size of the adder and lowers power consumption.

Original Line
As observed before, the architecture in Fig. 2(b), while more effective compared to Fig. 2(a),
requires an nC-bits adder to compute the output.

Explanation

The improved MAC architecture of Fig. 2(b) uses only one adder.

However, that adder must still process the entire operand C.

Example:

A = 8 bits

B = 8 bits

C = 20 bits

Therefore a:

20-bit adder

is still required.

Large adders consume:

 More power

 More area

 More delay

Original Line

We can reduce the adder length by segmenting also the input C.

Explanation

The authors propose:

Segment A ✓

Segment B ✓

Segment C ✓

Instead of processing all bits of C, only a selected portion is used.

This allows:

Smaller Adder

Less Area

Less Power
Original Line

By following an approach like Fig. 1, we subdivide the input C in a lower portion (LC) and an upper
portion (HC)

Explanation

Just like A and B were divided into:

HA and LA

the input C is divided into:

HC = High Portion

LC = Low Portion

Structure:

┌──────┴──────┐

│ │

HC (MSBs) LC (LSBs)

Original Line

which comprises mC bits, with nC/2 ≤ mC < nC

Explanation

The segment size is:

mC

and must satisfy:

nC/2 ≤ mC < nC

Example:

nC = 20

Possible values:

mC = 10,11,12,...19

So at least half the bits of C are kept.

Equation (7)

The paper defines:

L_C=C[m_C-1:0]

Explanation

LC contains:

mC least significant bits

Example:

C = 10110010101100101100

mC = 12

LC:

001011001100

And:

H_C=C[n_C-1

Explanation

HC contains:

mC most significant bits

Example:

101100101011

Original Line

Thus, the proposed static-segmented MAC (SSMAC) can be configured at design time with two
parameters

Explanation

The designer can tune the MAC using two parameters.

This allows balancing:

Accuracy

Area

Power

according to system requirements.

Original Line
m that controls the segmentation of A and B

Explanation

Parameter:

controls:

A segmentation

B segmentation

Example:

m=4

Very small multiplier.

Lower power but larger error.

Original Line

and mC that controls the segmentation of C.

Explanation

Parameter:

mC

controls:

C segmentation

Adder size

Smaller mC:

Lower Power

More Error

Larger mC:

Higher Accuracy

More Hardware

Original Line

In the following we will assume mC ≥ 2m.

Explanation

The authors impose a design constraint:

mC ≥ 2m

Example:

m=5

Then:

mC ≥ 10

This ensures the adder remains large enough to accommodate the multiplication result.

Original Line

Let us name αC the OR of the (nC−mC) MSBs of C

Explanation

A control signal:

αC

is generated.

It is computed by ORing the upper:

(nC−mC)

bits.

Example

Suppose:

C = 00000010101100101100

Upper bits:

00000000

Then:

αC = 0

Another example:

C = 10110010101100101100

Upper bits contain 1.

Therefore:

αC = 1
Original Line

and let us define Cssm the segmented input C

Explanation

The selected segment of C is named:

Cssm

This is the actual portion of C used in the MAC computation.

Original Line

(Cssm = LC if αC = 0 and Cssm = HC if αC = 1).

Explanation

Selection rule:

Case 1

αC = 0

Select:

Cssm = LC

Case 2

αC = 1

Select:

Cssm = HC

Equation (8)

The paper approximates C as:

C\approx C_{ssm}\cdot 2^{K_C}

Explanation

Just like A and B, the original value of C is approximated using:

Selected Segment

Shift Factor

KC Definition
The paper defines:

KC = 0

if αC = 0

Meaning:

Use LC directly

No shift.

And:

KC = nC−mC

if αC = 1

Meaning:

Use HC

and shift it back to its original position.

Example

Suppose:

nC = 20

mC = 14

Then:

KC = 20−14

=6

Therefore:

C ≈ Cssm × 2^6

which means:

Left Shift by 6 bits

Equation (9)

The final SSMAC equation becomes:

Y_{SSMAC}=(A_{ssm}\times B_{ssm}+C_{ssm}\cdot 2^{K_C-K_S})\cdot2^{K_S}

Explanation of Equation (9)

Originally:

A×B+C

was approximated using segmented A and B.

Now:

A → Assm

B → Bssm

C → Cssm

All three operands are segmented.

The MAC computes:

Small Multiplication

Segmented C

and finally performs the required shifting.

Why This Is Important

Previous Architecture

Segment A

Segment B

Full C

Required:

Large nC-bit Adder

Proposed Architecture

Segment A

Segment B

Segment C

Required:

Smaller Adder

Main Contribution of This Section

The authors extend the static segmentation technique from A and B to C as well.
This introduces a new design parameter mC, allowing the designer to trade:

Accuracy

Power

Area

As a result, the SSMAC becomes even more power-efficient and area-efficient than the previous
segmented MAC architecture.

Fig. 2 Explanation (Line by Line)

Figure 2 compares:

Fig. 2(a)

Conventional SSMAC
(Static Segmented Multiplier + Separate Adder)

Fig. 2(b)

Proposed SSMAC
(Fused Multiplier-Accumulator using only one adder)

The red blocks in Fig. 2(b) show the new modifications introduced by the authors.

Fig. 2(a): Conventional SSMAC

Top Left: Input A Segmentation

A[n−1:n−m]

A[m−1:0]

These are:

HA = Upper m bits

LA = Lower m bits

Example:

A = 10110110

m=5

HA = 10110

LA = 10110
OR Gate (αA)

The OR gate examines:

A[n−1:n−m]

and generates:

αA

Purpose

Determine which segment should be selected.

αA = 0 → Select LA

αA = 1 → Select HA

2:1 Multiplexer for A

Inputs:

0 → LA

1 → HA

Control:

αA

Output:

Assm

This is the segmented version of A.

Input B Segmentation

Exactly the same operation is performed on B.

Generate:

αB

Select:

Bssm

m × m Multiplier

The circle marked:

×
computes:

A_{ssm}\times B_{ssm}

Since:

Assm = m bits

Bssm = m bits

Output size:

2m bits

Example:

m=5

5×5 multiplier

instead of:

8×8 multiplier

Power saving occurs here.

Shifting Logic

The multiplier output is shifted according to:

KS

generated from:

αA

αB

Cases

αA αB = 00

KS = 0

No shift.

αA αB = 01 or 10

KS = n−m

Shift left by:

n−m bits
αA αB = 11

KS = 2(n−m)

Shift twice.

Output PSSM

After shifting:

PSSM

Approximate multiplication result.

Final Adder

The bottom adder performs:

Y_{SSMAC}=P_{SSM}+C

Problem

Two additions are needed:

1. Inside multiplier

2. Final addition with C

Therefore:

Two Carry Propagate Adders

are required.

This increases:

❌ Area

❌ Power

❌ Delay

Fig. 2(b): Proposed SSMAC

Now look at the right figure.

The red blocks are the new contributions.

Input A Segmentation

Same as Fig. 2(a).

Produces:
Assm

Input B Segmentation

Same as Fig. 2(a).

Produces:

Bssm

Small Multiplier

Computes:

A_{ssm}\times B_{ssm}

Again only:

m×m multiplier

is required.

Red Adder Block

This is the most important modification.

Instead of:

Multiplier

Adder

the multiplication result and C are combined directly.

The architecture performs:

A_{ssm}\times B_{ssm}+C\cdot2^{-K_S}

inside the same structure.

Red Multiplexer for C

This is a newly added multiplexer.

Inputs:

C[nC−1:0]

C[nC−1:n−m]

C[nC−1:2(n−m)]
Why?

Depending on:

αA

αB

different shifts are required.

Instead of shifting the multiplier result,

the circuit selects an already shifted portion of C.

Control Cases

αA αB = 00

Use:

C[nC−1:0]

No shift.

αA αB = 01 or 10

Use:

C[nC−1:n−m]

Equivalent to:

C >> (n−m)

αA αB = 11

Use:

C[nC−1:2(n−m)]

Equivalent to:

C >> 2(n−m)

Single nC-bit Adder

The adder now performs:

Y_{MAC}=A_{ssm}\times B_{ssm}+C\cdot2^{-K_S}

Only one carry-propagate adder is needed.

This is the main innovation.

Output Rearrangement Multiplexer

Bottom multiplexer restores the correct bit position.

Control:

αA αB

Cases:

00

01

10

11

Function

Equivalent to performing:

Left Shift by KS

after computation.

Produces final:

YSSMAC

Why Fig. 2(b) is Better

Feature Fig. 2(a) Fig. 2(b)

Multiplier m×m m×m

Adder Count 2 1

Multiplexer on C No Yes

Area Larger Smaller

Power Higher Lower

Delay Higher Lower

Main Idea of Figure 2

Fig. 2(a)
Segment A

Segment B

m×m Multiplier

Shift

Adder with C

Requires:

Two Carry Propagate Adders

Fig. 2(b)

Segment A

Segment B

Shifted C

Fused MAC

Single Adder

Output Rearrangement

Requires:

Only One Carry Propagate Adder

This reduction of one adder is the key reason the proposed SSMAC achieves lower power
consumption, lower area, and better efficiency than previous MAC architectures.

Line-by-Line Explanation (Simple English)

This section explains how the authors further reduce the adder size by approximating Equation (9).

Original Line

The word length of the product Assm × Bssm is 2m bits, and the word length of Cssm is mC.

Explanation
The multiplier inputs are:

Assm = m bits

Bssm = m bits

Therefore:

Assm × Bssm

produces:

2m bits

Example:

m=5

Then:

5 × 5 multiplication

gives:

10-bit result

Similarly:

Cssm

contains:

mC bits

Example:

mC = 14

Then:

Cssm = 14 bits

Original Line

Unfortunately, due to the term 2KC−KS (that can imply a left or a right shift of Cssm), we cannot
use a simple mC-bits adder to compute the output in (9).

Explanation

Equation (9) is:

Y_{SSMAC}=(A_{ssm}B_{ssm}+C_{ssm}2^{K_C-K_S})2^{K_S}

Notice:

2^(KC−KS)

Sometimes:
KC−KS > 0

which means:

Left Shift

Sometimes:

KC−KS < 0

which means:

Right Shift

Because the position of bits changes, a simple fixed-size adder cannot always be used.

Original Line

We thus consider the various cases that can occur in (9), depending on the values of αC, αB, αA.

Explanation

The output depends on:

αA

αB

αC

These control signals decide:

 HA or LA

 HB or LB

 HC or LC

Therefore different cases must be analyzed separately.

Case 1

Original Line

When (αC, αB, αA) = 000, we have KS = KC = 0

Explanation

This is the simplest case.

Since:

αA = 0

αB = 0

αC = 0
the circuit selects:

LA

LB

LC

No shifting is required.

Therefore:

KS = 0

KC = 0

Equation (10)

The paper obtains:

Y_{SSMAC}=A_{ssm}B_{ssm}+C_{ssm}

Explanation

Substituting:

KS = 0

KC = 0

into Equation (9):

2^(KC−KS)=2^0=1

So the equation becomes:

Multiplier Result

Cssm

which is very simple.

Original Line

where Assm = LA, Bssm = LB and Cssm = LC.

Explanation

Because all α values are zero:

Assm = LA

Bssm = LB

Cssm = LC
Only lower segments are used.

Original Line

The last equation requires a mC-bits adder, as desired.

Explanation

Now the largest operand is:

Cssm

which contains:

mC bits

Therefore only an:

mC-bit adder

is needed.

This is exactly what the authors wanted.

Benefits:

✅ Smaller hardware

✅ Less power

Remaining Cases

Original Line

In the other cases, we perform some additional approximations by truncating some of the terms in
(9)

Explanation

When:

αA = 1

or

αB = 1

or

αC = 1

shifts occur.

The exact computation becomes more complex.

To keep the adder small, the authors deliberately discard some bits.
This process is called:

Truncation

Example:

101101.1101

truncate:

101101

Some accuracy is lost.

Original Line

these approximations are different depending on the sign of KC−KS.

Explanation

The approximation method depends on whether:

KC−KS

is:

Positive

KC−KS > 0

or

Negative

KC−KS < 0

because shifts behave differently in each case.

Original Line

To fix ideas, let us assume: (nC−mC) ≥ 2(n−m)

Explanation

The authors introduce a design condition:

nC−mC ≥ 2(n−m)

This simplifies the mathematical analysis.

Example:

nC = 20

mC = 14
20−14 = 6

If:

n=8

m=5

2(n−m)=6

Condition is satisfied.

Original Line

so that KC−KS is negative only when KC = 0 and KS ≠ 0.

Explanation

Under the above condition:

The only time:

KC−KS < 0

occurs is:

KC = 0

and

KS > 0

This greatly simplifies the case analysis.

Positive Shift Case

Original Line

Let us consider the case in which KC−KS is positive, that is KC−KS > 0.

Explanation

Now the authors analyze:

KC > KS

This means:

Cssm

must be shifted left.

Original Line
We have in this case αC = 1, independently on the values of αA and αB.

Explanation

If:

KC−KS > 0

then:

αC = 1

must be true.

Therefore:

HC

is selected.

Original Line

We rewrite (9) as follows

Explanation

The equation is rearranged into a more convenient form.

Equation (11)

Y_{SSMAC}=(A_{ssm}B_{ssm}2^{-(K_C-K_S)}+C_{ssm})2^{K_C}

Explanation

The shift factor is moved from:

Cssm

to:

Assm × Bssm

This makes the hardware implementation easier.

Original Line

We approximate this equation by truncating the term Assm × Bssm × 2−(KC−KS).

Explanation

The multiplier result is shifted right:

Assm × Bssm

>>
(KC−KS)

Some least significant bits disappear.

Instead of computing them exactly, the authors simply remove them.

This reduces hardware complexity.

Equation (12)

Y_{SSMAC}\approx(\lfloor A_{ssm}B_{ssm}2^{-(K_C-K_S)}\rfloor+C_{ssm})2^{K_C}

Explanation

The symbol:

⌊⌋

is the floor operator.

Meaning:

Remove fractional bits

Example:

13.75

becomes:

13

This truncation is another approximation introduced by the authors.

Original Line

having indicated as [·] the floor operator.

Explanation

The notation:

[x]

used in the paper means:

Floor(x)

or:

Integer Part

Original Line

Let us assume, for the sake of simplicity, that KC−KS is even.

Explanation

To simplify the mathematical derivation, the authors assume:

KC−KS

is an even number.

Example:

This assumption makes the next equations easier to derive.

Main Idea of This Section

The authors want to use only a small mC-bit adder.

To achieve this:

1. They analyze different combinations of αA, αB, αC.

2. They rewrite Equation (9).

3. They shift and truncate some terms.

4. They intentionally discard less important bits.

Result:

Smaller Adder

Lower Power

Lower Area

Small Additional Error

This is the key approximation technique that enables the final low-power SSMAC architecture.

Line-by-Line Explanation (Simple English)

This section explains how the authors simplify Equation (12) so that the hardware implementation
becomes easier and requires a smaller adder.

Equation (11)
The paper starts with:

Y_{SSMAC}=(A_{ssm}\times B_{ssm}2^{-(K_C-K_S)}+C_{ssm})\cdot2^{K_C}

Explanation

Previously, the shift was applied to Cssm.

Now the shift is moved to the multiplication term:

Assm × Bssm

This makes the hardware easier to implement.

Original Line

We approximate this equation by truncating the term Assm × Bssm 2−(KC−KS).

Explanation

The term:

Assm × Bssm × 2^-(KC−KS)

means:

Assm × Bssm

is shifted right.

Example:

11010110

Right shift by 2:

00110101

The two least significant bits are lost.

Instead of keeping these bits, the authors simply discard them.

This process is called:

Truncation

Benefit:

✅ Simpler hardware

✅ Less area

✅ Less power

Drawback:

❌ Small error
Equation (12)

The paper writes:

Y_{SSMAC}\approx(\lfloor A_{ssm}B_{ssm}2^{-(K_C-K_S)}\rfloor+C_{ssm})\cdot2^{K_C}

Explanation

The symbol:

⌊x⌋

means:

Floor Operation

Keep only the integer part.

Example:

15.75

becomes

15

The fractional part is discarded.

In hardware, this means dropping some least significant bits after shifting.

Original Line

having indicated as [·] the floor operator.

Explanation

The authors use:

[x]

to represent:

⌊x⌋

which means:

Take Integer Part Only

or

Discard Fractional Bits

Original Line

Let us assume, for the sake of simplicity, that KC−KS is even.

Explanation
To make the mathematical derivation easier, the authors assume:

KC−KS

is an even number.

Examples:

This assumption allows the shift amount to be divided equally between Assm and Bssm.

Original Line

The (12) can be rewritten as follows:

Explanation

Instead of shifting the entire multiplication result:

Assm × Bssm

the authors distribute the shift equally between:

Assm

and

Bssm

This leads to Equation (13).

Equation (13)

Y_{SSMAC}\approx(A'{ssm}\times B'{ssm}+C_{ssm})\cdot2^{K_C}

Explanation

Now the multiplication is performed using:

A'ssm

and

B'ssm

instead of the original:

Assm

Bssm
This simplifies the implementation.

The structure becomes:

Reduced Assm

Reduced Bssm

Cssm

followed by:

Left Shift by KC

Why is Equation (13) Useful?

Instead of:

Multiply

Large Shift

Adder

the circuit becomes:

Pre-scaled Assm

Pre-scaled Bssm

Multiplier

Adder

This reduces hardware complexity.

Equation (14)

The paper defines:

A'{ssm}=\left\lfloor A{ssm}\cdot2^{-(K_C-K_S)/2}\right\rfloor

Explanation

To create:
A'ssm

the original:

Assm

is shifted right by:

(KC−KS)/2

and truncated.

Example

Suppose:

Assm = 100110

KC−KS = 4

Then:

(KC−KS)/2 = 2

Right shift by 2:

100110 >> 2

001001

Therefore:

A'ssm = 001001

The paper also defines:

B'{ssm}=\left\lfloor B{ssm}\cdot2^{-(K_C-K_S)/2}\right\rfloor

Explanation

Exactly the same operation is performed on:

Bssm

Example

Suppose:

Bssm = 111000

Right shift by 2:

111000 >> 2
=

001110

Therefore:

B'ssm = 001110

Why Split the Shift Between A and B?

Without this trick:

Assm × Bssm

must be multiplied first and then shifted.

With this trick:

Shift Assm

Shift Bssm

Multiply Smaller Numbers

This means:

Smaller Operands

Smaller Multiplier Activity

Lower Power

and simpler hardware.

Main Idea of This Section

The authors transform:

Assm × Bssm × 2^-(KC−KS)

into:

A'ssm × B'ssm

by:

1. Dividing the shift equally between A and B.

2. Truncating the discarded bits.

3. Using smaller effective operands.

Result:
Less Hardware

Lower Power

Smaller Adder

Acceptable Error

This mathematical manipulation is an important step that enables the final low-power SSMAC
architecture.

Line-by-Line Explanation (Simple English)

This section explains how Equation (13) is implemented in hardware and what happens when KC −
KS is odd.

Original Line

Thus, the approximation (13) can be implemented by truncating the (KC−KS)/2 rightmost bits of
Assm and Bssm.

Explanation

From Equation (13), the authors defined:

A'ssm = Assm × 2^(-(KC−KS)/2)

B'ssm = Bssm × 2^(-(KC−KS)/2)

Multiplying by:

2^-n

means:

Right Shift by n bits

Therefore, to obtain A'ssm and B'ssm, we simply remove the rightmost bits.

Example

Suppose:

Assm = 101101

Bssm = 110011

KC−KS = 4

Then:
(KC−KS)/2 = 2

Remove 2 rightmost bits:

Assm = 1011

Bssm = 1100

No actual shifter is needed.

Just connect fewer bits.

Benefits:

✅ Very simple hardware

✅ Lower power

✅ Smaller area

Original Line

In other words, A'ssm is simply a v-subsegment of HA or LA, and a similar observation holds for
B'ssm.

Explanation

The authors are saying:

You do not need to calculate A'ssm using extra hardware.

Instead:

A'ssm

is simply a smaller portion (sub-segment) of the already selected segment.

Example:

HA = 101101

If 2 bits are removed:

A'ssm = 1011

So:

HA

└──► A'ssm

Similarly:

LA

└──► A'ssm

depending on which segment was selected.

The same idea applies to:

B'ssm

Original Line

In the case in which KC−KS is odd, we can still use (13), but A'ssm and B'ssm will have a number of
bits that differ by one

Explanation

Previously, the authors assumed:

KC−KS = even

Example:

2, 4, 6

Now consider:

KC−KS = odd

Example:

1, 3, 5

Then:

(KC−KS)/2

is not an integer.

Example:

3/2 = 1.5

We cannot remove 1.5 bits.

Therefore:

 One operand loses 1 bit

 The other loses 2 bits

As a result:

A'ssm

and

B'ssm

have lengths differing by one bit.

Original Line
and are given by the following equation

Explanation

The authors now define exactly how many bits should be removed from A and B when the shift
amount is odd.

Equation (15)

For A:

A'{ssm}=\left\lfloor A{ssm}\cdot2^{-\lceil(K_C-K_S)/2\rceil}\right\rfloor

Explanation

For A:

Use the ceiling value.

Example

Suppose:

KC−KS = 3

Then:

(3/2) = 1.5

Ceiling:

⌈1.5⌉ = 2

Therefore:

A'ssm = Assm >> 2

Remove 2 bits.

For B:

B'{ssm}=\left\lfloor B{ssm}\cdot2^{-\lfloor(K_C-K_S)/2\rfloor}\right\rfloor

Explanation

For B:

Use the floor value.

Example:

(3/2) = 1.5

Floor:

⌊1.5⌋ = 1
Therefore:

B'ssm = Bssm >> 1

Remove 1 bit.

Original Line

where ⌈·⌉ is the ceil operator.

Explanation

The symbol:

⌈x⌉

means:

Ceiling Operator

Round upward to the nearest integer.

Examples:

⌈1.2⌉ = 2

⌈1.5⌉ = 2

⌈2.1⌉ = 3

Difference Between Floor and Ceiling

Ceiling ⌈x⌉
⌊x⌋
Floor
Value

1.2 1 2

1.5 1 2

2.8 2 3

Example for Odd KC−KS

Suppose:

KC−KS = 3

Then:

⌈3/2⌉ = 2

⌊3/2⌋ = 1

If:
Assm = 101101

Bssm = 110011

Then:

A'

Remove 2 bits:

1011

B'

Remove 1 bit:

11001

Notice:

A' length = 4 bits

B' length = 5 bits

Difference:

1 bit

which is exactly what the paper states.

Main Idea of This Section

The authors show that Equation (13) can be implemented very efficiently:

Even KC−KS

Remove equal bits from A and B

Odd KC−KS

Remove one extra bit from one operand

using:

 Floor operator

 Ceiling operator

Result:

No complex shifters

No extra arithmetic hardware

Only wire selection

This makes the proposed SSMAC architecture very hardware-efficient while maintaining
acceptable accuracy.
Line-by-Line Explanation (Simple English)

This section explains Figure 3 and the second approximation case when KC − KS is negative.

Original Line

The Fig. 3 shows an example for n = 8, m = 5 and nC = 20, mC = 14.

Explanation

The authors use the following example values:

A = 8 bits

B = 8 bits

m=5

Therefore:

Assm = 5 bits

Bssm = 5 bits

For C:

nC = 20 bits

mC = 14 bits

Only 14 bits of C will be used.

Original Line

In Fig. 3(a) the entire (exact) PPM of the multiplier-accumulator is shown.

Explanation

PPM means:

Partial Product Matrix

This is the complete multiplication and accumulation matrix.

A×B+C

without any approximation.

Figure 3(a) is the reference exact implementation.

Original Line

The Fig. 3(b) highlights the portion of PPM considered for (αC, αB, αA) = 111.

Explanation
Now consider:

αC = 1

αB = 1

αA = 1

This means:

HC selected

HB selected

HA selected

Only upper segments are used.

Figure 3(b) shows which part of the exact PPM remains after approximation.

Original Line

In this case A'ssm and B'ssm include the five most-significant bits of A and B

Explanation

Since:

αA = 1

αB = 1

the multiplier uses:

HA

HB

For:

n=8

m=5

these are:

a7 a6 a5 a4 a3

b7 b6 b5 b4 b3

The lower bits are ignored.

Original Line

therefore the bits a2..a0, b2..b0 are truncated.

Explanation
The least significant bits are discarded.

For A:

a2

a1

a0

are removed.

For B:

b2

b1

b0

are removed.

Example:

A = a7 a6 a5 a4 a3 a2 a1 a0

becomes:

A' = a7 a6 a5 a4 a3

This saves hardware but introduces approximation error.

Original Line

The segment Cssm, including the 14 most-significant bits of C, is employed

Explanation

Because:

αC = 1

the circuit selects:

HC

which contains:

14 MSBs of C

Original Line

and hence the bits c5..c0 are also truncated.

Explanation

Since:
nC = 20

mC = 14

the lower:

20 − 14 = 6 bits

are discarded.

Removed bits:

c5

c4

c3

c2

c1

c0

Only upper 14 bits remain.

Figure 3(c)

Original Line

The Fig. 3(c) shows the portion of PPM considered for (αC, αB, αA) = 101.

Explanation

Now consider:

αC = 1

αB = 0

αA = 1

Selections become:

HC

LB

HA

This is another approximation case.

Original Line

In this case A'ssm includes the three most-significant bits of A

Explanation

Due to the truncation explained earlier, only the top 3 bits of A remain.

Example:

A = a7 a6 a5 a4 a3 a2 a1 a0

becomes:

A'ssm = a7 a6 a5

Original Line

while B'ssm includes the bits b3b2b1

Explanation

For B:

B'ssm = b3 b2 b1

are retained.

Original Line

(the bit b0 is truncated)

Explanation

The least significant bit:

b0

is discarded.

This is another approximation.

Original Line

while b7b6b5 are zero since αB = 0.

Explanation

Since:

αB = 0

the lower segment:

LB

is selected.

Therefore upper bits:

b7

b6

b5

are effectively treated as:

in the computation.

Negative KC − KS Case

Original Line

Let us now consider the case in which KC−KS is negative, that is KC = 0 and KS ≠ 0.

Explanation

Now the authors analyze the opposite case.

Previously:

KC−KS > 0

Now:

KC−KS < 0

This occurs when:

KC = 0

and

KS > 0

Original Line

We are in this case when αC = 0

Explanation

If:

αC = 0

then:

Cssm = LC

and

KC = 0
Original Line

and one of αA and αB, or both, are equal to 1.

Explanation

At least one multiplier operand uses its upper segment.

Possible combinations:

αA αB

01

10

11

Thus:

KS > 0

Original Line

In these conditions, the (9) becomes:

Explanation

Substituting:

KC = 0

into Equation (9), the equation simplifies.

Equation (16)

Y_{SSMAC}=(A_{ssm}\times B_{ssm}+C_{ssm}\cdot2^{-K_S})\cdot2^{K_S}

Explanation

The segmented C must be shifted right by:

KS

before addition.

Original Line

This equation can be approximated by truncating Cssm · 2−KS as follows:

Explanation
Instead of computing:

Cssm × 2^(-KS)

exactly,

the shifted bits are simply truncated.

This reduces hardware complexity.

Equation (17)

Y_{SSMAC}\approx(A_{ssm}\times B_{ssm}+C'_{ssm})\cdot2^{K_S}

Explanation

The shifted version of C is replaced by:

C'ssm

which is a truncated version.

Now the hardware computes:

Multiplier Result

C'ssm

followed by a final shift.

Equation (18)

The paper defines:

C'{ssm}=\left\lfloor C{ssm}\cdot2^{-K_S}\right\rfloor

Explanation

To obtain:

C'ssm

the circuit:

1. Right shifts Cssm by KS bits.

2. Removes discarded fractional bits.

Example

Suppose:

Cssm = 111010101100
KS = 3

Right shift:

111010101100 >> 3

000111010101

The last 3 bits are lost.

Therefore:

C'ssm = 000111010101

Main Idea of This Section

The authors analyze the case:

KC − KS < 0

and simplify the computation by truncating the shifted value of C.

Result

Instead of:

Exact Shifted C

they use:

Truncated Shifted C

Benefits:

Smaller Adder

Lower Power

Lower Area

Simpler Hardware

with only a small increase in approximation error.

This is another key step that enables the low-power implementation of the proposed SSMAC.

This figure shows the partial-product reduction process of an 8×8 binary multiplier (typically a
Dadda or Wallace multiplier). Each symbol (a_i b_j) represents a partial product generated by an
AND gate.

(a) Initial Partial Product Matrix

 (a_i) = bit of multiplicand A.

 (b_j) = bit of multiplier B.

 (a_i b_j) = AND of the two bits.

For an 8×8 multiplication:

[
P = A \times B
]

64 partial products are generated:

[
a_0b_0,; a_0b_1,; \ldots,; a_7b_7
]

They are arranged according to their weight (column).

Example:

Column Partial Products

c₀ a₀b₀

c₁ a₁b₀, a₀b₁

c₂ a₂b₀, a₁b₁, a₀b₂

c₃ a₃b₀, a₂b₁, a₁b₂, a₀b₃

The center columns have the largest number of bits, creating the triangular shape shown in (a).

(b) First Reduction Stage

The dark terms are the bits retained after the first compression stage.

The light gray terms indicate bits that have already been reduced using:

 Half Adders (HA)

 Full Adders (FA)

 Compressors (4:2, 5:2, etc.)

For example:

Column c₉ may contain:

[
a_7b_2,; a_6b_3,; a_5b_4,; a_4b_5,; a_3b_6,; a_2b_7
]

Several of these bits are compressed into:

 Sum bit (same column)

 Carry bit (next column)

Thus column height decreases.

(c) Second Reduction Stage

More columns are compressed.

Notice:

 Many lower columns now contain only 0s.

 Remaining dark entries form a much smaller matrix.

Example:

Three bits

[
x+y+z
]

through a Full Adder become:

 Sum → same column

 Carry → next column

Therefore:

[
3 \text{ bits} \rightarrow 2 \text{ bits}
]

This gradually reduces the matrix height.

(d) Final Reduction Stage

Although the bottom portion is cut off in your image, this stage typically leaves only two rows:

Row 1:
[
S_{15}S_{14}\cdots S_0
]

Row 2:
[
C_{15}C_{14}\cdots C_0
]

These two rows are then added using a Carry Propagate Adder (CPA) such as:

 Ripple Carry Adder

 Carry Look-Ahead Adder

 Brent-Kung Adder

 Kogge-Stone Adder
to produce the final 16-bit multiplication result.

Meaning of Labels

 c₀, c₁, c₂, ... c₁₉ → column positions (weights).

 aᵢbⱼ → partial product bit.

 Black entries → active bits remaining in the current stage.

 Gray entries → bits already reduced or eliminated.

 0 → columns that became empty after reduction.

Overall Flow

8×8 Multiplication

64 Partial Products

Figure (a)

Initial Matrix

Figure (b)

1st Compression

Figure (c)

2nd Compression

Figure (d)

2-row Matrix

Final Adder

16-bit Product

This diagram is essentially showing how a Dadda/Wallace tree multiplier reduces the partial-
product matrix stage by stage before the final addition.
The paragraph below Table I explains how the segmented multiplier selects portions of the
operands (A), (B), and (C) depending on the control signals ((\alpha_C,\alpha_B,\alpha_A)).

Let's go line by line.

Line 1

"The (17) requires an (m_C) bit adder to compute the output."

 Equation (17) (given earlier in the paper) computes the final result.

 To perform this computation, an adder of width (m_C) bits is needed.

 Here:

o (m_C) = number of bits retained in segment (C).

Meaning:
Only the selected (m_C)-bit segment is added, reducing hardware complexity.

Line 2

"(c_5c_4c_3c_2c_1c_0) are truncated"

 The least significant bits (LSBs)

[
c_5,c_4,c_3,c_2,c_1,c_0
]

are discarded.

 They are not used in the final computation.

Why?

To save:

 area

 power

 delay

at the expense of a small approximation error.

Line 3

"while (c_{19}c_{18}\ldots c_{14}) are zero since (\alpha_C=0)."

The most significant bits

[
c_{19}, c_{18}, c_{17}, c_{16}, c_{15}, c_{14}
]

are forced to zero.

Reason:

[
\alpha_C = 0
]

indicates that the upper segment of (C) is not selected.

Therefore these bits contribute nothing to the result.

Line 4

"Please note that (C'_{ssm}) is simply a segment of (C), obtained by truncating (L_C)."

Definitions:

 (L_C) = lower segment of operand (C)

 (C'_{ssm}) = selected segment used in the segmented multiplier

So:

[
C'_{ssm}
]

is created by taking (L_C) and removing some bits.

Example:

If

[
L_C = c_{13}c_{12}c_{11}c_{10}c_9c_8c_7c_6c_5c_4c_3c_2c_1c_0
]

and bits (c_5)–(c_0) are discarded,

then

[
C'{ssm}=c{13}c_{12}c_{11}c_{10}c_9c_8c_7c_6
]

Line 5

"Table I summarizes the segmentation used to obtain (A'{ssm}), (B'{ssm}) and (C'_{ssm})
considering all possible values of (\alpha_C), (\alpha_B), and (\alpha_A)."
The table lists all combinations:

[
(\alpha_C,\alpha_B,\alpha_A)
]

For every combination it shows:

 Which part of (A) is selected

 Which part of (B) is selected

 Which part of (C) is selected

 Required shift amount

Thus the table acts as a lookup table for segmentation.

Line 6

"Fig. 3(d) shows an example for ((\alpha_C,\alpha_B,\alpha_A)=011."

Example case:

[
\alpha_C=0,\quad
\alpha_B=1,\quad
\alpha_A=1
]

This corresponds to the row:

αC αB αA

011

in Table I.

Line 7

"In this case (C'{ssm}) includes the bits (c{13}c_{12}\ldots c_6)"

For the 011 case:

[
C'_{ssm}

c_{13}c_{12}c_{11}c_{10}c_9c_8c_7c_6
]

Notice:

 (c_5) to (c_0) are removed

 (c_{13}) to (c_6) remain

These are the bits actually used.

Line 8

"(the bits (\alpha_B), and (\alpha_A)."

This sentence is partially cut in the image.

The intended meaning is that the chosen segment depends on:

[
\alpha_B
]

and

[
\alpha_A
]

as specified in the corresponding table row.

Line 9

"The last column reports the final shift to be applied."

The rightmost column (shift) tells how much the selected segment must be shifted.

For example:

If shift = (n-m),

then

[
Result = Segment \ll (n-m)
]

where << means left shift.

This restores the selected segment to its correct weight (bit position) in the final multiplication
result.

What Table I Does

The table answers:

1. Which part of A should be used?

2. Which part of B should be used?

3. Which part of C should be used?

 4. How much left shift is required afterward?

This segmentation allows the multiplier to process only the most important bits, reducing
hardware cost while maintaining acceptable accuracy.

This paragraph explains the segmentation choices used in the Static Segmented Multiplier-
Accumulator (SSMAC) shown in Fig. 4.

Let's go line by line.

Line 1

"As it can be observed, there are six possible segmentations to be considered for the operand A"

Operand A can be divided into six different segments.

Instead of always using the entire (n)-bit operand, the architecture selects only a portion of (A)
depending on the control signals.

This reduces:

 Power consumption

 Area

 Computation complexity

Line 2

"the segments are (L_A), (H_A) (see (1)) and also (L'_A), (L''_A), (H_A), and (H''_A)."

The six possible segments of A are:

1. (L_A) = Lower half of A

2. (H_A) = Upper half of A

3. (L'_A) = First modified lower segment

4. (L''_A) = Second modified lower segment

5. (H'_A) = First modified upper segment

6. (H''_A) = Second modified upper segment

These are generated by dividing A into smaller regions.

From the figure:

A[n-1:m] A[m-1:0]

↑ ↑

HA LA

Further truncation creates:

LA' , LA''

HA' , HA''

Line 3

"Similar considerations hold for B."

Exactly the same segmentation is applied to operand B.

Thus B has:

[
L_B,\ H_B,\ L'_B,\ L''_B,\ H'_B,\ H''_B
]

The upper block in Fig. 4 labeled (B'_{ssm}) performs this selection.

Line 4

"The possible segmentations for the operand C are four."

Operand C (the accumulator input) has only four possible segments.

Unlike A and B, C does not require six choices.

Line 5

"In addition to (H_C) and (L_C) (7), the other segments are named (L'_C) and (L''_C) in Table I."

For operand C the available segments are:

1. (H_C) = Upper segment

2. (L_C) = Lower segment

3. (L'_C) = Truncated lower segment

4. (L''_C) = More heavily truncated lower segment

So:

[
C \rightarrow
{H_C,\ L_C,\ L'_C,\ L''_C}
]

These are selected according to the control signals (\alpha_C).

Understanding Fig. 4

Step 1: Segment Selection

The control signals

[
\alpha_A,\ \alpha_B,\ \alpha_C
]

select:

 (A'_{ssm})

 (B'_{ssm})

 (C'_{ssm})

from the available segments.

Step 2: Multiplication

The selected segments of A and B are multiplied.

[
A'{ssm}\times B'{ssm}
]

This produces a product of approximately:

[
2m \text{ bits}
]

shown by the multiplier block.

Step 3: Error Correction

The block labeled:

Error correction

generates correction value (D).

Purpose:

When smaller segments are used, some bits are discarded.

The correction block compensates for part of the resulting error.

Step 4: Addition with C Segment

The selected C segment:

[
C'_{ssm}
]
is added to the corrected product.

This addition uses an

[
m_C\text{-bit adder}
]

which is why the caption states:

"The architecture requires a small (m_C)-bits adder."

Step 5: Output Multiplexer

The outputs:

[
y_1,\ y_2,\ y_3,\ y_4
]

represent the same MAC result shifted by different amounts.

From the figure:

[
y_1 = Y_{MAC}
]

[
y_2 = {Y_{MAC},1,{(n-m-1){0}}}
]

[
y_3 = {Y_{MAC},1,{2(n-m)-1{0}}}
]

[
y_4 = {Y_{MAC},1,{(n_C+m_C-1){0}}}
]

The multiplexer chooses the correct shifted version according to:

[
\alpha_A,\alpha_B,\alpha_C
]

Main Idea of Fig. 4

The architecture does not multiply the full operands every time. Instead it:

1. Selects important segments of A, B, and C.

2. Multiplies the selected A and B segments.

 3. Applies error correction.

4. Adds a selected segment of C.

5. Shifts the result back to the proper bit position.

This achieves a smaller, lower-power multiplier-accumulator with only a small loss in accuracy.

Let's explain the paragraph line by line.

Line 1

"The Fig. 4 shows the hardware implementation of the proposed SSMAC."

 Fig. 4 presents the actual hardware architecture of the Static Segmented Multiplier-
Accumulator (SSMAC).

 It shows how operands A, B, and C are segmented, multiplied, added, and corrected.

Line 2

"Different from the MAC of Fig. 2(b), two 6-1 multiplexers are used to select the relevant segments
(A'{ssm}) and (B'{ssm}) for the inputs A and B, according to the values of (\alpha_C,\alpha_B,) and
(\alpha_A)."

What is a 6-to-1 Multiplexer?

A 6-to-1 MUX chooses one of six inputs.

For operand A, the six possible segments are:

[
L_A,;H_A,;L'_A,;L''_A,;H'_A,;H''_A
]

Similarly for B.

The control signals

[
(\alpha_C,\alpha_B,\alpha_A)
]

determine which segment is selected.

Thus:

[
A \rightarrow A'_{ssm}
]

[
B \rightarrow B'_{ssm}
]
Line 3

"Similarly, the 4-1 multiplexer on the right selects the segment (C'_{ssm}) for the input C."

Operand C has only four possible segments:

[
L_C,;H_C,;L'_C,;L''_C
]

Therefore only a 4-to-1 MUX is needed.

The selected segment becomes:

[
C'_{ssm}
]

Line 4

"A small inner multiplier-accumulator computes the intermediate results named (Y_{MAC})."

After segmentation:

[
A'{ssm}\times B'{ssm}+C'_{ssm}
]

is computed by a smaller MAC unit.

Its output is called:

[
Y_{MAC}
]

Since the operands are smaller than the original ones, the hardware is much smaller and consumes
less power.

Line 5

"As shown in Table I, there are four possible shifts to obtain the result."

After multiplication, the result may represent:

 lower bits

 upper bits

 middle bits

Therefore it must be shifted to its correct position.

The shift amount depends on:

[
(\alpha_C,\alpha_B,\alpha_A)
]

Table I lists these shift values.

Possible shifts are:

[
0,; n-m,; 2(n-m),; n_C-m_C
]

(depending on the selected segments).

Line 6

"The multiplexer on the bottom in Fig. 4 is responsible for performing this shift to compute
(Y_{SSMAC})."

The bottom MUX chooses one of:

[
y_1,;y_2,;y_3,;y_4
]

Each output corresponds to a different shift.

For example:

[
y_1 = Y_{MAC}
]

(no shift)

or

[
y_2 = Y_{MAC}\ll(n-m)
]

(left shift by (n-m))

The selected output becomes:

[
Y_{SSMAC}
]

which is the final result.

Line 7
"The high bit in the quantities (y_2,y_3,y_4) of Fig. 4 and the dashed box that adds the correction
term D allow to limit the error of the proposed SSMAC."

Why is there error?

Because some bits of A, B, and C were discarded.

This introduces approximation errors.

To reduce this error:

Method 1: High Bit Insertion

When shifting:

[
Y_{MAC}
]

a '1' is inserted in a higher position.

This acts as a rounding operation.

Method 2: Correction Term D

The dashed block computes:

[
D
]

which is added to the result.

This compensates for part of the error caused by truncation.

Section B: Error Compensation

Now the paper mathematically analyzes the error.

Line 8

"The error sources in the proposed SSMAC are due to the truncation of the operands A, B, C."

Since only segments are used:

[
A'{ssm},;B'{ssm},;C'_{ssm}
]

some bits are removed.

Those removed bits create error.

Line 9

"Let us indicate as (\epsilon_A,\epsilon_B,\epsilon_C) the errors due to operands truncation:"

Define:

[
\epsilon_A
]

= bits removed from A

[
\epsilon_B
]

= bits removed from B

[
\epsilon_C
]

= bits removed from C

Equation (19)

[
A=A'_{ssm}+\epsilon_A
]

Meaning:

Original A

Selected segment

Discarded portion

Similarly:

[
B=B'_{ssm}+\epsilon_B
]

[
C=C'_{ssm}+\epsilon_C
]
Example

Suppose:

[
A=11010110
]

Selected segment:

[
A'_{ssm}=11010000
]

Discarded bits:

[
\epsilon_A=00000110
]

Then:

[
A=A'_{ssm}+\epsilon_A
]

Line 10

"The total approximation error of the SSMAC can be written as:"

Now derive total error.

Exact MAC:

[
A\times B+C
]

Approximate MAC:

[
A'{ssm}\times B'{ssm}+C'_{ssm}
]

Difference between them is the error:

[
\epsilon
]

Equation (20)
[
\epsilon

A\times B+C

(A'{ssm}\times B'{ssm}+C'_{ssm})
]

Substitute Equation (19):

[
A=A'_{ssm}+\epsilon_A
]

[
B=B'_{ssm}+\epsilon_B
]

[
C=C'_{ssm}+\epsilon_C
]

After expansion:

[
\epsilon

\epsilon_A B'{ssm}
+
\epsilon_B A'{ssm}
+
\epsilon_C
+
\epsilon_A\epsilon_B
]

Meaning of Each Term

First Term

[
\epsilon_A B'_{ssm}
]

Error caused by truncating A.

Second Term

[
\epsilon_B A'_{ssm}
]
Error caused by truncating B.

Third Term

[
\epsilon_C
]

Error caused by truncating C.

Fourth Term

[
\epsilon_A\epsilon_B
]

Interaction between truncation errors of A and B.

Usually small.

Final Paragraph

"The largest error component is due to the first two terms in (20)."

The dominant errors are:

[
\epsilon_A B'_{ssm}
]

and

[
\epsilon_B A'_{ssm}
]

because they are multiplied by large values.

"Thus, the error is mainly due to the segmentation of operands A and B of the multiplier"

Most error comes from the multiplier inputs A and B.

"while the error due to the segmentation of C is lower."

Since C is only added (not multiplied), its truncation error is much smaller.
"As a consequence, the approximation error can be widely mitigated by using the same approach
discussed in [19]"

Therefore, by applying the error-correction method (term (D)) introduced in reference [19], most
of the approximation error can be reduced.

Key Takeaway

The paper models the truncated bits as:

[
\epsilon_A,\epsilon_B,\epsilon_C
]

and proves that the largest errors come from truncating A and B, not C. Therefore, the correction
block (D) is mainly designed to compensate for multiplier-input truncation errors.

This section explains how the error correction term (D) is generated to compensate for the error
introduced by truncating partial products in the segmented multiplier.

First Paragraph

"As an example, Fig. 5(a) shows the PPM for the case (m=5) and (m_C=12)."

 PPM = Partial Product Matrix.

 The example uses:

o (m=5) (selected segment width)

o (m_C=12)

The figure shows which partial products are kept and which are discarded.

Line 2

"In the case ((\alpha_C,\alpha_B,\alpha_A)=011) the dropped terms with the largest weight (2^9)
are (a_7b_2) and (a_2b_7)."

For control combination:

[
(\alpha_C,\alpha_B,\alpha_A)=011
]

some partial products are removed.

The most important discarded terms are:

[
a_7b_2
]

and
[
a_2b_7
]

Their weight is:

[
2^{7+2}=2^9
]

because the weight of (a_ib_j) is:

[
2^{i+j}
]

These are the largest discarded terms and therefore contribute most to the error.

Line 3

"We mitigate the error by performing the OR of these two terms and by including this value in the
column of weight (2^{10})."

Instead of completely ignoring them, the circuit computes:

[
a_7b_2 ; OR ; a_2b_7
]

If either term is 1:

[
d_0=1
]

This correction bit is then inserted into the next higher column:

[
2^{10}
]

Why?

Because:

[
2^9 + 2^9 = 2^{10}
]

So a single bit at (2^{10}) roughly approximates the contribution of the discarded terms.

Line 4
"A similar approach is used for the dropped terms with weight (2^8) (a_6b_2) and (a_2b_6)."

Another discarded pair:

[
a_6b_2
]

[
a_2b_6
]

Both have weight:

[
2^{6+2}=2^8
]

Again compute:

[
a_6b_2 ; OR ; a_2b_6
]

and use it as another correction bit.

Next Paragraph

"The condition in Fig. 5(b) refers to the case ((\alpha_C,\alpha_B,\alpha_A)=111)."

Now they analyze another segmentation mode:

[
(\alpha_C,\alpha_B,\alpha_A)=111
]

Different partial products are discarded.

Line

"Here, the terms considered for the error correction are: (a_7b_3) OR (a_3b_7)."

Largest removed terms:

[
a_7b_3
]

[
a_3b_7
]

Weight:
[
2^{7+3}=2^{10}
]

Compute:

[
a_7b_3 ; OR ; a_3b_7
]

Insert correction in column:

[
2^{11}
]

Next Line

"and: (a_6b_3) OR (a_3b_6) (included in column of weight (2^{10}))."

Second correction pair:

[
a_6b_3
]

[
a_3b_6
]

Weight:

[
2^9
]

OR them and place correction at:

[
2^{10}
]

Equation (21)

The paper generalizes the correction term:

D \approx 2^{2n-2m}\sum_{k=0}^{1} d_k 2^k

Meaning

The total correction is built from two bits:

[
d_0
]

and

[
d_1
]

Only two correction bits are used.

Then the whole correction value is shifted by:

[
2^{2n-2m}
]

to place it at the correct significance level.

Equation (22)

d_k=(a_{k+n-m}b_{n-m-1};OR;b_{k+n-m}a_{n-m-1})

Meaning

Each correction bit is formed by OR-ing two discarded partial products.

For (k=0):

[
d_0=
(a_{n-m}b_{n-m-1})
\ OR
(b_{n-m}a_{n-m-1})
]

For (k=1):

[
d_1=
(a_{n-m+1}b_{n-m-1})
\ OR
(b_{n-m+1}a_{n-m-1})
]

Thus the correction hardware is extremely simple:

 Two AND terms

 One OR gate
Why Only Two Terms?

"Only two terms are considered in (21)."

The authors tested many possibilities.

They found that correcting only the two most significant discarded terms gives:

 Good accuracy improvement

 Very little hardware overhead

Adding more terms increases area and power while giving diminishing returns.

Next Paragraph

"When ((\alpha_C,\alpha_B,\alpha_A)=111), the expression for the error compensation term is

similar to (21)-(22)."

For the 111 mode:

 Same correction method

 Same equations

but different operand segments are used.

Line

"In this case come into play the terms (A'{ssm}) and (B'{ssm}) that are truncated versions of (H_A)
and (H_B)."

For 111 mode:

Instead of using:

[
L_A,\ L_B
]

the circuit uses truncated upper segments:

[
A'_{ssm}
]

[
B'_{ssm}
]

derived from:
[
H_A,\ H_B
]

Last Equation (23)

[
m'

\frac{(n_C-m_C)-2(n-m)}{2}
]

This computes the effective width (m').

It tells how many MSBs are retained in the truncated upper segments.

Overall Idea

The authors observed:

1. The largest approximation error comes from a few high-weight discarded partial products.

2. Instead of restoring all discarded terms, they:

o Identify the two most important discarded pairs.

o OR each pair together.

o Insert the result into the next higher-weight column.

3. This creates the correction value (D).

Result:

 Very small hardware cost (few gates).

 Significant reduction in multiplier approximation error.

This figure (Fig. 5) illustrates how the error correction term (D) is generated in the SSMAC by
examining the most significant discarded partial products.

Figure 5(a): Case ((\alpha_C,\alpha_B,\alpha_A)=011)

The black terms are the partial products used in multiplication.

The blue terms are the important partial products that were discarded during segmentation.

First discarded pair

[
a_7b_2,\quad a_2b_7
]

Both belong to column (c_9).

Why?

[
7+2=9
]

[
2+7=9
]

So their weight is:

[
2^9
]

These are the largest-weight discarded terms.

Correction Bit (d_0)

Instead of ignoring them completely, compute:

[
d_0 = a_7b_2 ; OR ; a_2b_7
]

Shown in blue below column (c_9).

If either discarded term is 1:

[
d_0=1
]

Placement of (d_0)

The red arrow shows that (d_0) is inserted into column:

[
c_{10}
]

whose weight is:

[
2^{10}
]
The green "1" in column (c_{10}) represents this correction bit.

Second discarded pair

Also highlighted in blue:

[
a_6b_2,\quad a_2b_6
]

Weight:

[
6+2=8
]

Thus both belong to column:

[
c_8
]

(weight (2^8)).

Correction Bit (d_1)

Compute:

[
d_1 = a_6b_2 ; OR ; a_2b_6
]

This correction is inserted into:

[
c_9
]

(weight (2^9)).

The green "1" in column (c_9) represents this correction.

Why Use OR?

Suppose:

(a_7b_2) (a_2b_7) OR

0 0 0

0 1 1
(a_7b_2) (a_2b_7) OR

1 0 1

1 1 1

Instead of recovering both terms exactly, the circuit uses one OR gate.

Advantages:

 Very small hardware

 Very low power

 Significant error reduction

Figure 5(b): Case ((\alpha_C,\alpha_B,\alpha_A)=111)

Now a different segmentation is used.

The discarded terms are different.

First discarded pair

[
a_7b_3,\quad a_3b_7
]

Weight:

[
7+3=10
]

Column:

[
c_{10}
]

(weight (2^{10}))

Correction

Compute:

[
a_7b_3 ; OR ; a_3b_7
]

and insert it into:

[
c_{11}
]

(weight (2^{11}))

The red arrow points from (c_{10}) to (c_{11}).

Second discarded pair

[
a_6b_3,\quad a_3b_6
]

Weight:

[
6+3=9
]

Column:

[
c_9
]

Correction

Compute:

[
a_6b_3 ; OR ; a_3b_6
]

and insert into:

[
c_{10}
]

(weight (2^{10}))

What the Red Arrows Mean

The red arrows show:

Discarded column

OR operation
 ↓

Insert correction

into next higher column

Example:

Weight 2^9

(a7b2, a2b7)

↓ OR

Correction bit

Placed at weight 2^10

What the Green "1" Means

The green "1" indicates the location where the correction bit is added.

It is not always equal to 1.

Actually:

[
1 \equiv d_k
]

where

[
d_k = (\text{first discarded term})\ OR\ (\text{second discarded term})
]

The figure uses "1" only to show the insertion position.

Main Idea of Fig. 5

The SSMAC discards many partial products to save area and power.

The largest error comes from a few high-weight discarded terms.

Instead of restoring all discarded terms:

1. Select the two most significant discarded pairs.

2. OR each pair.

3. Insert the result into the next higher-weight column.

4. Add these bits as the correction term (D).

This provides a good trade-off between:

 Accuracy

 Area

 Power consumption

 Hardware complexity

with only a few extra gates.

This section defines the error metrics used to evaluate the accuracy of the approximate SSMAC
compared to the exact MAC.

1. Error (E or D)

The paper defines:

D=Y_{EXACT}-Y_{APP}

where:

 (Y_{EXACT}) = output of the exact MAC

 (Y_{APP}) = output of the approximate MAC (SSMAC)

Meaning

It is simply the difference between the correct result and the approximate result.

Example

If

[
Y_{EXACT}=100
]

and

[
Y_{APP}=95
]

then

[
D=100-95=5
]

2. Error Distance (ED)

Defined as:
ED=\left|Y_{EXACT}-Y_{APP}\right|

Meaning

ED measures how far the approximate result is from the exact result, regardless of sign.

Example

If

[
Y_{EXACT}=100
]

and

[
Y_{APP}=105
]

then

[
D=-5
]

but

[
ED=|-5|=5
]

Thus ED is always positive.

3. Relative Error Distance (RED)

Defined as:

RED=\frac{ED}{|Y_{EXACT}|}

(valid only when (Y_{EXACT}\neq0))

Meaning

RED tells what fraction of the exact result is error.

Example

If

[
Y_{EXACT}=100
]

and
[
ED=5
]

then

[
RED=\frac{5}{100}=0.05
]

or

[
5%
]

Why RED is Important

Consider:

Case 1

Error = 5

Exact result = 100

[
RED=5%
]

Case 2

Error = 5

Exact result = 1000

[
RED=0.5%
]

Same absolute error, but much less significant.

Average Error Metrics

The paper runs millions of simulations and computes average values.

4. Normalized Mean Error (NM)

Defined as:
[
NM=\frac{\mu_E}{Y_{MAX}}
]

where:

 (\mu_E) = mean error

 (Y_{MAX}) = maximum possible output value

Meaning

Average signed error normalized by the largest possible result.

5. Normalized Mean Error Distance (NMED)

Defined as:

[
NMED=\frac{\mu_{ED}}{Y_{MAX}}
]

where:

[
\mu_{ED}
]

is the average ED.

Meaning

Measures the average magnitude of the error.

This is one of the most commonly used metrics in approximate computing.

6. Mean Relative Error Distance (MRED)

Defined as:

[
MRED=\mu_{RED}
]

Meaning

Average relative error across all test cases.

Example

Suppose three test cases give:

[
RED_1=1%
]

[
RED_2=3%
]

[
RED_3=2%
]

Then

[
MRED=\frac{1+3+2}{3}=2%
]

7. Normalized Maximum Error Distance (NmaxED)

Defined as:

[
NmaxED=\frac{\max(ED)}{Y_{MAX}}
]

Meaning

It measures the worst-case error.

Example

If during 10 million simulations:

Largest error found:

[
ED=100
]

and

[
Y_{MAX}=65535
]

then

[
NmaxED=\frac{100}{65535}
]

Meaning of the Symbols

The paper states:

"where (\mu_E,\mu_{ED},\mu_{RED}) are the mean values of E, ED, RED, respectively."

Thus:

Symbol Meaning

(\mu_E) Average error

(\mu_{ED}) Average error distance

(\mu_{RED}) Average relative error distance

Probability of Large Errors (PRED)

The paper also defines:

[
PRED
]

which means:

Probability that the relative error exceeds 2%.

Mathematically:

[
PRED=P(RED>0.02)
]

Example

Suppose:

 10,000 test cases simulated

 300 cases have RED > 2%

Then

[
PRED=\frac{300}{10000}=0.03
]

or

[
3%
]

Why These Metrics Are Used

Different metrics capture different aspects:

Metric Measures

E Signed error

ED Absolute error

RED Percentage error

NM Average signed error

NMED Average absolute error

MRED Average percentage error

NmaxED Worst-case error

PRED Frequency of large errors

Last Paragraph

"Error performance of investigated MACs have been obtained by simulating 10 million uniformly
distributed values of A, B and C."

This means:

 The authors generated 10 million random test vectors.

 Inputs A, B, and C were uniformly distributed.

 For every test vector they computed:

o Exact MAC output

o Approximate SSMAC output

o Error metrics

The reported NM, NMED, MRED, NmaxED, and PRED values are statistical results obtained from
these 10 million simulations.

Let's explain this paragraph line by line.

Line 1

"the use of the architecture in Fig. 2(b), where segmentation on operand C is not performed."

This refers to the previous MAC architecture.

In Fig. 2(b):

 A and B are segmented.

 C is not segmented.

 The complete accumulator operand C is used.

Therefore:

 Larger adder is needed.

 More hardware area and power consumption.

Line 2

"As it can be observed in Fig. 6, the segmentation of C reveals effective."

The results in Fig. 6 show that segmenting operand C works well.

Meaning:

 Hardware complexity decreases.

 Accuracy remains nearly the same.

So segmentation of C is beneficial.

Line 3

"For (m=4), using (m_C=12) (and hence a 12-bits adder) allows to obtain almost the same precision
as the architecture with (m_C=20) (using a 20-bits adder)."

Case:

[
m=4
]

The proposed design keeps only:

[
m_C=12
]

bits of operand C.

Therefore the adder width is:

[
12\text{ bits}
]

instead of

[
20\text{ bits}
]

What they observed

Accuracy with:

[
m_C=12
]

is almost the same as with

[
m_C=20
]

even though:

[
20-12=8
]

bits are removed.

Advantage

Smaller adder:

 less area

 less power

 shorter delay

without noticeable loss of accuracy.

Line 4

"For (m=5), the SSMAC with (m_C=14) gives a precision very close to the one with (m_C=20)."

Now:

[
m=5
]

and

[
m_C=14
]

Only 14 bits of C are kept.

Again the obtained precision is very close to the full:

[
m_C=20
]
case.

Line 5

"The plots in Fig. 6 also show that the correction technique is efficacious"

"Efficacious" means effective.

The correction term (D):

[
D = \text{error compensation}
]

successfully improves accuracy.

Line 6

"reducing by more than 50% NMED and MRED in all investigated cases."

The correction mechanism reduces:

NMED

Normalized Mean Error Distance

[
NMED=\frac{\mu_{ED}}{Y_{MAX}}
]

and

MRED

Mean Relative Error Distance

[
MRED=\mu_{RED}
]

by more than:

[
50%
]

This is a significant improvement.

Next Paragraph

Line 7

"The Table II reports results obtained for the proposed SSMAC"

Table II contains the performance results of:

 Proposed SSMAC

 Competing MAC architectures

Line 8

"(the SSMACs marked with * implement the correction technique)"

In Table II:

If an SSMAC entry has:

[
*
]

it means the correction block (D) is enabled.

Without *:

 No error correction.

With *:

 Error correction active.

Line 9

"and for several state-of-the-art MACs from literature in the case (n=8, n_C=20)."

Comparison is performed using:

[
n=8
]

8-bit multiplier inputs.

and

[
n_C=20
]

20-bit accumulator.

Several published MAC designs are compared.

Line 10

"Similarly, Table III shows results for (n=8, n_C=24) bits as further test case."
Another experiment uses:

[
n=8
]

and

[
n_C=24
]

to verify that the proposed method also works for larger accumulators.

Comparison With Previous Works

Now the paper explains the architectures used for comparison.

Line 11

"The techniques [10], [12], [14] implement different types of approximate multipliers."

References:

 [10]

 [12]

 [14]

all use approximate multipliers.

Each uses a different approximation strategy.

Line 12

"The design in [10] uses a recursive architecture based on an approximate 4 × 4 multiplier."

Reference [10]:

 Builds a large multiplier from smaller

[
4\times4
]
approximate multipliers.

This recursive construction reduces hardware cost.

Line 13

"In [12], L represents the number of rows grouped for the compression with the OR-gates."
Reference [12]:

Uses OR-gates during partial-product compression.

Parameter:

[
L
]

determines how many rows are merged.

Larger (L):

 More approximation

 Lower hardware cost

Line 14

"The reference [14] uses approximate 4-2 compressors that populate the n less significant columns
in the PPM."

Reference [14]:

Uses approximate:

[
4:2
]

compressors.

These compressors operate on the least significant columns of the Partial Product Matrix (PPM).

Line 15

"The CN version uses only the compressors developed in [14]"

CN configuration:

Uses only the original compressors proposed in [14].

Line 16

"while the CNHYB version uses both the compressors of [14] and the ones proposed in [15]."

CNHYB = Hybrid version.

Uses:

 Compressors from [14]

 Compressors from [15]

combined together.

Line 17

"The architectures in [20], [21], [22] are specifically designed for multiplier-accumulators."

Unlike [10], [12], [14], these works directly design complete MAC units.

Line 18

"The work [20] employs a mask able to define the accuracy of the PPM compression."

Reference [20]:

Uses a mask parameter.

The mask controls:

 Accuracy

 Hardware complexity

of partial-product compression.

Line 19

"We considered the two cases mask = 0 and mask = 127."

Two configurations tested:

mask = 0

Maximum simplification.

Highest approximation.

mask = 127

Maximum precision.

Lowest approximation.

Line 20

"The MACISH architecture [21] uses a recursive structure."

Reference [21]:

Uses recursive hardware construction.

Similar idea to [10].

Line 21

"The MAC ISH_1 involves only approximate 2 × 2 multipliers"

Configuration:

[
ISH_1
]

Uses only approximate:

[
2\times2
]

multipliers.

This provides maximum area savings but lower accuracy.

Line 22

"whereas ISH_2 uses also exact multipliers."

Configuration:

[
ISH_2
]

Mixes:

 Approximate multipliers

 Exact multipliers

to improve accuracy.

Line 23

"The IBAM architecture [22] uses imprecise adders and multipliers, trying to compensate the error
of the two blocks."

Reference [22]:

Both:

 Multiplier

 Adder

are approximate.
The design attempts to balance their errors so that overall MAC accuracy remains acceptable.

Main Conclusion of This Section

The authors show that:

1. Segmenting operand C greatly reduces adder size.

2. A 12-bit or 14-bit adder can achieve accuracy close to a 20-bit adder.

3. The correction term (D) reduces NMED and MRED by more than 50%.

4. The proposed SSMAC is compared against many state-of-the-art approximate MAC

architectures from the literature.

This figure shows the error performance of the proposed SSMAC for different values of (m_C)
(number of bits retained from operand (C)).

Axes Meaning

 X-axis ((m_C)): Number of bits retained from operand (C).

 Y-axis:

o NMED (Normalized Mean Error Distance) in plots (a) and (c)

o MRED (Mean Relative Error Distance) in plots (b) and (d)

Blue curve:

 Without correction ((D=0))

Orange curve:

 With correction ((D\neq0))

Figure (a): NMED for (m=4)

Observation

When (m_C) increases from 10 to 12:

 NMED drops sharply.

 Error decreases significantly.

Approximate values:

(m_C) Without Correction With Correction

10 3.3×10⁻³ 1.25×10⁻³

11 2.5×10⁻³ 1.1×10⁻³

12 1.6×10⁻³ 0.63×10⁻³
After (m_C=12):

 Curves become nearly flat.

 Keeping more than 12 bits gives very little additional benefit.

Conclusion

For (m=4),

[
m_C=12
]

is sufficient.

Figure (b): MRED for (m=4)

Observation

MRED decreases rapidly as (m_C) increases.

Without correction:

[
14\times10^{-3}
\rightarrow
7\times10^{-3}
]

With correction:

[
5.8\times10^{-3}
\rightarrow
2.8\times10^{-3}
]

at (m_C=12).

Beyond 12 bits:

 Almost no improvement.

Effect of Correction

The correction term reduces MRED by approximately:

[
50%-60%
]

Figure (c): NMED for (m=5)

Now the multiplier segment width is larger:

[
m=5
]

Observation

NMED keeps decreasing until about:

[
m_C=14
]

Approximate values:

(m_C) Without Corr. With Corr.

10 3.2×10⁻³ 1.35×10⁻³

12 1.6×10⁻³ 0.7×10⁻³

14 0.75×10⁻³ 0.32×10⁻³

After (m_C=14):

 Improvement becomes negligible.

Conclusion

For (m=5),

[
m_C=14
]

is sufficient.

Figure (d): MRED for (m=5)

This plot shows the same trend for relative error.

Without correction:

[
0.0135
\rightarrow
0.003
]

With correction:

[
0.0063
\rightarrow
0.0013
]

as (m_C) increases.

Again, the curve flattens after:

[
m_C=14
]

Why Does Error Decrease as (m_C) Increases?

Recall:

[
C'_{ssm}
]

is only a segment of operand (C).

When (m_C) is small:

 More bits of (C) are discarded.

 Larger truncation error.

When (m_C) increases:

 More bits are retained.

 Less truncation error.

Therefore:

[
NMED,\ MRED
]

decrease.

Why Do Curves Become Flat?

After a certain point:

 Error due to (C) becomes very small.

 Remaining error mainly comes from segmentation of (A) and (B).

Adding more bits of (C) no longer helps much.

That's why the curves saturate.

Effect of the Correction Technique

Compare blue and orange curves.

For every value of (m_C):

[
\text{Error with correction}
<
\text{Error without correction}
]

The reduction is typically:

[
50% \text{ to } 60%
]

which confirms the effectiveness of the correction term (D).

Main Conclusions from Fig. 6

1. Increasing (m_C) reduces error.

2. Error improvement saturates after:

o (m_C \approx 12) for (m=4)

o (m_C \approx 14) for (m=5)

3. Using a larger (m_C) than these values gives little benefit.

4. The correction term (D) reduces both NMED and MRED by more than 50%.

5. A 12-bit or 14-bit adder can achieve accuracy very close to a 20-bit adder, saving hardware
area and power.

Let's explain this paragraph line by line.

Line 1

"The considered approximate multiplier truncates the VBL = 3 less significant columns of the
PPM."

Terms

 PPM = Partial Product Matrix

 VBL = Vertical Broken Lines (approximation boundary)

The multiplier removes the 3 least significant columns of the partial-product matrix.

Example:

c7 c6 c5 c4 c3 c2 c1 c0
 ↑ ↑ ↑

truncated

Columns:

[
c_0,; c_1,; c_2
]

are discarded.

Why?

To reduce:

 Area

 Power

 Delay

at the cost of some error.

Line 2

"The results in Tables II, III show that the investigated MACs cover a wide range of precision."

The tested MAC architectures produce different levels of accuracy.

Some are:

 Highly accurate

 Moderately accurate

 Very approximate

Thus the comparison spans a broad accuracy range.

Line 3

"The error performances of the proposed SSMACs with (m=4) are comparable with [10], [12], [20],
and [21]"

The proposed SSMAC using:

[
m=4
]

achieves approximately the same accuracy as the MAC architectures from references:

 [10]

 [12]
  [20]

 [21]

This means the proposed design is competitive with existing methods.

Line 4

"with NMED and MRED in the range (2.56\times10^{-4} - 3.3\times10^{-3}), and (1.12\times10^{-
3} - 1.44\times10^{-2}) for (n_C=20) respectively."

For the test case:

[
n_C=20
]

the observed errors are:

NMED

[
2.56\times10^{-4}
]

to

[
3.3\times10^{-3}
]

which is:

0.000256 to 0.0033

MRED

[
1.12\times10^{-3}
]

to

[
1.44\times10^{-2}
]

which is:

0.00112 to 0.0144

or

0.112% to 1.44%
relative error.

Line 5

"Similarly, NMED and MRED are in the range (1.69\times10^{-5}-4.21\times10^{-4}), and (1.17\
times10^{-4}-2.81\times10^{-3}) for (n_C=24)."

When accumulator width increases:

[
n_C=24
]

the errors become smaller.

NMED

[
1.69\times10^{-5}
]

to

[
4.21\times10^{-4}
]

MRED

[
1.17\times10^{-4}
]

to

[
2.81\times10^{-3}
]

The larger accumulator improves accuracy.

Line 6

"Only the implementations [14] and [22] show superior accuracy"

Among all compared designs, only references:

 [14]

 [22]

are more accurate than the proposed SSMAC.

Line 7

"with NMED and MRED in the ranges (2.19\times10^{-6}-2.97\times10^{-5}) and (1.11\times10^{-

5}-1.42\times10^{-4}) when (n_C=20)."

For those highly accurate designs:

NMED

[
2.19\times10^{-6}
]

to

[
2.97\times10^{-5}
]

MRED

[
1.11\times10^{-5}
]

to

[
1.42\times10^{-4}
]

These values are much smaller than the proposed SSMAC.

Therefore [14] and [22] are more accurate.

Line 8

"and in the range (1.47\times10^{-7}-1.97\times10^{-6}) and (1.09\times10^{-6}-1.43\times10^{-

5}) when (n_C=24)."

For:

[
n_C=24
]

their errors become even smaller.

These architectures are extremely accurate.

Section C: Electrical Performances

Now the paper evaluates hardware cost.

Line 9

"We synthesize the proposed SSMACs and the state-of-the-art in TSMC 28nm CMOS technology"

All circuits were implemented using:

TSMC 28nm CMOS technology

This ensures a fair comparison.

Line 10

"employing a physical flow in Cadence Genus."

The synthesis tool used is:

Cadence Genus

This tool converts RTL (Verilog/VHDL) into gate-level hardware.

Line 11

"An exact Dadda MAC is also implemented for reference."

Besides approximate MACs, the authors also implement an exact Dadda MAC.

Purpose:

To provide a baseline.

Then they can compare:

 Area savings

 Power savings

 Accuracy loss

against the exact implementation.

Line 12

"We obtain the power dissipation by means of post-synthesis simulations"

Power is measured after synthesis.

This is more realistic than theoretical estimation.

Line 13

"with (10^5) random input vectors"

They test the circuit using:

[
100,000
]

random input combinations.

This provides statistically reliable power measurements.

Line 14

"and toggle rate of 1GHz."

Inputs are assumed to change at:

[
1\text{ GHz}
]

meaning:

[
10^9
]

switching opportunities per second.

Power consumption depends strongly on switching activity.

Line 15

"The timing constraint is 500ps for all the implementations"

Every design must satisfy:

[
500\text{ ps}
]

(clock period constraint)

which corresponds to:

[
\frac{1}{500\text{ ps}}

2\text{ GHz}
]
maximum clock frequency target.

Line 16

"to obtain iso-delay area and power values."

Iso-delay means:

All designs are compared at the same speed.

Therefore:

 Area comparison is fair.

 Power comparison is fair.

Otherwise a slower circuit would naturally consume less power.

Main Takeaways

1. The approximate multiplier discards the 3 least significant PPM columns.

2. SSMAC with (m=4) achieves accuracy comparable to several state-of-the-art MACs.

3. Only architectures [14] and [22] are noticeably more accurate.

4. Hardware evaluation is performed in TSMC 28nm CMOS technology.

5. Power is measured using 100,000 random vectors at 1 GHz.

6. All designs are constrained to 500 ps delay, ensuring a fair area/power comparison.

Let's explain this paragraph line by line.

Line 1

"The minimum delay is instead computed by synthesizing each MAC at the minimum timing
constraint that allows to achieve a positive slack."

What is Slack?

In digital design:

[
\text{Slack} = \text{Required Time} - \text{Arrival Time}
]

 Positive slack → timing is met.

 Negative slack → timing violation.

Meaning
The authors keep tightening the clock period during synthesis until the design just barely meets
timing.

The smallest clock period that still gives:

[
\text{Slack} > 0
]

is reported as the minimum delay.

Line 2

"As shown in Tables II the proposed SSMACs show a remarkable power reduction compared to the
exact MAC"

The proposed approximate MAC consumes much less power than the exact Dadda MAC.

Line 3

"ranging from 45%-66% for (m=4) and 16%-60% for (m=5)."

For (m=4)

Power reduction:

[
45% \text{ to } 66%
]

Example:

If exact MAC consumes:

[
100;\mu W
]

then approximate MAC consumes:

[
34;\mu W \text{ to } 55;\mu W
]

For (m=5)

Power reduction:

[
16% \text{ to } 60%
]
Still significant but generally less than the (m=4) case.

Line 4

"The segmentation on operand C reveals effective in reducing power consumption."

This confirms one of the paper's main ideas:

Instead of using the full accumulator operand:

[
C
]

they use only:

[
C'_{ssm}
]

This reduces:

 Adder size

 Switching activity

 Power consumption

Line 5

"For example, the SSMAC architecture with (m=5,m_C=20) has a power consumption of 225 \mu
W"

Configuration 1

[
m=5
]

[
m_C=20
]

No segmentation of C.

Power:

[
225;\mu W
]

Line 6
"while the SSMAC with (m=5,m_C=14) exhibits a power consumption of 188 \mu W with almost
the same precision."

Configuration 2

[
m=5
]

[
m_C=14
]

Power:

[
188;\mu W
]

Power Saving

[
225-188=37;\mu W
]

Percentage:

[
\frac{37}{225}\times100
\approx16.4%
]

So:

 Similar accuracy

 16% less power

Line 7

"Likewise, also results in Table III show remarkable power improvements"

The same trend appears in another test case (Table III).

The proposed architecture consistently saves power.

Line 8

"ranging between 42.4%-69.5% for (m=4) and 12.8%-63.6% for (m=5)."

Table III Results

For (m=4):

[
42.4%-69.5%
]

power reduction.

For (m=5):

[
12.8%-63.6%
]

power reduction.

Again, substantial savings.

Comparison With Other Approximate MACs

Line 9

"Among the other investigated approximate MACs, [12] (L=4) and [20] mask = 0 show the largest
power saving compared to the exact MAC"

Among competing designs:

Reference [12]

[
L=4
]

Reference [20]

[
mask=0
]

These save the most power.

Line 10

"offering 45% and 37.3% respectively for (n_C=20)"

For:

[
n_C=20
]

Power savings:
Design Saving

[12], (L=4) 45%

[20], mask=0 37.3%

Line 11

"and 44.5% and 36.4% with (n_C=24)."

For:

[
n_C=24
]

Power savings become:

Design Saving

[12], (L=4) 44.5%

[20], mask=0 36.4%

Line 12

"Among the investigated circuits, area saving shows a similar trend"

Not only power,

but chip area also decreases in a similar manner.

Smaller hardware ⇒ less silicon area.

Line 13

"with improvements up to 50% with (m=4,m_C=10)"

Best case:

[
m=4
]

[
m_C=10
]

Area reduction:
[
50%
]

This means the circuit occupies only half the silicon area of the exact MAC.

Line 14

"and up to 34.4% with (m=5) and (m_C=10)"

For:

[
m=5
]

[
m_C=10
]

Area reduction:

[
34.4%
]

Still substantial.

Line 15

"At the same time, an increase of the minimum delay is registered"

There is a trade-off.

Although:

 Area decreases

 Power decreases

the delay increases.

The circuit becomes slightly slower.

Line 16

"due to the multiplexers that realize the shift and the segmentation."

Why does delay increase?

Because additional hardware is introduced:

Segmentation MUXes
Select:

[
A'_{ssm}
]

[
B'_{ssm}
]

[
C'_{ssm}
]

Output Shift MUX

Selects:

[
y_1,y_2,y_3,y_4
]

These multiplexers add extra logic levels.

Example:

Input

MUX

Multiplier

Adder

MUX

Output

Each MUX contributes propagation delay.

Thus:

[
\text{Delay}_{SSMAC}
\text{Delay}_{Exact}
]

even though area and power are lower.

Main Conclusions of This Paragraph

Metric Result

Power saving ((m=4)) 45–66%

Power saving ((m=5)) 16–60%

Best area saving 50%

Effect of segmenting (C) Significant power reduction

Accuracy loss Small

Delay Slightly increased

Reason for delay increase Additional multiplexers for segmentation and shifting

Key Takeaway

The proposed SSMAC achieves large reductions in power (up to ~70%) and area (up to 50%) while
maintaining nearly the same accuracy. The main cost is a small increase in delay due to the extra
multiplexers used for segment selection and output shifting.

This is Table II, which compares the proposed SSMAC with several existing approximate MAC
architectures and an exact MAC.

Understanding Each Column

Column Meaning

MAC type Architecture name

NM Normalized Mean Error

NMED Normalized Mean Error Distance

MRED Mean Relative Error Distance

NmaxED Worst-case normalized error

PRED Probability that RED > 2%

Min Delay Minimum delay (ps)

Area Silicon area (μm²)

Power Power consumption (μW/GHz)

First Row: Exact MAC

Metric Value

Delay 249 ps

Area 218.6 μm²

Power 276.6 μW

This is the reference design.

Since it is exact:

 NM = 0

 NMED = 0

 MRED = 0

 PRED = 0

Kulkarni [10]

Metric Value

NMED (8.11\times10^{-4})

MRED (2.91\times10^{-3})

Delay 224 ps

Area 161.9 μm²

Power 231.1 μW

Compared to exact MAC:

 Delay reduced by 10%

 Area reduced by 25.9%

 Power reduced by 16.4%

Moderate accuracy and moderate savings.

Qiqieh [12] L = 2

Metric Value

NMED (2.06\times10^{-4})

MRED (8.76\times10^{-4})
Metric Value

Delay 208 ps

Area 145 μm²

Power 200 μW

More accurate than Kulkarni and lower power.

Qiqieh [12] L = 4

Increasing (L):

 More approximation

 More savings

Metric Value

NMED (1.91\times10^{-3})

Area 98.78 μm²

Power 152.7 μW

Area reduction:

[
54.8%
]

Power reduction:

[
44.8%
]

But error increases significantly.

Strollo [14] CN

Very accurate design.

Metric Value

NMED (1.66\times10^{-5})

MRED (7.38\times10^{-5})

Almost exact behavior.

However:

 Area reduction only 14.7%

  Power reduction only 8.4%

Strollo [14] CNHYB

Hybrid version.

Metric Value

NMED (2.97\times10^{-5})

MRED (1.42\times10^{-4})

Still extremely accurate.

Power reduction:

[
17.4%
]

Yang [20]

mask = 0

Aggressive approximation.

Metric Value

NMED (1.70\times10^{-3})

Power 173.3 μW

Power saving:

[
37.3%
]

mask = 127

More accurate.

Metric Value

NMED (5.99\times10^{-4})

Power 197.9 μW

Less power saving but better accuracy.

MACISH [21]
ISH_1

Metric Value

NMED (1.36\times10^{-4})

Area 168.1 μm²

Power 235.6 μW

Good accuracy but limited savings.

ISH_2

Uses some exact multipliers.

Accuracy improves further:

[
NMED=7.05\times10^{-4}
]

IBAM [22]

One of the most accurate approximate MACs.

Metric Value

NMED (2.19\times10^{-6})

MRED (1.11\times10^{-5})

Almost exact.

However:

 Area reduction only 16.3%

 Power reduction only 16.2%

Proposed SSMAC Results

Rows beginning with:

SSMAC(...)

are without correction.

Rows beginning with:

SSMAC*(...)

include the correction term (D).

The star (*) means:

Error correction enabled.

SSMAC (m=4)

mC = 10

Without correction:

Metric Value

NMED (3.30\times10^{-3})

Area 109 μm²

Power 94 μW

Power reduction:

[
66%
]

Area reduction:

[
50.1%
]

Largest savings in the table.

mC = 12

Metric Value

NMED (1.60\times10^{-3})

Power 128 μW

Accuracy improves significantly.

Still:

[
53.7%
]

power reduction.

mC = 20

No segmentation of C.
Metric Value

NMED (1.57\times10^{-3})

Power 135.2 μW

Notice:

Accuracy nearly same as (m_C=12).

But power is higher.

This proves segmentation of C is effective.

Effect of Correction

Compare:

Without correction

[
NMED=1.60\times10^{-3}
]

for (m=4,m_C=12)

With correction

[
NMED=6.33\times10^{-4}
]

for (m=4,m_C=12)

Improvement:

[
\frac{1.60-0.633}{1.60}
\approx 60%
]

Similar improvements occur for MRED.

SSMAC (m=5)

Increasing (m):

 Improves accuracy

 Increases area and power

m=5, mC=14
Without correction:

Metric Value

NMED (7.44\times10^{-4})

Power 188.1 μW

With correction:

Metric Value

NMED (3.07\times10^{-4})

Power 210.4 μW

Correction greatly improves accuracy.

Why Delay Increases

Notice:

Exact MAC:

[
249\ ps
]

Some SSMAC designs:

[
275-296\ ps
]

This happens because of:

 Segment-selection multiplexers

 Shift-selection multiplexers

 Error-correction logic

Main Conclusions from Table II

Best Accuracy

 IBAM [22]

 Strollo [14]

They have NMED around:

[
10^{-6}
]
but modest power savings.

Best Power Saving

SSMAC:

[
m=4,;m_C=10
]

Power:

[
94\ \mu W
]

Reduction:

[
66%
]

Best Trade-off

The paper highlights:

SSMAC*(m=4,mC=12)

Metric Value

NMED (6.33\times10^{-4})

Power 135.8 μW

Area 120.1 μm²

because it provides:

 More than 50% power reduction

 More than 45% area reduction

 Significant error reduction due to correction

 Accuracy comparable to many state-of-the-art approximate MACs.

This is Table II, which compares the proposed SSMAC with several existing approximate MAC
architectures and an exact MAC.

Understanding Each Column

Column Meaning

MAC type Architecture name

NM Normalized Mean Error

NMED Normalized Mean Error Distance

MRED Mean Relative Error Distance

NmaxED Worst-case normalized error

PRED Probability that RED > 2%

Min Delay Minimum delay (ps)

Area Silicon area (μm²)

Power Power consumption (μW/GHz)

First Row: Exact MAC

Metric Value

Delay 249 ps

Area 218.6 μm²

Power 276.6 μW

This is the reference design.

Since it is exact:

 NM = 0

 NMED = 0

 MRED = 0

 PRED = 0

Kulkarni [10]

Metric Value

NMED (8.11\times10^{-4})

MRED (2.91\times10^{-3})

Delay 224 ps

Area 161.9 μm²

Power 231.1 μW
Metric Value

Compared to exact MAC:

 Delay reduced by 10%

 Area reduced by 25.9%

 Power reduced by 16.4%

Moderate accuracy and moderate savings.

Qiqieh [12] L = 2

Metric Value

NMED (2.06\times10^{-4})

MRED (8.76\times10^{-4})

Delay 208 ps

Area 145 μm²

Power 200 μW

More accurate than Kulkarni and lower power.

Qiqieh [12] L = 4

Increasing (L):

 More approximation

 More savings

Metric Value

NMED (1.91\times10^{-3})

Area 98.78 μm²

Power 152.7 μW

Area reduction:

[
54.8%
]

Power reduction:
[
44.8%
]

But error increases significantly.

Strollo [14] CN

Very accurate design.

Metric Value

NMED (1.66\times10^{-5})

MRED (7.38\times10^{-5})

Almost exact behavior.

However:

 Area reduction only 14.7%

 Power reduction only 8.4%

Strollo [14] CNHYB

Hybrid version.

Metric Value

NMED (2.97\times10^{-5})

MRED (1.42\times10^{-4})

Still extremely accurate.

Power reduction:

[
17.4%
]

Yang [20]

mask = 0

Aggressive approximation.

Metric Value

NMED (1.70\times10^{-3})

Power 173.3 μW
Metric Value

Power saving:

[
37.3%
]

mask = 127

More accurate.

Metric Value

NMED (5.99\times10^{-4})

Power 197.9 μW

Less power saving but better accuracy.

MACISH [21]

ISH_1

Metric Value

NMED (1.36\times10^{-4})

Area 168.1 μm²

Power 235.6 μW

Good accuracy but limited savings.

ISH_2

Uses some exact multipliers.

Accuracy improves further:

[
NMED=7.05\times10^{-4}
]

IBAM [22]

One of the most accurate approximate MACs.

Metric Value

NMED (2.19\times10^{-6})

MRED (1.11\times10^{-5})

Almost exact.

However:

 Area reduction only 16.3%

 Power reduction only 16.2%

Proposed SSMAC Results

Rows beginning with:

SSMAC(...)

are without correction.

Rows beginning with:

SSMAC*(...)

include the correction term (D).

The star (*) means:

Error correction enabled.

SSMAC (m=4)

mC = 10

Without correction:

Metric Value

NMED (3.30\times10^{-3})

Area 109 μm²

Power 94 μW

Power reduction:

[
66%
]

Area reduction:
[
50.1%
]

Largest savings in the table.

mC = 12

Metric Value

NMED (1.60\times10^{-3})

Power 128 μW

Accuracy improves significantly.

Still:

[
53.7%
]

power reduction.

mC = 20

No segmentation of C.

Metric Value

NMED (1.57\times10^{-3})

Power 135.2 μW

Notice:

Accuracy nearly same as (m_C=12).

But power is higher.

This proves segmentation of C is effective.

Effect of Correction

Compare:

Without correction

[
NMED=1.60\times10^{-3}
]

for (m=4,m_C=12)
With correction

[
NMED=6.33\times10^{-4}
]

for (m=4,m_C=12)

Improvement:

[
\frac{1.60-0.633}{1.60}
\approx 60%
]

Similar improvements occur for MRED.

SSMAC (m=5)

Increasing (m):

 Improves accuracy

 Increases area and power

m=5, mC=14

Without correction:

Metric Value

NMED (7.44\times10^{-4})

Power 188.1 μW

With correction:

Metric Value

NMED (3.07\times10^{-4})

Power 210.4 μW

Correction greatly improves accuracy.

Why Delay Increases

Notice:

Exact MAC:
[
249\ ps
]

Some SSMAC designs:

[
275-296\ ps
]

This happens because of:

 Segment-selection multiplexers

 Shift-selection multiplexers

 Error-correction logic

Main Conclusions from Table II

Best Accuracy

 IBAM [22]

 Strollo [14]

They have NMED around:

[
10^{-6}
]

but modest power savings.

Best Power Saving

SSMAC:

[
m=4,;m_C=10
]

Power:

[
94\ \mu W
]

Reduction:

[
66%
]
Best Trade-off

The paper highlights:

SSMAC*(m=4,mC=12)

Metric Value

NMED (6.33\times10^{-4})

Power 135.8 μW

Area 120.1 μm²

because it provides:

 More than 50% power reduction

 More than 45% area reduction

 Significant error reduction due to correction

 Accuracy comparable to many state-of-the-art approximate MACs.

This paragraph explains the trade-off between accuracy and power saving shown in Figure 7.

Figure 7 Caption

"Tradeoff between (a) power saving and NMED and (b) power saving and MRED for (n=8, n_C=20)
bits."

The figure compares MAC architectures using:

 Power Saving (%)

 NMED (Normalized Mean Error Distance)

 MRED (Mean Relative Error Distance)

for:

[
n=8,\quad n_C=20
]

Line 1

"To put results in perspective, the Fig. 7 represents the trade-off between power saving and the
metrics NMED and MRED."

The authors want to compare:

Benefit
[
\text{Power Saving}
]

against

Cost

[
\text{Error (NMED, MRED)}
]

Every approximate MAC reduces power, but usually increases error.

Figure 7 visualizes this balance.

Line 2

"For the sake of simplicity, we focus our attention on the case with (n=8, n_C=20)."

Only one configuration is plotted:

[
n=8
]

[
n_C=20
]

to make the comparison easier.

Line 3

"since the MACs with (n_C=24) offer a comparable behavior both in terms of power and error
metrics."

The authors observed that:

[
n_C=24
]

shows nearly the same trend.

Therefore showing both figures would be redundant.

Line 4

"In the plots of Fig. 7, the optimal point is located in the top-left corner"

This is the key idea.

X-axis

Error metric

(NMED or MRED)

Smaller is better.

Y-axis

Power saving

Larger is better.

Therefore the ideal design is:

High Power Saving

Top Left ● ← Ideal

+----------------→ Error

Small Large

Top-left means:

 Maximum power reduction

 Minimum error

Line 5

"corresponding to better precision and larger power reduction."

Why top-left?

Because:

Left

[
\text{Error} \rightarrow \text{Small}
]

Higher accuracy.
Top

[
\text{Power Saving} \rightarrow \text{Large}
]

Lower energy consumption.

Line 6

"As shown, the proposed SSMACs exhibit a favorable trade-off between accuracy and power"

The proposed SSMAC points appear close to the desirable region.

This means:

 Good accuracy

 Large power savings

simultaneously.

Line 7

"defining the Pareto front for NMED > 5\times10^{-4} and MRED > 3\times10^{-3}."

What is a Pareto Front?

A design belongs to the Pareto front if:

No other design is simultaneously better in both objectives.

In this paper:

Objectives are:

1. Lower error

2. Higher power saving

Example:

Design Error Power Saving

A 0.001 50%

B 0.001 40%

A dominates B.

So B is not Pareto-optimal.
The paper says that for:

[
NMED > 5\times10^{-4}
]

or

[
MRED > 3\times10^{-3}
]

the proposed SSMACs lie on the Pareto frontier.

Meaning:

No competing design offers both:

 lower error

 and higher power saving

at the same time.

Line 8

"In this region, the proposed MACs overcome the designs of [10], [20] and [21]"

Compared with:

 Kulkarni [10]

 Yang [20]

 MACISH [21]

the SSMAC achieves:

 Similar or better accuracy

 Higher power savings

Therefore SSMAC is preferable.

Line 9

"which achieve comparable error metrics with a lower power saving."

Those previous designs may have similar:

[
NMED
]

and
[
MRED
]

but they save less power.

Example:

Design Error Power Saving

Previous MAC Same 35%

SSMAC Same 60%

SSMAC is clearly better.

Line 10

"The figure highlights also that the MACs [14] and [22] offer the best accuracy"

The architectures:

 Strollo [14]

 IBAM [22]

have the smallest errors.

Their NMED values are around:

[
10^{-6}
]

which is much better than SSMAC.

Line 11

"at the cost of a reduced power improvement (limited around 20%)."

However, they save much less power.

Typical power reduction:

[
10%-20%
]

only.

Thus:

Very Accurate

but
Less Energy Efficient

Final Conclusion

"Therefore, the proposed SSMACs are good candidates..."

The authors conclude:

If the goal is

 Maximum accuracy

choose:

 Strollo [14]

 IBAM [22]

If the goal is

 Strong power reduction

 Reasonable accuracy

choose:

 SSMAC

because it provides the best overall trade-off.

Visual Summary

Power Saving

SSMACs ●

[10],[20],[21]

[14],[22]
 ●

----------------------------------------→ Error

Low High

 Upper-left = best trade-off.

 SSMACs occupy much of this region.

 [14] and [22] are far left (excellent accuracy) but lower on the graph (less power saving).

 [10], [20], [21] have similar error to SSMAC but lower power savings, so they are
dominated by SSMAC in many operating points.

Let's explain this section line by line.

Section V: Applications

This section evaluates the proposed SSMAC in a real-world application rather than only using
mathematical error metrics.

A. Image Filtering

Image filtering is used for:

 Noise removal

 Blurring

 Smoothing

 Motion effects

 Edge detection

Since image filtering performs a large number of:

[
A\times B + C
]

operations, it is a good application for testing approximate MACs.

Line 1

"The MACs performances are investigated in image filtering applications"

The authors test the MAC architectures inside image-processing filters.

Instead of measuring only:

  NMED

 MRED

they observe actual image quality.

Line 2

"by using two kernels"

Two different filter masks (kernels) are used.

A kernel is a small matrix that slides over an image.

Example:

[
\begin{bmatrix}
1 & 2 & 1\
2 & 4 & 2\
1&2&1
\end{bmatrix}
]

Each kernel requires many MAC operations.

Line 3

"the first one is a Gaussian low-pass filter with size 5 and standard deviation 2"

Gaussian Filter

A Gaussian filter smooths the image.

Characteristics:

 Kernel size = 5×5

 Standard deviation:

[
\sigma = 2
]

Purpose

Removes:

 Noise

 Fine details

Produces a blurred image.

Example:

Original Image

Gaussian Filter

Smooth Image

Line 4

"while the second kernel approximates the linear motion of a camera by 10 pixels, with an angle of
25 degrees."

The second filter simulates:

Motion Blur

Parameters:

 Motion length = 10 pixels

 Direction = 25°

This mimics a camera moving while taking a picture.

Example:

Camera movement

Motion blur filter

Blurred image

Line 5

"The Table IV shows the performances in terms of mean structural similarity index (SSIM) and peak
signal-to-noise ratio (PSNR) in dB"

Image quality is measured using:

SSIM

Structural Similarity Index

PSNR

Peak Signal-to-Noise Ratio

What is SSIM?

SSIM compares:

 Brightness

 Contrast

 Structure

between two images.

Range:

[
0 \le SSIM \le 1
]

where:

 1 = identical images

 0 = completely different

Example

SSIM Quality

1.00 Perfect

0.99 Excellent

0.95 Very good

0.90 Acceptable

<0.80 Noticeable degradation

What is PSNR?

PSNR measures error between images.

Higher is better.

Typical values:

PSNR Quality

>40 dB Excellent

30–40 dB Good

20–30 dB Noticeable distortion

<20 dB Poor
Line 6

"having considered MACs with (n=8) and (n_C=20) bits."

The image-filtering experiments use:

[
n=8
]

and

[
n_C=20
]

which are the same settings used earlier in the paper.

Line 7

"Here, we report the average values of SSIM and PSNR obtained by processing two test images,
'Lena' and 'Cameraman'."

Two standard benchmark images are used.

Lena

Widely used image-processing test image.

Cameraman

Another standard grayscale benchmark image.

These are common in image-processing research.

Line 8

"The last column of Table IV reports the overall average SSIM and PSNR."

Table IV contains:

 Results for Lena

 Results for Cameraman

and then computes:

[
\text{Average SSIM}
]

and
[
\text{Average PSNR}
]

across both images.

Line 9

"The proposed SSMACs with correction perform quite well in this application"

The correction term:

[
D
]

improves image quality significantly.

The corrected SSMAC produces filtered images very close to those obtained using the exact MAC.

Line 10

"exhibiting an average SSIM larger than 0.92 for all the investigated configurations"

For every corrected SSMAC tested:

[
SSIM > 0.92
]

This means:

 Very good image similarity

 Visual quality remains high

Line 11

"and SSIM larger than 0.98 for (m_C \ge 12)."

When:

[
m_C \ge 12
]

the similarity becomes:

[
SSIM > 0.98
]
which is extremely close to the exact result.

Most users would not notice any difference.

Line 12

"The average PSNR is up to 34.4 dB with (m=4)"

For some configurations:

[
PSNR = 34.4; dB
]

This is considered good image quality.

Distortion is relatively small.

Line 13

"and overcomes 41 dB with (m=5) and (m_C \ge 14)."

For:

[
m=5
]

and

[
m_C \ge 14
]

the quality becomes:

[
PSNR > 41; dB
]

This is excellent.

Many image-processing systems consider:

[
40; dB
]

to be visually lossless.

Line 14
"The SSMACs without correction, on the other hand, show a lower SSIM that is smaller than 0.9 for
(m_C=10)."

Without correction:

[
D=0
]

the image quality drops.

For:

[
m_C=10
]

the SSIM becomes:

[
SSIM < 0.9
]

This indicates noticeable image degradation.

Line 15

"The other investigated MACs also show very good performance"

Other approximate MAC architectures also produce acceptable image quality.

Line 16

"with the partial exceptions of [20] mask = 0 (SSIM about 0.88 and PSNR about 20 dB)"

Reference [20] with:

[
mask=0
]

performs poorly.

Results:

[
SSIM \approx 0.88
]

[
PSNR \approx 20 dB
]

These values indicate visible image degradation.

Line 17

"and [12] L = 4 ..."

Reference [12] with:

[
L=4
]

also experiences reduced image quality because of stronger approximation.

(The sentence continues beyond the cropped image.)

Main Conclusions of This Section

Observation Result

Corrected SSMAC Very good image quality

SSIM > 0.92 for all corrected designs

SSIM ((m_C \ge 12)) > 0.98

PSNR ((m=5,m_C\ge14)) > 41 dB

Effect of correction Major quality improvement

Without correction SSIM may drop below 0.9

Best visual quality Larger (m) and larger (m_C)

Poor competitors [20] mask=0 and [12] L=4

Key Takeaway

The proposed SSMAC with error correction achieves substantial power and area savings while still
maintaining excellent image quality (SSIM > 0.98 and PSNR > 41 dB in the best configurations),
making it suitable for practical image-filtering applications.

Let's explain this paragraph line by line.

Line 1

"PSNR about 27 dB."

This refers to the architecture discussed just before this paragraph (Qiqieh [12], (L=4)).

A PSNR of:
[
27\text{ dB}
]

means:

 Image quality is acceptable.

 Distortion is noticeable.

 Much worse than high-quality results (>40 dB).

Typical interpretation:

PSNR Quality

>40 dB Excellent

30–40 dB Good

20–30 dB Moderate

<20 dB Poor

So 27 dB is only moderate quality.

Line 2

"The IBAM MAC [22] shows a remarkably good behavior, with SSIM about 1 and PSNR larger than
67 dB."

IBAM [22] performs extremely well.

SSIM ≈ 1

[
SSIM \approx 1
]

means the filtered image is almost identical to the exact image.

PSNR > 67 dB

[
PSNR > 67\text{ dB}
]

is extraordinarily high.

For comparison:

PSNR Meaning

40 dB Excellent
PSNR Meaning

50 dB Nearly perfect

67 dB Practically indistinguishable from exact

Thus IBAM is almost exact.

Line 3

"The Fig. 8 shows some examples of Gaussian filtered Cameraman image."

Figure 8 contains visual examples.

The test image is:

Cameraman

and the filter applied is:

Gaussian low-pass filter

The purpose is to visually compare image quality.

Line 4

"The images computed with the proposed SSMACs without correction and (m=4, m_C=12,20) show
a slight degradation in the background."

Configurations:

[
m=4
]

[
m_C=12
]

or

[
m_C=20
]

without correction.

Observation

Small artifacts appear in the image background.

This happens because:

  Some partial products are discarded.

 Error compensation is disabled.

The degradation is described as slight, meaning it is visible but not severe.

Line 5

"The images obtained using the SSMACs with the correction technique are instead very close to
the exact case."

Now the correction term:

[
D
]

is enabled.

Result:

 Visual artifacts nearly disappear.

 Filtered image becomes very similar to the exact MAC output.

This confirms that the correction technique is effective.

Line 6

"The SSMAC without correction and (m=5, m_C=14,20) yield acceptable results."

Configurations:

[
m=5
]

[
m_C=14
]

or

[
m_C=20
]

without correction.

Why Better?

Because:
  Larger (m) means more multiplier bits retained.

 Larger (m_C) means more accumulator bits retained.

Therefore:

[
\text{Error} \downarrow
]

and image quality improves.

Even without correction, results are considered acceptable.

Power vs Image Quality

Line 7

"In order to compare the power performances with the accuracy, we plot in Fig. 9 the power
saving with respect to the average PSNR."

Figure 9 compares:

X-axis

Average PSNR

(image quality)

Y-axis

Power saving

This allows evaluation of the trade-off:

Better Quality

+----------------→ More Power Saving

Line 8

"In order to simplify the visualization, we have included in this Figure only the corrected SSMACs"

Figure 9 shows only:

[
SSMAC^*
]

(corrected versions).

Reason:

These have the best accuracy.

Showing non-corrected versions would clutter the graph.

Line 9

"(which give the best behavior, as pointed out above)."

The corrected SSMACs consistently outperform the non-corrected ones.

They achieve:

 Higher SSIM

 Higher PSNR

 Similar power savings

Line 10

"As it can be observed, the proposed SSMACs with (m=4,m_C=12,20) and (m=5,m_C=12) offer the
best trade-off between power and quality of results"

The authors identify the most attractive designs.

Recommended configurations

1.

[
m=4,\quad m_C=12
]

2.

[
m=4,\quad m_C=20
]

3.

[
m=5,\quad m_C=12
]
These configurations balance:

 Image quality

 Power consumption

better than the others.

Line 11

"giving an acceptable PSNR (between 30 and 35 dB)"

These designs achieve:

[
30 \le PSNR \le 35 \text{ dB}
]

This corresponds to:

 Good image quality

 Small visible distortion

Suitable for many practical image-processing applications.

Line 12

"with a remarkable power reduction (larger than 40%)."

At the same time:

[
\text{Power Saving} > 40%
]

This is the main advantage.

Compared with the exact MAC:

 Image quality remains good.

 Power consumption is reduced nearly by half.

Section B: Template Matching

Now the paper evaluates another application.

Line 13

"Template matching is a method for finding the location of a template image in a larger image"
Template matching is a computer vision technique.

Goal:

Find where a small image appears inside a larger image.

Example:

Large Image

+----------------+

| |

| FACE |

| |

+----------------+

Template

+------+

| FACE |

+------+

The algorithm searches for the face inside the large image.

Line 14

"and is a common task in several applications."

Applications include:

 Face detection

 Object recognition

 Industrial inspection

 Medical imaging

 Robot vision

Line 15

"The basic algorithm involves sliding the template over the given image."

The template moves pixel by pixel:

Position 1

Position 2
Position 3

...

across the entire image.

Line 16

"At each position the template and the patch of the input image under the template are
compared."

For every position:

 Take image patch

 Compare it with template

This comparison requires many:

[
A\times B + C
]

operations.

Therefore MAC accuracy directly affects matching accuracy.

Line 17

"The algorithm then selects the position with the maximum..."

The sentence continues on the next page.

The intended meaning is:

The algorithm computes a similarity score at every position and chooses the position with the
highest similarity (maximum correlation) as the detected location of the template.

Main Takeaways

Image Filtering Results

Configuration Result

Corrected SSMAC Very close to exact image

(m=4,m_C=12) Good quality

(m=5,m_C=14) Good quality even without correction

IBAM [22] Nearly perfect (SSIM≈1, PSNR>67 dB)

Best SSMAC trade-off (m=4,m_C=12), (m=4,m_C=20), (m=5,m_C=12)

Configuration Result

Power saving >40%

PSNR 30–35 dB

Template Matching

Template matching searches for a small image inside a larger image by sliding the template and
computing similarity scores using many MAC operations, making it another suitable application for
evaluating the proposed SSMAC.

Let's explain Figure 9 and Equation (28) line by line.

Figure 9: Power Saving vs Average PSNR

Caption:

"Power saving versus average PSNR for image filtering applications."

This figure compares:

 Image quality (PSNR)

 Power saving

for all MAC architectures.

Axes

X-axis

Average PSNR (dB)

Left -----------------> Right

Low quality High quality

Higher PSNR = better image quality.

Y-axis

Power Saving (%)

Bottom ---------------> Top

Low saving High saving

Higher means less power consumption.

Ideal Location
The best point is:

Top Right Corner

because it means:

 High PSNR

 High power saving

Points in Figure

IBAM (VBL=3)

Located around:

PSNR ≈ 67 dB

Power saving ≈ 16%

Meaning:

 Excellent image quality

 Small power reduction

Almost exact behavior.

CN and CNHYB ([14])

Around:

PSNR ≈ 60 dB

Power saving ≈ 10–20%

Very accurate but limited power savings.

Kulkarni [10]

Around:

PSNR ≈ 45 dB

Power saving ≈ 15%

Good quality but not much energy saving.

MACISH

Around:
PSNR ≈ 40–43 dB

Power saving ≈ 10%

Moderate trade-off.

Yang [20]

mask=0

PSNR ≈ 20 dB

Power saving ≈ 37%

Large power saving but poor image quality.

mask=127

PSNR ≈ 35 dB

Power saving ≈ 27%

Better accuracy but less power saving.

Proposed SSMAC*

Black × symbols are corrected SSMACs.

Labels:

4,10

4,12

4,20

5,12

5,14

5,20

mean:

[
(m,m_C)
]

SSMAC*(4,10)

Approximately:

PSNR ≈ 25 dB
Power saving ≈ 60%

Huge power reduction.

Quality somewhat lower.

SSMAC*(4,12)

Approximately:

PSNR ≈ 35 dB

Power saving ≈ 50%

Excellent trade-off.

SSMAC*(4,20)

Approximately:

PSNR ≈ 37 dB

Power saving ≈ 45%

Very good quality and large power saving.

SSMAC*(5,12)

Approximately:

PSNR ≈ 38 dB

Power saving ≈ 40%

One of the best trade-offs.

SSMAC*(5,14)

Approximately:

PSNR ≈ 45 dB

Power saving ≈ 25%

Better image quality but reduced power saving.

Conclusion from Figure 9

The authors conclude:

Best trade-off
  SSMAC*(4,12)

 SSMAC*(4,20)

 SSMAC*(5,12)

because they provide:

PSNR = 30–35+ dB

Power Saving > 40%

No competing architecture achieves such a balance.

Template Matching Section

Line

"similarity as the location of the template within the image."

The template matching algorithm computes a similarity score.

The location with the highest score is assumed to contain the template.

Line

"Several comparison methods can be employed."

There are many matching metrics:

 Correlation

 Covariance

 SAD (Sum of Absolute Differences)

 SSD (Sum of Squared Differences)

 Normalized Cross Correlation

Line

"In our experiment, we used the covariance (corresponding to TM_CCOEFF mode in OpenCV)."

The authors use OpenCV's:

[
TM_CCOEFF
]

matching method.

This is based on covariance.

It measures how strongly two image patches vary together.

Equation (28)

The covariance score is:

[
C(x,y)=
\sum_{i=0}^{d_1-1}
\sum_{j=0}^{d_2-1}
\left(I(x-i,y-j)-\mu_I\right)
\left(T(i,j)-\mu_T\right)
]

Meaning of Symbols

(T(i,j))

Template pixel.

Small image being searched.

(I(x-i,y-j))

Pixel of the large image currently under the template.

(\mu_T)

Mean pixel value of template.

[
\mu_T=
\frac{1}{d_1d_2}
\sum T(i,j)
]

(\mu_I)

Mean pixel value of current image patch.

[
\mu_I=
\frac{1}{d_1d_2}
\sum I(x-i,y-j)
]
(d_1)

Template width.

(d_2)

Template height.

What Equation (28) Does

For every template position:

Step 1

Subtract average brightness

[
T(i,j)-\mu_T
]

[
I(x-i,y-j)-\mu_I
]

This removes illumination effects.

Step 2

Multiply corresponding pixels.

Step 3

Sum all products.

Result:

[
C(x,y)
]

Interpretation of (C(x,y))

Large Positive Value

Template matches well.

[
C(x,y)\gg0
]

Near Zero

Weak similarity.

[
C(x,y)\approx0
]

Negative Value

Poor match.

Example

Suppose:

Template:

10 20

20 30

Image patch:

11 19

22 31

After mean subtraction the patterns are very similar.

Therefore:

[
C(x,y)
]

will be large and positive.

The algorithm declares this location as a match.

Why MAC Accuracy Matters

Equation (28) contains many:

[
(I-\mu_I)(T-\mu_T)
]
multiplications and additions.

Therefore template matching performs thousands of:

[
A\times B + C
]

operations.

If the MAC introduces too much error:

 Correlation values become inaccurate.

 Wrong template locations may be selected.

The purpose of this section is to show that the proposed SSMAC still performs template matching
accurately while consuming much less power.

This is Table V: MAC Results for Template Matching.

The table evaluates how different approximate MAC architectures perform in a template matching
application.

Columns Meaning

Column Meaning

MAC type Architecture tested

PSNR [dB] Image quality compared to exact result

Correct match Whether the template location was found correctly

What Does "Correct Match" Mean?

Template matching computes a correlation score:

[
C(x,y)
]

for every image position.

The position with the largest score is selected.

"yes"

The approximate MAC found exactly the same template location as the exact MAC.

"no"

The approximation error caused the algorithm to select the wrong location.

This is more important than PSNR because template matching is a decision-making task.
Analysis of Each MAC

Kulkarni [10]

PSNR Correct Match

49.6 dB No

Although PSNR is high, the correlation values were distorted enough to produce an incorrect
template location.

Qiqieh [12], L=2

PSNR Correct Match

63.7 dB Yes

Very good quality.

Correct template location found.

Qiqieh [12], L=4

PSNR Correct Match

49.2 dB No

Increasing (L):

 More approximation

 More error

The matching result becomes incorrect.

Strollo [14] CN

PSNR Correct Match

75.8 dB Yes

Excellent result.

Very close to exact MAC.

Strollo [14] CNHYB

PSNR Correct Match

59.5 dB Yes
PSNR Correct Match

Still accurate enough for correct matching.

Yang [20]

mask = 0

PSNR Correct Match

55.7 dB Yes

Even though it is highly approximate, it still finds the correct location.

mask = 127

PSNR Correct Match

61.2 dB Yes

More accurate and also correct.

MACISH

ISH_1

PSNR Correct Match

49.1 dB No

Incorrect template location.

ISH_2

PSNR Correct Match

50.0 dB Yes

Adding exact multipliers improves matching accuracy.

IBAM [22]

PSNR Correct Match

90.2 dB Yes

Best result in the table.

Practically identical to exact computation.

Proposed SSMAC (Without Correction)

(m=4, m_C=12)

PSNR Correct Match

49.7 dB No

Too much approximation.

Wrong template position selected.

(m=4, m_C=14)

PSNR Correct Match

50.8 dB Yes

Keeping more bits improves accuracy enough to obtain the correct match.

(m=4, m_C=24)

PSNR Correct Match

60.3 dB Yes

Excellent matching performance.

Corrected SSMAC* (m=4)

(m=4, m_C=12)

PSNR Correct Match

49.7 dB No

Interesting observation:

The correction improves many error metrics but still doesn't recover the correct match in this
configuration.

(m=4, m_C=14)
PSNR Correct Match

58.2 dB Yes

Correction significantly improves quality.

(m=4, m_C=24)

PSNR Correct Match

63.5 dB Yes

Very good performance.

Proposed SSMAC (m=5)

(m=5, m_C=12)

PSNR Correct Match

49.7 dB No

Again, too aggressive approximation.

(m=5, m_C=14)

PSNR Correct Match

50.8 dB Yes

Correct match obtained.

(m=5, m_C=16)

PSNR Correct Match

60.2 dB Yes

High-quality result.

(m=5, m_C=24)

PSNR Correct Match

65.9 dB Yes

Very accurate.
Corrected SSMAC* (m=5)

(m=5, m_C=12)

PSNR Correct Match

49.7 dB No

Still insufficient.

(m=5, m_C=14)

PSNR Correct Match

58.4 dB Yes

Correction improves PSNR significantly.

(m=5, m_C=16)

PSNR Correct Match

63.6 dB Yes

Very good.

(m=5, m_C=24)

PSNR Correct Match

71.7 dB Yes

One of the best SSMAC results.

Important Observation

Notice a pattern:

When (m_C=12)

All SSMAC versions show:

Correct Match = No

because too many bits of operand (C) are discarded.

When (m_C \ge 14)

Almost all SSMAC configurations show:

Correct Match = Yes

Thus:

[
m_C = 14
]

appears to be the minimum practical value for reliable template matching.

Main Conclusions from Table V

Best Overall Accuracy

Architecture PSNR

IBAM [22] 90.2 dB

Strollo CN 75.8 dB

SSMAC*(m=5,mC=24) 71.7 dB

Minimum SSMAC Configuration That Works Reliably

[
m_C \ge 14
]

This is the key design recommendation from the table.

Effect of Correction

For example:

[
m=4,;m_C=14
]

PSNR improves:

[
50.8 \rightarrow 58.2\text{ dB}
]

and
[
m=5,;m_C=14
]

improves:

[
50.8 \rightarrow 58.4\text{ dB}
]

showing that the correction term significantly improves template-matching quality.

Final Takeaway

The proposed SSMAC can successfully perform template matching with large power savings,
provided that at least 14 bits of operand (C) are retained. The error-correction technique further
improves PSNR by roughly 7–8 dB, making the approximate MAC suitable for practical vision
applications.

Let's explain Figure 10 and the paragraph below it line by line.

Figure 10

Caption:

"(a) 'Onion' template and (b) 'Peppers' image and template matching for three different
approximate MACs."

This figure demonstrates the template matching application discussed in the previous section.

Figure 10(a)

The small image on the left is the template.

It is an image of an onion.

Template

Onion

This is the pattern the algorithm is trying to locate inside the larger image.

Figure 10(b)

The larger image is the well-known Peppers test image.

The template-matching algorithm searches this image for the onion.

Three rectangles are shown:

Yellow Rectangle
Label:

[
\text{SSMAC}(m=4,m_C=14)
]

and

[
\text{SSMAC}^*(m=4,m_C=14)
]

Both approximate MACs correctly identify the onion.

The yellow box is positioned on the actual onion.

Cyan Rectangle

Label:

[
\text{MACISH}_1
]

This architecture identifies a wrong location.

The cyan rectangle is not centered on the onion.

This corresponds to:

Correct Match = No

in Table V.

Why This Figure Is Important

The figure visually demonstrates that:

Correct Matching

SSMAC

Finds Onion

Incorrect Matching

MACISH1

Wrong Position
Even if two architectures have similar PSNR values, one may still fail the matching task.

Therefore:

Correct Match

is a more meaningful metric than PSNR alone.

Paragraph Below Figure 10

Line 1

"MACs with (n=8) and (n_C=24) bits are employed to perform the sum of products in (28)."

The template-matching experiment uses:

[
n=8
]

for multiplier inputs

and

[
n_C=24
]

for the accumulator.

The MAC computes Equation (28):

[
C(x,y)

\sum
(I-\mu_I)(T-\mu_T)
]

which requires many multiplications and additions.

Line 2

"The Table V collects the obtained results."

Table V summarizes:

 PSNR

 Correct match status

for all MAC architectures.

Line 3

"The second column reports the PSNR computed by comparing the covariance (C(x,y)) obtained
with the exact calculation with the one computed with the approximate MACs."

The PSNR is not computed from images here.

Instead it is computed from the correlation maps:

[
C(x,y)
]

generated by:

Exact MAC

[
C_{exact}(x,y)
]

and

Approximate MAC

[
C_{approx}(x,y)
]

The closer they are, the higher the PSNR.

Line 4

"As shown, the proposed segmented MACs are able to offer a PSNR up to 60 dB without error
correction"

Without correction:

[
D=0
]

the proposed SSMAC can still achieve:

[
PSNR \approx 60\text{ dB}
]

This indicates very good agreement with the exact covariance computation.

From Table V:

Example:
[‘

gives:

[
60.2\text{ dB}
]

Line 5

"whereas the performance improves up to 71 dB with the correction factor."

When correction is enabled:

[
D \neq 0
]

accuracy improves further.

Example:

[
SSMAC^*(m=5,m_C=24)
]

achieves:

[
71.7\text{ dB}
]

which is extremely high.

Line 6

"Implementations [14] CN and [22] offer the best PSNR"

The best-performing architectures are:

Strollo CN [14]

PSNR:

[
75.8\text{ dB}
]

IBAM [22]

PSNR:
[
90.2\text{ dB}
]

These are the closest to exact computation.

Line 7

"whereas [12] (L=4) and [21] ISH_1 show worse performance."

The poorest performers are:

Qiqieh [12], (L=4)

PSNR:

[
49.2\text{ dB}
]

and

MACISH(_1)

PSNR:

[
49.1\text{ dB}
]

These also failed the template-matching task in Table V.

Connection Between Table V and Figure 10

Figure 10 directly illustrates the results from Table V:

Architecture PSNR Correct Match

SSMAC(m=4,mC=14) 50.8 dB Yes

SSMAC*(m=4,mC=14) 58.2 dB Yes

MACISH(_1) 49.1 dB No

Although the PSNR values are fairly close, only the SSMAC architectures correctly locate the onion.

Main Takeaway

Figure 10 demonstrates that the proposed SSMAC, especially with error correction:

 Correctly locates the template.

 Produces covariance maps very close to the exact MAC.

  Achieves PSNR values up to 71 dB.

 Outperforms some competing approximate MACs in practical template-matching tasks

while still providing substantial power and area savings.

Let's explain this final section line by line.

Template Matching Results

Line 1

"The third column in Table V reports whether a correct match has been obtained or not."

Table V contains three columns:

MAC Type PSNR Correct Match

The third column simply indicates:

Yes

The template was found at the correct location.

No

The template was found at the wrong location.

Line 2

"It can be observed that all the SSMACs allow to obtain a correct match"

The proposed SSMAC architectures generally succeed in locating the template correctly.

This means the approximation error is not large enough to alter the position of the maximum
correlation.

Line 3

"with the exception of the two versions with: (m=4,m_C=12) and (m=5,m_C=12)."

Only two configurations fail:

Configuration 1

[
m=4,\quad m_C=12
]

Configuration 2

[
m=5,\quad m_C=12
]
These use the smallest (m_C) value.

Since more bits of operand (C) are discarded:

[
\text{Error} \uparrow
]

and the matching result becomes incorrect.

Line 4

"The architectures [12] L=4, [21] ISH_1 and Kulkarni [10] are also unable to obtain the right
match."

Three competing architectures also fail:

Qiqieh [12]

[
L=4
]

MACISH(_1)

Reference [21]

Kulkarni [10]

These architectures produce enough error to move the correlation peak away from the correct
location.

Line 5

"The Fig. 10(b) represents the obtained matching for SSMAC(4,14), SSMAC(4,14), and [21] ISH_1."*

Figure 10 visually compares:

SSMAC(4,14)

Correct match.

SSMAC*(4,14)

Correct match with error correction.

MACISH(_1)
Incorrect match.

The figure demonstrates the practical effect of approximation errors.

Section VI: Conclusion

This is the summary of the entire paper.

Line 6

"In this paper we have proposed a novel approximate multiply-and-accumulate unit"

The main contribution is a new:

Approximate MAC

(Multiply-Accumulate)

architecture.

Line 7

"that computes (Y=A\times B+C) using static segmentation."

The MAC computes:

[
Y=A\times B+C
]

but instead of using all bits:

 A is segmented

 B is segmented

 C is segmented

Only selected segments are processed.

This is called:

Static Segmentation

because the segmentation pattern is fixed by design parameters.

Line 8

"The developed architecture uses a unique carry-propagate adder"

Most approximate MACs focus mainly on the multiplier.

This architecture also modifies the accumulator path.

A specialized carry-propagate adder is used.

Line 9

"and performs segmentation on the three operands"

Unlike previous approaches:

Operand A

Segmented

Operand B

Segmented

Operand C

Segmented

This is one of the paper's main innovations.

Line 10

"by using a reduced word length adder."

Since only part of (C) is used:

The adder width can be reduced.

Example:

Instead of:

[
20\text{-bit adder}
]

they may use:

[
12\text{-bit adder}
]

or

[
14\text{-bit adder}
]

which saves:

 Area

 Power
Line 11

"A correction technique is also proposed for recovering precision."

The paper introduces the correction term:

[
D
]

which:

 Estimates discarded partial products.

 Reduces approximation error.

Line 12

"The proposed circuit can be configured at design-time by two parameters."

The architecture is tunable.

Two parameters determine the trade-off between:

 Accuracy

 Area

 Power

Line 13

"The first one controls the segmentation on A and B"

Parameter:

[
m
]

controls how many bits are retained from:

 A

 B

Larger (m):

 Better accuracy

 More hardware

Smaller (m):
  Lower power

 More error

Line 14

"while the second one controls the segmentation on C and the adder length."

Parameter:

[
m_C
]

controls:

Number of retained bits of C

and

Adder width

Larger (m_C):

 Higher accuracy

 Larger adder

Smaller (m_C):

 Lower power

 Smaller area

Line 15

"Analysis of error metrics and VLSI synthesis results in 28 nm CMOS technology are presented."

The authors evaluated:

Accuracy

using:

 NM

 NMED

 MRED

 PRED

Hardware Cost

using:
  Delay

 Area

 Power

in:

[
28\text{ nm CMOS}
]

technology.

Line 16

"The obtained results show that the proposed approximate MACs outperform the state of the art"

The authors claim that their design performs better than existing approximate MACs.

Not necessarily in every metric individually,

but in overall trade-off.

Line 17

"exhibiting a favorable trade-off between accuracy and power consumption."

This is the central conclusion.

The proposed SSMAC achieves:

Large Power Savings

Up to approximately:

[
66%
]

Large Area Savings

Up to approximately:

[
50%
]

While Maintaining

 Good NMED
  Good MRED

 Good image quality

 Correct template matching

Line 18

"Application examples to image filtering and template matching confirm"

The authors tested the design in two practical applications:

Image Filtering

Gaussian blur

Motion blur

Template Matching

Object detection using correlation.

Line 19

"that proposed circuits are good candidates in applications where their error performances are
acceptable."

The final message is:

The SSMAC should be used in applications that can tolerate a small amount of error.

Examples:

✅ Image processing

✅ Computer vision

✅ Multimedia systems

✅ Machine learning accelerators

Not ideal for:

❌ Financial calculations

❌ Cryptography

❌ Scientific computations requiring exact arithmetic

Overall Summary of the Paper

The paper proposes a Static Segmented MAC (SSMAC) that:

1. Segments operands A, B, and C.

2. Uses a smaller adder by truncating part of C.

3. Introduces an error-correction term D.

4. Is controlled by two design parameters:

o (m) (segmentation of A and B)

o (m_C) (segmentation of C and adder width)

5. Achieves:

o Up to 66% power reduction

o Up to 50% area reduction

o Significant error reduction through correction

6. Maintains good performance in:

o Image filtering

o Template matching

The authors conclude that the proposed SSMAC offers one of the best accuracy–power trade-offs
among the approximate MAC architectures they evaluated.