PCI Express Overview

- Shivappa K M
Introduction
PCI and PCIe History

PCI Express 5.0 2019

PCIe 4.0

PCIe 3.0 2017

PCIe 2.0 2010

PCIe 1.0 2007

PCI 2.3, 3.0 2003
PCI-X 1.0b, 2.0
2001
PCI-X 1.0 • Hot Plug 1.1
1999 • Mini PCI
PCI 2.2
1998
• PCI Hot Plug 1.0

PCI 2.1
• 66 MHz 3.3v
1994
PCI 2.0
• PCI Power Management
1993
PCI 1.0
1992
• PCI Plug and Play Configuration Model
What is wrong with PCI?
What is wrong with PCI?

Bandwidth
Multi-drop bus limits
Frequency
Large pin-count causes board
routing problems
No Quality of Service (QoS)
Limited Power Management
Capabilities
Limited Reliability,
Availability, Serviceability
Scalability for different market
segments and applications
Ease of use
Bus architecture
CPU

Bridge/
Memory
controller

PCI Bus

Legacy/expansion Graphics controller/

PCI cards
bus controller IDE PCI cards

ISA, EISA Bus

 Buffered isolation: Electrical and frequency isolation
 Benefits of buffered isolation:
 Running concurrent CPU cycles and PCI bus cycles thus improving overall system efficiency.
 Increasing the CPU local bus frequency independent of PCI bus frequency and device loading.
Transaction Protocol

Function 1 Device B/ Device A/

PCI-PCI bridge Host bridge
Function 2

 Delayed transaction protocol: Conventional PCI

 Retry response is sent to the host if the requested device is not ready with data.
 Host has to arbitrate again to put the retry request resulting in more latencies.
 Device based arbitration based on request and grant in both PCI and PCI-X.

 Split transaction protocol: PCI-X and PCIe.

 Split response is sent to the host if the requested device is not ready with data.
 Once the data is available, device arbitrates for bus, sends the completion response.
 Flow control based arbitration based on traffic classes(virtual channels) in PCIe.
BUS Bandwidth, Pin efficiency
Bus and width in Bus frequency in Bandwidth in Pin efficiency
bits Megahertz MB/s
ISA - 16 8.3 8.3 -

EISA - 32 8.3 33 -

PCI – 32 33 132 133/74=1.8MB/pin

PCI - 32 66 264 264/74=3.56MB/pin

PCI - 64 33 264 264/150=1.8MB/pin

PCI - 64 533 4264 4264/150=28.4MB/pin

PCIe - serial 2.5GHz 2.5Gbits/s 2.5Gz*1*8/10=250MB/s on Tx
= 250MB/s on Rx
= 500/8pins = 62.5MB/pin
Comparison of PCI, PCI-X, PCIE
PCI PCI-X PCIe

Transaction Delayed Split Split

Protocol
Flow control Device based arbitration Device based arbitration Based on traffic class and virtual
mechanism channels. Point-to-point.

Link topology Master/target, transaction are Master/target, transaction No master/target, PCIe identifies
identified by who mastered it are identified by who the transactions by identifiers.
mastered it

Bus Interface type Parallel(32/64-bit) Parallel(32/64-bit) Serial(upto x32),

Layered architecture
Maximum 512Mbytes/s 4.2Gbytes/s 500Mbytes/lane*32 = 16Gbytes
Bandwidth at 66MHz at 533MHz
Isochronous data Limited Limited Un-limited
transfer
Pin Efficiency 28.4Mbytes/pin 28.4Mbytes/pin 62.5Mbytes/pin
PCI Express Goals

High ▪ Scaleable Width and Frequency

Performance ▪ Higher Bandwidth

▪ Consolidate the I/O

I/O
▪ Unify Proliferated Segments
Simplification ▪ Work in Existing PCI Environment
▪ Layered Architecture
Advanced
▪ Reliability, Availability, Serviceability
Architecture ▪ Advanced Power Management

Next Gen ▪ Differentiated Services

Multimedia ▪ Isochronous Support

▪ New Form Factors/Innovative Designs

Ease of Use
▪ Hot Plug/Hot Swap
Introduction to PCIE
 Layered Architecture, promoted and standardized by PCI-SIG
 Physical layer Pcie - x4
 Data link layer
Pcie – x16
 Transaction layer
Pcie – x1
 High Performance interconnect with fever pins with 2.5Gbits/s.
Pcie – x16
 Available in x1, x2, x4, x8, x16 and x32 lane configurations.
 Addresses PCI challenges:
 Bandwidth limitations – Shared bus, depends on number of
users
 Host pin limitations – Impedance mis-match, Less connectors
on high frequencies.
 Inability to support real time audio, video (isochronous) transfer.
 Inability to address future IO requirements such as security and
IO virtualizations
TX+ RX+
Single Lane PCIe Link Device A
TX- RX-
Device B
RX+ TX+
RX- TX-
PCIe System Overview
Pin Side B Connector Side A Connector

# Name Description Name Description

Hot plug
+12 volt
1 +12v PRSNT#1 presence
power
detect
+12 volt +12 volt
2 +12v +12v
power power
+12 volt +12 volt
3 +12v +12v
power power
4 GND Ground GND Ground

5 SMCLK SMBus clock JTAG2 TCK

6 SMDAT SMBus data JTAG3 TDI

7 GND Ground JTAG4 TDO

+3.3 volt
8 +3.3v JTAG5 TMS
power
+3.3 volt
9 JTAG1 +TRST# +3.3v
power
3.3v volt +3.3 volt
10 3.3Vaux +3.3v
power power
Link
Elements of PCIe 11 WAKE#

Mechanical Key
Reactivation
PWRGD Power Good

• A Root Complex - Root of the connection of IO system to CPU and Memory 12

13
RSVD
GND
Reserved
Ground
GND
REFCLK+
Ground
Reference
Clock
• PCI express to PCI bridge - Has one PCIe port and one or more PCI/PCI-X 14 HSOp(0)
Transmitter
Lane 0,
REFCLK- Differential
pair
Differential
bus interfaces 15 HSOn(0) pair GND Ground

• End Point - Request or complete PCI transaction itself 16 GND Ground HSIp(0) Receiver Lane
0,
Hotplug Differential
17 PRSNT#2 HSIn(0) pair
• Switch - Traffic Director between multiple PCIe links 18 GND
detect

Ground GND Ground

PCI Express Features
 Physical Interface
 Point-to-point dual-simplex

 Differential low-voltage signaling

 Embedded clocking CPU

 Scalable frequency (2.5Gb/sec+)

 Scalable width (1, 2, 4, 8, 12, 16, 32)

Memory
 Supports Connectors and Cables Graphics Memory
Bridge
 Protocol
 Load Store architecture

 Fully packetized split-transaction HDD PCI

 Credit-based flow Control

Gigabit
 Virtual Channel mechanism Ethernet I/O USB 2.0
 PCI Compatibility Bridge
Add Ins Local I/O
 Configuration model and PCI Software Driver model

 Advanced Capabilities Add Ins

 Enhanced Configuration and Power Management Add Ins

 CRC Data Integrity, Hot Plug PCI Express

 Advanced error logging/reporting

 QoS and Isochronous support

 Advanced Switching Extensions

Sample Topology
Layered Architecture Overview

Software
- PCI Compatible Configuration & Driver model
Software
- PCI Express Enhanced Configuration

Transaction
- Split transaction packet based protocol
Transaction
- PCI-like Load-Store transaction semantics
- Credit based flow control, Virtual Channels
Data Link
Data Link - Logical connection between devices
- Provides reliable data transport
Physical
Physical - Electrical interface and Signaling mechanism
- Interface initialization and maintenance
Mechanical
Mechanical - Market segment specific form factors
Data Flow Between Devices

Software Software

Transaction Transaction

Data Link Data Link

Physical Physical

Mechanical Mechanical
Physical Layer

▪ Logical Functions
Software  8b/10b Encoding & Decoding
 Scrambling & Unscrambling
 Reset & Initialization
Transaction  Multi-lane deskew
 Receiver elastic buffer
 Link width and Lane mapping
Data Link negotiation
 Lane and Polarity reversal
Physical
▪ Electrical Functions
Logical  Transmitter & Receiver
 Embedded Clock extraction &
Electrical alignment
 Link Power Management

Mechanical
PCI Express Signaling

▪ 8b/10b Encoding
 Limits run lengths of 1’s and 0’s
 Data transitions enable bit-level clock recovery at the receiver
▪ Routing Flexibility
 Removes skew relationships between clock and data signals
▪ High Performance
 High frequencies
 Skew/Jitter between bits
Link Training example

▪ Configuration and
initialization of the link
Detect
Detect
Detect
▪ Detect if receiver is present
▪ Recovering from link errors
▪ Transitioning to and Polling
Polling Disabled
Polling
restarting from low power ▪ Achieve Bit lock, Symbol lock
states ▪ Configure Lane Polarity
▪ Link training & negotiation Configuration
Configuration Hot Reset Configuration
 Link width ▪ Negotiate Link width and Lane number
▪ Lane-to-lane deskew
 Lane reversal
L0
 Polarity inversion
L0 L0 Loopback

▪ Normal operational state

 Bit lock per lane L2

 Symbol lock per lane L0s Recovery

 Receiver detection
 Lane-to-lane deskew
L1
Data Link Layer

Software ▪ Initialization and Power Management

 Initialize link flow control credits
 Convey Power state Requests from
Transaction Layer to the Physical Layer
Transaction  Convey Link state to Transaction Layer
 active/reset/disconnected/power
managed

Data Link ▪ Data protection, error checking, and retry

 TLP Sequence Number and LCRC
generation
 Data integrity checking for Transaction
and Data Link Layer Packets
Physical  Transmitted TLP storage for Data Link
level retry
 TLP acknowledgment and retry
messages
Mechanical  Error indication for error reporting and
logging
Transaction Layer

 Based on Load-Store Architecture

Software  PCI addressing model
 Flat 32/64-bit address space

 Split-transaction, packet based protocol

 Credit based flow control
Transaction  PCI-X like Producer Consumer ordering
rules
 Relaxed Ordering and No Snoop support
 Transaction level End-to-End CRC
 Software controlled Power Management
Data Link  Virtual Channel and Traffic Class
 Multiple independent logical flows over
common physical link
Physical  Supports differentiated QoS

 PCI Compatible configuration mechanism

 PCI Express Enhanced Configuration
Mechanical
Transaction Basics

 Topology components
 Root Complex
 End Point CPU
 Switch
 PCI Express – PCI Bridge
Root Complex Memory

 Split Transaction
End to
 Packet based
R C
End
C
Bridge
 Request packet Switch
R

 Completion packet
 End to end and Local link PCI End
Point
End
Point
End
Point
level
Local
Packet Sources & Types

▪ Transaction Layer Packet (TLP)

Software  Memory Read and Write request
 I/O Read and Write request
 Configuration request
Transaction  Message request
 Completions
Data Link
▪ Data Link Layer Packet (DLLP)
Physical  Link data integrity Ack/Nak
 Flow control information exchange
Mechanical  Low level Power Management
Packet Format - TLP

Frame Sequence# Header Data ECRC LCRC Frame

1 byte 2 bytes 12/16 bytes 0 – 4K bytes 4 bytes 4 bytes 1 byte

Transaction Layer

Data Link Layer

Physical Layer
Packet Format - DLLP

Frame DLLP Contents CRC Frame

1 byte 4 bytes 2 bytes 1 byte

Data Link Layer

Physical Layer
Flow Control

TLP

Device A Device B

FC Update

▪ Credit based flow control

 Transmitter throttles traffic according to available credits
 Receiver sends flow control updates to the transmitter
▪ Handled by the Transaction Layer in cooperation with the
Data Link Layer
 Transaction Layer obeys flow control
 DLLPs used to exchange flow control information
▪ Prevents overflow of receive buffers
▪ Separate flow control credits
 Posted, Non-Posted, and Completions
 Headers and Payload
Flow Control Example

1. Device A advertises buffer space for FC Update = 2 NP

two Non-Posted Requests 1

2. Device B sends two Memory Read

2
Requests

3. Device A consumes one of the Non- A B

Posted Requests 3 FC Update = 1 NP

4
4. Device A advertises the released
buffer space to Device B 5
Mem Read

5. Device B sends another Memory

Read Request
Virtual Channels

Packets Packets  Traffic segregation using Virtual

Channels (VC) enables QoS
 Bandwidth management

 Latency control
VC0 VCn VC0 VCn
 Blocking – ordering and flow control

 Individual traffic paths – ordering and

flow control
Link Link  Traffic Class (TC) labeling of TLPs for
traffic differentiation
 Up to 8 Virtual Channels with associated
servicing priorities
VC0 VCn VC0 VCn
 Mapping of TCs to Virtual Channels for
platform flexibility
 Configuration of TC/VC mapping and
Packets Packets arbitration by software
PCI Software Compatibility

 PCI compatible configuration

mechanism
 Defined to boot PCI 2.2 compliant
Software Operating Systems unmodified
 Compatible with PCI device driver
model and existing software stacks for
Transaction optional PCI capabilities
 PCI Power Management, Hot-plug, MSI
Data Link  PCI compatible in band signaling
INTx interrupts and PME supported

using in-band messaging
Physical  MSI is the native interrupt mechanism
in PCI Express
 Enhanced configuration mechanism
Mechanical  Extends device configuration space

 Native Hot Plug/Surprise Removal

Application Layer

Application layer is customized based on the particular client requirements

Transaction Layer
Transaction layer
 On Tx side, TL receives the requests or the completions data from
clients and turns this to an outgoing PCIe transaction
 On Rx side, accepts the incoming PCIe transactions and
communicates to the clients.
 The main blocks are:
 Virtual channel decode
 TLP check mechanism
 BAR mechanism
 Packet recording mechanism
 ECRC mechanism
 Application interface protocol procedure
Transaction layer packet format

 TLP is Transaction layer packet consists of header, optional data

payload and optional TLP digest.
TLP Header format

Format field encoding Length field encoding

TLP Header format description

 All Transaction Layer Packet (TLP) headers contain the First 4 bytes of header
 TLP data must be 4-byte naturally aligned and in increments of 4-byte Double Words.
 Fmt[1:0] – Format of TLP
 Type[4:0] – Type of TLP
 TC[2:0] – Traffic Class (virtual channels)
 Attr[1:0] – Attributes(snoop and relaxed ordering)
 TD – 1b indicates presence of TLP digest in the form of a single DW at the end of TLP
 EP – indicates the TLP is poisoned
 Length[9:0] – Length of data payload in DW
TLP Header format:Type Encoding
TLP Header Format: Requester ID and Tag

 Tag[7:0] is a 8-bit field generated by each Requestor, and it must be unique for all outstanding
Requests that require a Completion for that Requester
 For Requests which do not require Completion (Posted Requests), the value in the Tag[7:0] field
is undefined and may contain any value
 Requester ID and Tag combined form a global identifier (Transaction ID).
 ID routing uses the Bus, Device, and Function Numbers to specify the destination Device for the
TLP
 Zero Length Read: A Memory Read Request of 1 DW with no bytes enabled, or “zero length
Read,” may be used by devices as a type of flush Request. For a Requester, the flush semantic
allows a device to ensure that previously issued Posted Writes have been completed at their PCI
Express destination.
TLP Header : Memory Requests
64-bit Memory Request

32-bit Memory Request

 Memory Requests route by address, using either 64-bit or 32-bit Addressing

 For Memory Read Requests, Length must not exceed the value specified by Max_Read_Request_Size
 Requests must not specify an Address/Length combination which causes a Memory Space access to cross a
4-KB boundary.
TLP Header : IO Requests

 I/O Requests route by Address, using 32-bit Addressing

 I/O Requests have the following restrictions:
 TC[2:0] must be 000b

 Attr[1:0] must be 00b

 Length[9:0] must be 00 0000 0001b

 Last DW BE[3:0] must be 0000b

TLP Header : Configuration Requests

 Configuration Requests route by ID, and use a 3 DW header

 In addition to the header fields included in all Memory, I/O, and Configuration
Request contain the following additional fields
 Register Number[5:0]
 Extended Register Number[3:0]
 Configuration Requests have the following restrictions:
 TC[2:0] must be 000b
 Attr[1:0] must be 00b 10
 Length[9:0] must be 00 0000 0001b
 Last DW BE[3:0] must be 0000b
TLP Header : Completion Packets

 Completion Status[2:0] Field Value Completion Status

 000b Successful Completion (SC)
 001b Unsupported Request (UR)
 010b Configuration Request Retry Status (CRS)
 100b Completer Abort (CA)
 The Completer ID[15:0] is a 16-bit value that is unique for every PCI Express
function within a Hierarchy
 Byte count is remaining byte count for that completion including the current
packet.
 BCM – Byte count field is modified from normal usage and set to indicate the
byte count field is just the size of the first packet not the whole completion.
TLP Header : Message Requests

 All Message Requests include the following fields in addition to the common header fields
Requester ID[15:0] and Tag[7:0], forming the Transaction ID.
 Message Code[7:0] – Specifies the particular Message Request.
 INTx Interrupt Signaling
 Power Management
 Error Signaling
 Locked Transaction Support
 Slot Power Limit Support
 Vendor-Defined Messages
 Hot-Plug Signaling
 Message Requests are posted and do not require Completion.
TLP Header : INTx Messaging
INTx Message Routing

 Assert_INTx/Deassert_INTx Message pairs constitute

four “virtual wires” for each of the legacy PCI interrupts
designated A, B, C, and D
 The INTx mechanism uses eight distinct Messages
 Assert_INTx/Deassert_INTx Messages do not include a
data payload (TLP Type is Msg).
TLP Header : PM Messaging
PM Message Routing

 Power Management Messages do not include a data payload (TLP Type is Msg).
 The Length field is reserved.
 Power Management Messages must use the default Traffic Class designator (TC0).
 Receivers must check for violations of this rule. If a Receiver determines that a TLP
violates this rule, it must handle the TLP as a Malformed TLP.
TLP Header : Error Messaging
ERROR Message Routing

 Error Signaling Messages do not include a data payload (TLP Type is Msg).
 The Length field is reserved.
 Error Signaling Messages must use the default Traffic Class designator (TC0)
 Receivers must check for violations of this rule. If a Receiver determines that a
TLP violates this rule, it must handle the TLP as a Malformed TLP.
TLP Header payload & TLP digest
 TLP Data payload
 Data payload is appended at the end of TLP header based on type of packet.
 Maximum payload size is 1024 double words(4 bytes)
 Address and length combination should not cross 4Kbytes boundary.
 When the data is included in TLP, first data corresponds to lowest byte address.
 TLP digest
 Data link layer inserts 32-bit LCRC to outgoing TLP, if the error has occurred to TLP before it
reaches DL, LCRC won’t detect.
 To ensure end-to-end data integrity, 32-bit ECRC is generated.

 This is optional, TD bit in header indicates the presence of TLP digest.

Flow control

Note : 1 credit unit = 16 bytes

Transaction Ordering rules
Software Overview: Type 0 config header
Software Overview: Type 1 config header
Data Link Layer
Data link layer
 Data link layer serves as gate keeper for each link.
 DL has 3 states:Inactive, Init (link is operational), Active(link up or down)
 It ensures data sent back and forth across the link is correct and received in same order
 It inserts 12-bit sequence number and 32-LCRC to each TLP being passed from transaction layer.
 Sequence number is unique and independent for each direction (Tx/Rx)
 DL increments the sequence number by 1 after sending a packet
 On the receive side, packet is accepted and ack DLLP is sent to the link if the sequence number is
correct and no LCRC error.
 When Packet is Nacked, DL will retry for the packet stored in retry buffer. If the packet is Acked, DL will
purge the TLP from retry buffer.
 Multiple TLPs could be acknowledged by sending single Ack DLLP.
 A TLP is retried if packet is Nacked or replay/Retry timer expires.
 If the retry happens for one TLP continuously four times, receiver does not acknowledge, 2 bit replay
counter rolls-over to 00. This indicates an error to physical layer to retrain the link.
Data link Layer: DLLP
 DLLP is Data link layer packet originated at Data link layer. It consists of four bytes of
data followed by 16-bit CRC.

 Ack/Nak DLLP:
 Ack DLLP: Sequence number acknowledgement on successful receipt of TLP
 Nak DLLP:Sequence number negative acknowledgement, triggers retry TLPs.

 FC DLLP:Flow control,
 initFC1, initFC2 and Update FC
 initFC1 and initFC2 are sent during FC initialization for virtual channel.
 Update FC is sent during normal link operation indicating how much buffer space available for TLPs.

 PM DLLP: Power management, there are four types:

 PM_Enter_L1,
 PM_Enter_L23,
 PM_Request_Ack and
 PM_Active_State_Request_L1
Data link Layer: DLLP types
Data link Layer: ACK/NAK DLLP

DLLP format for Ack/Nak

Data link Layer: Flow Control DLLP

DLLP format for initFC1

DLLP format for initFC2

DLLP format for UpdateFC

Data link Layer: PM DLLP

DLLP format for PM

DLLP format for vendor specific

Physical Layer
Physical Layer
 Contains all the necessary digital and analog circuits to configure
and maintain a link.
 Supports lane reversal and polarity reversal technique in order to
facilitate natural routing.
 There are two key sub-blocks : Logical and Electrical
 Logical Sub-block: Consists of Transmit unit and Receive unit
 Transmit unit
 Prepares packets received from upper layers for transmission across the link.
 Involves data scrambling, 8b/10b or 128/130b or 1b/1b encoding and packet framing.
 Receive unit
 Receives packets from link and forwards to upper layers
 Involves data de-scrambling, 8b/10b or 128/130b or 1b/1b decoding and removes the frame.
Physical Layer: Encoding and Framing
 8/10-bit Encoding example:
 Patented by IBM and used to increase data transfer rates and adopted in Serial ATA,
Gigabit ethernet, Infiniband.
 Purpose is to embed a clock signal, adding error detection and DC balance feature to
data stream to avoid data error due to length mismatches
 There are 12 special symbols and 256 data symbols. Encoding involves splitting 8-
bit byte(HGFEDCBA) to 2 parts:HGF and EDCBA,
 Example: 0x25 –> 00100101 –> 001 00101->D5.1, Special characters are prefixed by K.
 The above 3-bit and 5-bit streams are converted to 4-bit and 6-bit streams to form
10-bit symbol.
 Minimum bit transitions are forced for synchronization purposes.
 Example: 0x00 –> 00000000(8-bit) -> 1101000110(10-bit).

 Framing : Special characters are inserted to mark Start and End of packet.
Physical layer: Scrambling scheme
Scrambling is a technique used in PCI Express (PCIe) to randomize data and remove repetitive patterns. It helps to:
• Balance the signal: Scrambling creates transitions to DC-balance the signal.
• Reduce EMI noise: Scrambling removes electromagnetic interference (EMI) noise, which can be significant for PCI Express
transmission lines.
• Reduce the possibility of electrical resonances: Scrambling reduces the possibility of electrical resonances on the link

• Scrambling polynomials The polynomial used for :

o PCIe 2.0 and earlier - (G(x)=x^{16}+x^{5}+x^{4}+x^{3}+1),

o PCIe 3.0 - (G(x)=x^{23}+x^{21}+x^{16}+x^{8}+x^{5}+x^{2}+1)

Physical Layer: Special symbol table
Physical Layer: Ordered sets

Note : TS2 identifier : D5.2

Physical Layer:Electrical sub-block
 Contains transmit and receive buffers that transforms the data into/from electrical signals
 Serial/parallel conversion
 Clock extraction – recovering link clock
 Lane to lane De-skew – Compensate up to allowable 20ns skew
 Differential signaling
 Disadvantages of parallel buses are signal attenuation over length.
 Based on relative difference between two differential pair.
 To represent logical 1, positive notated signal swings to +1 and negative notated signal swings to –1.
 Advantages that of single ended signaling is, even if the differential signals are attenuated by 50%, the
difference will be still 1V, Receivers need not be designed so sensitively to detect the incoming signal.
 PLL – Clock derived from PLL circuit may provide internal clocking. PCIe is given 100MHz differential
clock, which is multiplied to achieve 2.5GHz
 AC coupling – To eliminate dc common mode element
 De-emphasis – To reduce the effects of inter-symbol interference
Physical Layer:Link Training Status State Machine

Configuration Disable Exit to

detect
L0s

L0
Polling Recovery (Full On)

loopback

Link power management states

L1
Active power management state
Hot reset

Link training states

L2
Detect
L2/L3 Ready

L3

 Electric Idle:
 When Transmit pairs TX+ and TX- are held at constant value.
Link Training and Status State Machine(LTSSM)
 Detect state :
 First state to enter upon cold reset, warm reset.
 Determines whether the device connected on the other side on per lane basis.
 Both the devices select the data rate 2.5Gb/s.
 If x4 device connected to x2 device, x2 link will be formed after 12 ms timeout on
other 2 lanes.
 Polling State:
 Training ordered sets TS1 and TS2 are used to establish bit and symbol alignment and
to exchange physical layer parameters such as data rate, clock synchronization, lane
numbering, lane polarity, enable data scrambling.
 Training ordered sets are groups of 16 8/10-bit encoded symbols and never scrambled
 Configuration:
 In Configuration, both the Transmitter and Receiver are sending and receiving data at
the negotiated data rate.
 The Lanes of a Port configure into a Link through a width and Lane negotiation
sequence.
 Lane-to-Lane de-skew must occur, scrambling can be disabled, the N_FTS is set, and
the Disable or Loopback states can be entered.
Physical Layer:Link and Training
 Recovery:
 In Recovery, both the Transmitter and Receiver are sending and receiving data using the configured
Link and Lane number as well as the previously negotiated data rate.
 Recovery allows a configured Link to re-establish bit lock, Symbol lock, and Lane-to-Lane de-skew.
 Recovery is also used to set a new N_FTS and enter the Loopback, Disable, Hot Reset, and
Configuration states.
 L0
 L0 is the normal operational state where data and control packets can be transmitted and received.
 All power management states are entered from this state.
 L0s
 L0s is intended as a power savings state.
 L0s allows a Link to quickly enter and recover from a power conservation state without going through
Recovery.
 The entry to L0s occurs after receiving an Electrical Idle ordered set.
 The exit from L0s to L0 must re-establish bit lock, Symbol lock, and Lane-to-Lane de-skew.
 A Transmitter and Receiver Lane pair on a Port are not required to both be in L0s simultaneously.
 L1
 L1 is intended as a power savings state.
 The L1 state allows an additional power savings over L0s at the cost of additional resume latency.
 The entry to L1 occurs after being directed by the Data Link Layer and receiving an Electrical Idle
ordered set.
Physical Layer:Link Training Status State Machine
 L2
 Power can be aggressively conserved in L2. Most of the Transmitter and Receiver may be shut off.
 Main power and clocks are not guaranteed.
 Disabled
 The intent of the Disabled state is to allow a configured Link to be disabled until directed or Electrical
Idle is exited (i.e., due to a hot removal and insertion).
 after entering Disabled. Disabled uses bit 1 (Disable Link) in the Training Control field which is sent
within the TS1 and TS2 training ordered set.
 A Link can enter Disabled if directed by a higher Layer. A Link can also reach the Disable state by
receiving two consecutive TS1 ordered sets with the Disable bit asserted
 Loopback
 Loopback is intended for test and fault isolation use.
 Loopback can operate on either a per Lane or configured Link basis.
 A Loopback Master is the component requesting Loopback.
 A Loopback Slave is the component looping back the data.
 Loopback uses bit 2 (Loopback) in the Training Control field which is sent within the TS1 and TS2
training ordered set.
 Hot Reset
 Hot Reset uses bit 0 (Hot Reset) in the Training Control field which is sent within the TS1 and TS2
training ordered set.
 A Link can enter Hot Reset if directed by a higher Layer. A Link can also reach the Hot Reset state by
receiving two consecutive TS1 ordered sets with the Hot Reset bit asserted
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