DCD MODULE 2

SEQUENTIAL LOGIC DESIGN — CHEAT SHEET

PICT Pune | Digital Circuit Design (DCD) | AY 2025-26

1. COMBINATIONAL vs SEQUENTIAL CIRCUITS

Feature Combinational Sequential

Memory No memory Has memory (Flip-Flops)
Output depends on Only present inputs Present inputs + past outputs
Clock Not needed Required (generally)
Feedback No feedback Feedback path exists
Speed Faster Slower
Design complexity Simpler Complex
Examples Adder, MUX, Decoder Counters, Flip-Flops, Registers

2. LATCH vs FLIP-FLOP

Feature Latch Flip-Flop

Triggering Level-triggered Edge-triggered (rising/falling)
When output changes As soon as input changes (if EN=1) Only at clock edge
Clock needed? No (or enable signal) Yes
Speed Faster Slightly slower
Predictability Less predictable More predictable
Usage SR Latch, D Latch SR FF, JK FF, D FF, T FF

KEY DISTINCTION: Latch = level-sensitive | Flip-Flop = edge-sensitive

3. 1-BIT MEMORY CELL (Bistable Element)

▶ Two inverters in a loop → two stable states: Q=0 or Q=1

▶ Bistable = can stay in either state without external input
▶ Adding NAND gates with inputs → makes it controllable (SR Latch)
▶ Problem: No way to set initial state on power-up → solved by Preset/Clear inputs

4. FLIP-FLOPS — ALL TYPES

4A. SR Flip-Flop (Set-Reset)

S R Qn+1 Operation
0 0 Qn (no change) Hold
0 1 0 Reset
1 0 1 Set
1 1 ? (invalid) Forbidden / Race

S=1 → Set (Q=1) | R=1 → Reset (Q=0) | S=R=1 →

KEY
FORBIDDEN (undefined output)

4B. JK Flip-Flop

J K Qn+1 Mode
0 0 Qn Hold (no change)
0 1 0 Reset
1 0 1 Set
1 1 Q'n (toggle) Toggle

JK FF fixes SR FF's forbidden state: J=K=1 → Toggle

KEY
instead of invalid

4C. D Flip-Flop (Delay)

D Qn+1 Meaning
0 0 Output = Input
1 1 Output = Input (delayed by 1 clock)

D FF = 'Delay' FF | Q follows D with 1 clock delay |

KEY
Only 2 middle rows of SR/JK | Single input

4D. T Flip-Flop (Toggle)

T Qn+1 Meaning
0 Qn Hold (no change)
1 Q'n Toggle

T FF = JK with J=K=T | T=1 → toggle | Used in

KEY
counters (each FF divides freq by 2)

4E. Master-Slave JK Flip-Flop

▶ Two gated SR latches in series — Master + Slave

▶ Master's CLK = normal | Slave's CLK = inverted (complement of master)
▶ CLK HIGH → Master captures input, Slave is locked
▶ CLK LOW → Slave accepts master's output, Master is locked
▶ Data accepted on HIGH → passed to output on FALLING EDGE

'Master-Slave' because master controls/feeds the

WHY CALLED
slave which follows on opposite clock phase

5. RACE AROUND CONDITION

J = K = 1 | Clock pulse width > Propagation delay of

WHEN
FF

Output toggles multiple times within ONE clock pulse

WHAT HAPPENS
→ unpredictable final state

Master-Slave JK FF → separates input capture and

SOLUTION 1
output by clock phases

Edge-triggered JK FF → responds only at exact rising

SOLUTION 2
or falling edge (not during full pulse)

6. ASYNCHRONOUS INPUTS (Preset & Clear)

▶ Preset (PRE): Forces Q=1 immediately, regardless of clock

▶ Clear (CLR): Forces Q=0 immediately, regardless of clock

They act independent of clock — no need to wait for

WHY ASYNC?
clock edge to take effect

They OVERRIDE all other inputs (J, K, D, T, Clock) —

WHY OVERRIDING?
highest priority

Purpose: To set known initial state at power-up when flip-flop state is unpredictable

7. EXCITATION TABLES — ALL FLIP-FLOPS

Truth Table: Given inputs → find output | Excitation Table: Given desired Qn→Qn+1 → find required inputs

SR Excitation Table
Qn Qn+1 S R
0 0 0 X
0 1 1 0
1 0 0 1
1 1 X 0
JK Excitation Table
Qn Qn+1 J K
0 0 0 X
0 1 1 X
1 0 X 1
1 1 X 0

D Excitation Table
Qn Qn+1 D
0 0 0
0 1 1
1 0 0
1 1 1

D = Qn+1 always. Whatever output you want, apply

D shortcut
that as D input.

T Excitation Table
Qn Qn+1 T
0 0 0
0 1 1
1 0 1
1 1 0

T = Qn XOR Qn+1. If state changes → T=1. If state

T shortcut
stays → T=0.

8. FLIP-FLOP CONVERSION — METHOD & KEY RESULTS

Steps for ANY Conversion

▶ Step 1: Identify Available FF (what you have) and Required FF (what you need)
▶ Step 2: Make characteristics/truth table of REQUIRED FF
▶ Step 3: Use EXCITATION TABLE of AVAILABLE FF
▶ Step 4: Combine → write Boolean expression using K-Map
▶ Step 5: Draw circuit using available FF + extra logic gates

Key Conversion Equations

D→T
T= D ⊕ Q (XOR of D and current output)
T → SR
S= T · Q' (T AND complement of Q)

R= T · Q (T AND Q)

JK → SR
S= J · Q' (J AND complement of Q)

R= K · Q (K AND Q)

T→D
D ⊕ Q (same as D→T, derived from T = Qn XOR
T=
Qn+1, and Qn+1=D)

SR → JK
S= J · Q' | R = K · Q

JK → D
J=D | K = D' (complement of D)

9. COUNTERS

Synchronous vs Asynchronous
Feature Synchronous Asynchronous (Ripple)
Clock All FFs get SAME clock Each FF's output = next FF's clock
Speed Faster Slower (ripple delay accumulates)
Design Complex (parallel logic) Simpler (cascade connection)
Propagation delay Low (all toggle together) High (adds up stage by stage)
Used for High-speed counters Simple / low-frequency counters
Example ICs IC 74191 IC 7490

Design Steps: Synchronous Counter (JK FF)

▶ Step 1: Determine number of bits (n) → n FFs needed (2^n states)
▶ Step 2: Write state sequence table
▶ Step 3: Note current state (Qn) and next state (Qn+1) for each FF
▶ Step 4: Use JK excitation table to find J and K for each FF
▶ Step 5: Simplify J and K using K-Map
▶ Step 6: Draw circuit
3-bit Sync UP Counter (JK) — Key Equations
JA = KA = 1 (always toggle)

JB = KB = QA (toggle when A=1)

JC = KC = QA · QB (toggle when A=1 AND B=1)

Mod-N Counter
Number of FFs = ceil(log2(N)) i.e. smallest n such that 2^n ≥ N

Need 4 FFs (2^4=16 ≥ 11) | Use NAND gate reset

Mod-11
when count reaches 11 (1011)

Frequency Division
Each FF divides frequency by 2 | n FFs → output freq
Principle
= input freq / 2^n

▶ JK FF with J=K=1 on 1 MHz clock → output = 0.5 MHz (divides by 2)

▶ Counter 0 to 2048: need 11 FFs (2^11 = 2048) | Last FF freq = 6MHz / 2^11 = ~2.93 kHz

UP-DOWN Counter with Mode Control (M)

M=0 UP counting

M=1 DOWN counting

Achieved using XOR gates: feed QA (for UP) or Q'A (for DOWN) based on M to next FF's clock

IC 7490 (Asynchronous BCD Counter)

▶ Mod-2 counter (QA) + Mod-5 counter (QB, QC, QD) internally
▶ Connect QA to input of Mod-5 section → BCD counter (Mod-10)
▶ R0(1) & R0(2) = Reset inputs | R9(1) & R9(2) = Set to 9
▶ Counts 0–9 in BCD | Output = 8421 BCD code

10. SHIFT REGISTERS

Types
Type Input Output Key Point
Data in bit-by-bit, out bit-
SISO Serial Serial
by-bit. Acts as delay line.
Serial-to-parallel
SIPO Serial Parallel converter. n clocks to load
n-bit word.
 Parallel-to-serial
PISO Parallel Serial converter. Needs extra
gates + control.
Simplest — buffer
PIPO Parallel Parallel register. Load & read in
one clock.

PISO Operation (Most Asked)

▶ Load control: HIGH → load all bits simultaneously (parallel in)
▶ Shift control: LOW → shift out serially one bit per clock
▶ Needs MUX-like gate structure to select between parallel load and serial shift

Ring Counter
SISO with Q output connected back to D input of first
What?
FF | Circulates a single '1'

n FFs → n states (not 2^n) | Single 1 rotates:

States
1000→0100→0010→0001→1000...

Johnson Counter (Twisted Ring)

Q' (complement) of last FF fed back to D of first FF |
What?
Also called switch-tail counter

n FFs → 2n states |
States 0000→1000→1100→1110→1111→0111→0011→00
01→0000...

Universal Shift Register

Right shift + Left shift + Parallel load + Hold — all in
What?
one | IC 74194

11. SEQUENCE GENERATOR

A circuit that produces a prescribed bit sequence in sync with clock

Design Steps (same as counter design)

▶ Step 1: Write the required sequence (e.g., 1→3→5→7 i.e., 001→011→101→111)
▶ Step 2: Make state table: present state → next state for each FF
▶ Step 3: Use excitation table of chosen FF (JK/T/D)
▶ Step 4: Find J, K (or T or D) expressions for each FF using K-Map
▶ Step 5: Draw circuit

1→3→5→7 in binary: 001→011→101→111 (3 FFs:

Q Bank Seq
A=LSB, B, C=MSB)
12. MEALY AND MOORE MACHINES (FSM)

What is an FSM?
Finite State Machine = sequential circuit with defined
FSM
states, transitions, inputs, outputs

Comparison
Feature Moore Machine Mealy Machine
Output depends on Only PRESENT STATE Present State + Present Input
Output changes Only at clock edge (with state) Can change when input changes
States needed More states required Fewer states (more efficient)
Output Associated with state Associated with transition
Response speed Slower (1 clock delay) Faster (immediate)
Diagram notation Output written inside state circle Output written on transition arrow
Example Traffic light controller Sequence detector

Representation
▶ State Diagram: Circles = states | Arrows = transitions | Labels = input/output
▶ State Table: Current state + Input → Next state + Output
▶ Moore: Output column tied to state | Mealy: Output column tied to (state, input) pair

13. QUICK COMPARE TABLE (Q7 of QB)

Negative Edge Triggered FF vs MS-JK FF

Feature Negative Edge Triggered FF Master-Slave JK FF
Output changes at falling edge (of
Triggering Responds only at falling edge
clock to slave)
Avoided (master locked when slave
Race around Avoided (edge is instantaneous)
active)
Simpler (single FF with edge
Implementation Two latches in series
detect)
Speed Faster Slightly slower

14. CLOCK & TRIGGERING — QUICK REFERENCE

▶ Positive Level Trigger: Active when CLK = HIGH

▶ Negative Level Trigger: Active when CLK = LOW
▶ Positive Edge Trigger: Active at LOW→HIGH transition
▶ Negative Edge Trigger: Active at HIGH→LOW transition

Timing Waveform Draw Q output aligned to clock edges. Show hold, set,
reset, toggle as per FF type. For counter — show QA,
 QB, QC stacked below clock.

15. FORMULA SHEET — QUICK NUMBERS

▶ No. of FFs for n-bit counter: n FFs → 2^n states

▶ No. of FFs for Mod-N counter: smallest n where 2^n ≥ N
▶ Frequency division: f_out = f_clk / 2^n (n = FF stage number)
▶ JK FF with J=K=1, 1 MHz in → 0.5 MHz out (÷2)
▶ Counter 0 to 2048: 2^11 = 2048 → need 11 FFs | f_out_last = 6MHz / 2^11 ≈ 2.93 kHz
▶ Mod-11 counter: need 4 FFs | Reset at count 11 (1011 in binary)
▶ Ring counter: n FFs → n states | Johnson: n FFs → 2n states
▶ Output freq of Mod-11 counter: f_clk / 11 → If out = 11 kHz, f_clk = 11×11 = 121 kHz

16. CIRCUIT DIAGRAM DRAWING GUIDE

2 NAND gates cross-coupled + Clock gate | CLK=0 →

SR FF
disabled | CLK=1 → active

SR FF + feedback from Q to R input, Q' to S input |

JK FF
Adds toggle mode

D FF JK FF with K = J' | Or SR FF with R = S'

T FF JK FF with J = K = T

Master SR latch → CLK → Slave SR latch (CLK

MS-JK
inverted) → output fed back to master input

FFs in parallel, same clock, J/K driven by logic from

Sync Counter
other FFs' outputs

FF0 clocked normally; FF1 clocked by Q0; FF2

Async Counter
clocked by Q1; etc.

17. QUESTION BANK — QUICK ANSWER MAP

Q1: 1-Bit Memory Cell

▶ = Bistable element: 2 inverters in loop | 2 stable states (Q=0, Q=1) | No input | Can't be set
▶ Enhancement: Replace inverters with NAND gates → SR Latch → controllable

Q2: Race Around + MS-JK

▶ Race: J=K=1 | Clock width > propagation delay → toggles multiple times in 1 pulse
▶ MS-JK: Master captures on CLK HIGH | Slave outputs on CLK LOW → never both active simultaneously
▶ Called Master-Slave: Master controls/feeds Slave | Both respond on opposite clock phases
Q3: FF Conversions
▶ D→T: T = D⊕Q
▶ T→SR: S = TQ', R = TQ
▶ JK→SR: S = JQ', R = KQ
▶ T→D: T = D⊕Q (same expression; solving for D: D = T⊕Q)

Q4: 3-bit Sync UP Counter JK

▶ 3 FFs: A(LSB), B, C(MSB) | Counts 000 to 111 (0 to 7)
▶ JA=KA=1 | JB=KB=QA | JC=KC=QA·QB
▶ All FFs share same clock

Q5: 2-bit Async UP/DOWN (M control)

▶ M=0 → UP: FF-B clocked by QA (non-inverted)
▶ M=1 → DOWN: FF-B clocked by Q'A (inverted)
▶ Use XOR or MUX: CLK_B = QA⊕M gives Q'A when M=1, QA when M=0

Q6: Sequence Generator 1→3→5→7

▶ Binary: 001→011→101→111 | 3 FFs: A(bit0), B(bit1), C(bit2)
▶ Unused states: 000, 010, 100, 110 → treat as don't cares in K-map
▶ For JK: derive JA, KA, JB, KB, JC, KC from state table + JK excitation
▶ For T: derive TA, TB, TC (T = Qn⊕Qn+1 for each bit)
▶ For D: derive DA, DB, DC (D = Qn+1 directly)

Q7: Comparison Summary

▶ Combo vs Seq: Memory | Latch vs FF: Level vs Edge trigger
▶ Truth vs Excitation: Input→Output vs Output→required Input
▶ Sync vs Async Counter: Common clock vs Ripple clock
▶ Moore vs Mealy: State-output vs State+Input-output
▶ Neg Edge vs MS-JK: See Section 13 above

Q8: Circuit Analysis → Truth Table

▶ Trace each input combination through the gates
▶ Build truth table from traced outputs
▶ Identify pattern → name the function (AND, OR, XOR, latch, etc.)

Q9: Asynchronous Inputs

▶ PRE (Preset): Q=1 immediately | CLR (Clear): Q=0 immediately
▶ Async: Acts without waiting for clock
▶ Overriding: Overrides all other inputs (J, K, D, T, clock)

Q10: Mod-11 Async Counter

▶ 4 FFs needed (2^4 = 16 > 11) | Count 0 to 10, reset on 11 (1011)
▶ NAND gate connected to Q0 and Q1 and Q3 (bits set in 11 = 1011) → CLR
▶ Timing waveform: QA period = T_clk | QB = 2T | QC = 4T | QD = 8T | Reset ripple visible
▶ Freq: f_out = 11 kHz → f_clk = 11 × 11 = 121 kHz (mod-11 divides by 11)
Q11: FSM — Mealy vs Moore
▶ See Section 12 full comparison
▶ Example Moore: traffic light (outputs depend only on light state)
▶ Example Mealy: vending machine (output depends on state + coin inserted)

Q12: PISO Shift Register

▶ Parallel IN → Serial OUT
▶ Load phase: all bits loaded simultaneously into FFs
▶ Shift phase: bits shifted out one by one on each clock
▶ Needs: load/shift control line + AND-OR gate arrangement per stage

Q13: JK FF Output Frequency

▶ J=K=1 → Toggle mode → divides clock by 2
▶ 1 MHz clock → output = 0.5 MHz

Q14: Counter for 0 to 2048

▶ 2^11 = 2048 → need 11 FFs
▶ Input = 6 MHz | Output of last (11th) FF = 6MHz / 2^11 = 6,000,000 / 2048 ≈ 2929 Hz ≈ 2.93 kHz

Q15: IC 7490 Internal Structure

▶ Contains: 1 JK FF (Mod-2, pin 14 input, QA output) + 3 FF RS network (Mod-5, QD QB QC outputs)
▶ For Mod-10 (BCD): Connect QA (pin 12) to input B (pin 1)
▶ Reset pins: R0(1), R0(2) → Reset to 0 | R9(1), R9(2) → Reset to 9
▶ Cascade multiple ICs for larger counts

DCD Module 2 Cheat Sheet | PICT Pune | All rights for study use