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20EC212 – COMPUTER ARCHITECTURE

AND PARALLELPROCESSING
Class: III ECE
Academic Year:2024 – 2025 ( Even)
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VISION AND MISSION OF THE

DEPERTMENT
• VISION
• To develop Electronics and Communication Engineers by keeping
pace with changing technologies,professionalism, creativity, research
and employability.
• MISSION
• • To provide quality and contemporary education through effective
teaching - learning process that equips the
• students with adequate knowledge in Electronics and Communication
Engineering for a successful career.
• • To inculcate in students, problem solving and lifelong learning skills
that will enable the students to pursue
• higher studies and career in research.
• • To prepare engineers who possess effective communication skills,
the ability to lead a team, adhering to ethical
• values and inclination to serve the society.
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PREREQUISITE
• 20EC208 - Microcontrollers and Applications

• Google Classroom Code : vkiibwl

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COURSE OUTCOMES

• On successful completion of the course, students will be able to

• CO1: Explain the functional units of computer system, Instruction Set
Architecture and Addressing modes. PO1
• CO2: Apply the knowledge of algorithms to improve the performance
of arithmetic functions. PO1, PO2, PO12
• CO3: Interpret the basic operations involved in execution of an
instruction, control unit design and pipelining concepts. PO1,
PO12
• CO4: Summarize the several types of memory, performance and the
communication process with input and output devices in a computer.
PO1, PO12
• CO5: Describe the concept of parallel, vector and multi processors
systems. PO1, PO12
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Module – III

MEMORYSYSTEM AND I/O ORGANIZATION 11

Semiconductor Memories - Speed, Size and cost ,Cache memories

-Mapping functions, Replacement Algorithms,
Memory Interleaving - Virtual memory.
Accessing I/O devices - Programmed Input/output -Interrupts -
Direct Memory Access
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Memory system
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Virtual memories
• Recall that an important challenge in the design
of a computer system is to provide a large, fast
memory system at an affordable cost.
• Architectural solutions to increase the effective
speed and size of the memory system.
• Cache memories were developed to increase the
effective speed of the memory system.
• Virtual memory is an architectural solution to
increase the effective size of the memory
system.
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Virtual memories
• Recall that the addressable memory space depends on the
number of address bits in a computer.
• For example, if a computer issues 32-bit addresses, the
addressable memory space is 4G bytes.
• Physical main memory in a computer is generally not as large
as the entire possible addressable space.
• Physical memory typically ranges from a few hundred
megabytes to 1G bytes.
• Large programs that cannot fit completely into the main
memory have their parts stored on secondary storage
devices such as magnetic disks.
• Pieces of programs must be transferred to the main
memory from secondary storage before they can be
executed.
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Contd.
• When a new piece of a program is to be transferred to the
main memory, and the main memory is full, then some other
piece in the main memory must be replaced.
• Operating system automatically transfers data between the
main memory and secondary storage.
• Application programmer need not be concerned with this
transfer.
• Also, application programmer does not need to be aware
of the limitations imposed by the available physical
memory.
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Contd.
◾ Techniques that automatically move program and data
between main memory and secondary storage when they are
required for execution are called virtual-memory techniques.
◾ Programs and processors reference an instruction or data
independent of the size of the main memory.
◾ Processor issues binary addresses for instructions and data.
▪ These binary addresses are called logical or virtual
addresses.
◾ Virtual addresses are translated into physical addresses by a
combination of hardware and software subsystems.
▪ If virtual address refers to a part of the program that is
currently in the main memory, it is accessed immediately.
▪ If the address refers to a part of the program that is not
currently in the main memory, it is first transferred to the
main memory before it can be used.
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Contd.
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Contd.
• Memory management unit (MMU) keeps track of
which parts of the virtual address space are in the
physical memory.
• When the desired data or instructions are in the main
memory, the MMU translates the virtual address into the
corresponding physical address.
• Then, the requested memory access proceeds in the
usual manner.
• If the data are not in the main memory, the MMU causes
the operating system to transfer the data from the disk
to the memory.
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Address translation
• Assume that program and data are composed of fixed-length
units called pages.
• A page consists of a block of words that occupy contiguous
locations in the main memory.
• Page is a basic unit of information that is transferred
between secondary storage and main memory.
• Size of a page commonly ranges from 2K to 16K bytes.
• Pages should not be too small, because the access time of
a secondary storage device is much larger than the main
memory.
• Pages should not be too large, else a large portion of the
page may not be used, and it will occupy valuable space in
the main memory.
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Contd.
• Concepts of virtual memory are similar to
the concepts of cache memory.
• Cache memory:
– Introduced to bridge the speed gap between the
processor and the main memory.
– Implemented in hardware.
• Virtual memory:
– Introduced to bridge the speed gap between the
main memory and secondary storage.
– Implemented in part by software.
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Contd.
• Each virtual or logical address generated by a processor is
interpreted as a virtual page number (high-order bits) plus an
offset (low-order bits) that specifies the location of a
particular byte within that page.
• Information about the main memory location of each page is
kept in the page table.
• Main memory address where the page is stored.
• Current status of the page.
• Area of the main memory that can hold a page is called as
page frame.
• Starting address of the page table is kept in a page table base
register
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Contd.
• Virtual page number generated by the processor is
added to the contents of the page table base
register.
– This provides the address of the corresponding entry
in the page table.
• The contents of this location in the page table give
the starting address of the page if the page is
currently in the main memory.
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contd.
PTBR holds Virtual address from processor
Page table base register
the address of
the page table. Page table address Virtual page number Offset
Virtual address is
interpreted as
+ page number and
PAGE TABLE
offset.
PTBR +
page
virtual number
provide the entry of This entry has the starting
the page in the page location
table. of the page.

Page table holds information

about each page. This includes
the starting address of the page
in the main memory. Control
bits
Page frame
in memory Page frame Offset

Physical address ry
in main
memo
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Contd.
◾ Page table entry for a page also includes some control bits
which describe the status of the page while it is in the main
memory.
◾ One bit indicates the validity of the page.
▪ Indicates whether the page is actually loaded into the main
memory.
▪ Allows the operating system to invalidate the page without
actually removing it.
◾ One bit indicates whether the page has been modified during
its residency in the main memory.
▪ This bit determines whether the page should be written
back to the disk when it is removed from the main
memory.
▪ Similar to the dirty or modified bit in case of cache
memory.
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Contd.
• Other control bits for various other types of
restrictions that may be imposed.
– For example, a program may only have read
permission for a page, but not write or modify
permissions.
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Contd..
• Where should the page table be located?
• Recall that the page table is used by the MMU for every
read
and write access to the memory.
• Ideal location for the page table is within the MMU.
• Page table is quite large.
• MMU is implemented as part of the processor chip.
• Impossible to include a complete page table on the chip.
• Page table is kept in the main memory.
• A copy of a small portion of the page table can be
accommodated within the MMU.
• Portion consists of page table entries that correspond to
the most recently accessed pages.
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contd..
• A small cache called as Translation Lookaside Buffer
(TLB) is
• included in the MMU.
• TLB holds page table entries of the most recently accessed
• pages.
• The TLB functions as a cache for the page table in the
main
• memory.
• Each entry in the TLB includes a copy of the information
in the
• corresponding entry in the page table.
• In addition, it includes the virtual address of the page,
which
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Contd.
• Figure 26 shows a possible organization of aTLB that uses
the
associative-mapping technique.
• Set-associative mapped TLBs are also found in commercial
products.
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Contd..
Virtual address from processor

Virtual page number Offset

TLB

Virtual page Control Page frame

number bits in memory

No
=?

Yes

Miss

Hit

Page frame Offset

Physical address in main memory

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Associative-mapped
TLB
• Given a virtual address, the MMU looks in the TLB for
the referenced page.
• High-order bits of the virtual address generated by the
processor select the virtual page.
• These bits are compared to the virtualpage numbers in
the TLB.
• If there is a match, a hit occurs and the corresponding
address of the page frame is read.
• If there is no match, a miss occurs and the page table
within the main memory must be consulted.
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Contd.
• How to keep the entries of the TLBcoherent with
the
contents of the page table in the main memory?
• Operating system may change the contents of the page table
in the main memory.
• Simultaneously it must also invalidate the corresponding
entries in the TLB.
• A control bit is provided in the TLB to invalidate an entry.
• If an entry is invalidated, then the TLB gets the information
for that entry from the page table.
• Follows the same process that it would follow if the entry
is not found in the TLB or if a “miss” occurs.
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contd.
• What happens if a program generates an access to a page
that is not in the main memory?
• In this case, a page fault is said to occur.
• Whole page must be brought into the main memory
from the disk, before the execution can proceed.
• Upon detecting a page fault by the MMU,
following
actions occur:
• MMU asksthe operating system to intervene by
raising an exception.
• Processing of the active task which caused the page
fault is interrupted.
• Control is transferred to the operating system.
• Operating system copies the requested page from
secondary storage to the main memory.
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Contd..
• Servicing of a page fault requires transferring the
requested page from secondary storage to the main
memory.
• This transfer may incur a long delay.
• While the page is being transferred the operating system
may:
– Suspend the execution of the task that caused the
page fault.
– Begin execution of another task whose pages are in
the main memory.
• Enables efficient use of the processor.
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contd..
• How to ensure that the interrupted task can
continue correctly when it resumes execution?
• There are two possibilities:
– Execution of the interrupted task must continue
from the point where it was interrupted.
– The instruction must be restarted.
• Which specific option is followed depends on the
design of the processor.
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Contd..
• When a new page is to be brought into the main memory
from secondary storage, the main memory may be full.
• Some page from the main memory must be replaced with
this new page.
• How to choose which page to replace?
• This is similar to the replacement that occurs
when the cache is full.
• The principle of locality of reference can also be applied
here.
• A replacement strategy similar to LRU can be applied.
• Since the size of the main memory is relatively larger
compared to cache, a relatively large amount of programs
and data can be held in the main memory.
• Minimizes the frequency of transfers between secondary
storage and main memory.
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Contd..
• A page may be modified during its residency in
the main
memory.
• When should the page be writtenback to the
secondary
storage?
• Recall that we encountered a similar problem in the context
of cache and main memory:
• Write-through protocol(?)
• Write-back protocol(?)
• Write-through protocol cannot be used, since it will incur a
long delay each time a small amount of data is written to the
disk.