20EC212 – COMPUTER ARCHITECTURE

AND PARALLELPROCESSING
Class: III ECE
Academic Year:2024 – 2025 ( Even)
 VISION AND MISSION OF THE
DEPERTMENT
• VISION
• To develop Electronics and Communication Engineers by keeping
pace with changing technologies,professionalism, creativity, research
and employability.
• MISSION
• • To provide quality and contemporary education through effective
teaching - learning process that equips the
• students with adequate knowledge in Electronics and Communication
Engineering for a successful career.
• • To inculcate in students, problem solving and lifelong learning skills
that will enable the students to pursue
• higher studies and career in research.
• • To prepare engineers who possess effective communication skills,
the ability to lead a team, adhering to ethical
• values and inclination to serve the society.
PREREQUISITE
● 20EC208 - Microcontrollers and Applications

● Google Classroom Code : vkiibwl

COURSE OUTCOMES

● On successful completion of the course, students will be able to

● CO1: Explain the functional units of computer system, Instruction
Set Architecture and Addressing modes. PO1
● CO2: Apply the knowledge of algorithms to improve the performance
of arithmetic functions. PO1, PO2, PO12
● CO3: Interpret the basic operations involved in execution of an
instruction, control unit design and pipelining concepts. PO1, PO12
● CO4: Summarize the several types of memory, performance and the
communication process with input and output devices in a computer.
PO1, PO12
● CO5: Describe the concept of parallel, vector and multi processors
systems. PO1, PO12
Module – I
FUNCTIONALBLOCKS OFACOMPUTER AND ARITHMETIC UNIT 15
•Functional units of a Computer- CPU, memory, input-output subsystems,

control unit, Instruction set architecture of a CPU - Instructions and

Instruction Sequencing- Register Transfer Notation, Assembly-Language
Notation, Introduction to RISC Instruction Sets, Instruction Execution and
Straight-Line- Sequencing- Addressing modes-CISC Instruction Sets- RISC
and CISC Styles- Fast Adders- Carry look-ahead adder, multiplication -
shift-and-add, Booth multiplier, carry save multiplier- Division -
non-restoring and restoring techniques.
Objectives
● Machine instructions and program execution,
including branching and subroutine call and return
operations.
● Number representation and addition/subtraction in
the 2’s-complement system.
● Addressing methods for accessing register and
memory operands.
● Assembly language for representing machine
instructions, data, and programs.
● Program-controlled Input/Output operations.
Memory Locations,
Addresses, and
Operations
Memory Location, Addresses,
and Operation
n
bits
first word
● Memory consists
second word
of many millions of
storage cells, each
•
of which can store •
•
1 bit.
● Data is usually i th word
accessed in n-bit
groups. n is called •
word length. •
•

last word

Figure 2.5. Memory words.

Memory Location, Addresses,
and Operation
● 32-bit word length example
32 bits

b31 b30 b1 b0

•
•
•
Sign bit: b31= 0 for positive numbers
b31= 1 for negative numbers

(a) A signed integer

8 bits 8 bits 8 bits 8 bits

ASCII ASCII ASCII ASCII

character character character character

(b) Four characters

Memory Location, Addresses,
and Operation
● To retrieve information from memory, either for one
word or one byte (8-bit), addresses for each location
are needed.
● A k-bit address memory has 2k memory locations,
namely 0 – 2k-1, called memory space.
● 24-bit memory: 224 = 16,777,216 = 16M (1M=220)
● 32-bit memory: 232 = 4G (1G=230)
● 1K(kilo)=210
● 1T(tera)=240
Memory Location, Addresses,
and Operation
● It is impractical to assign distinct addresses
to individual bit locations in the memory.
● The most practical assignment is to have
successive addresses refer to successive
byte locations in the memory –
byte-addressable memory.
● Byte locations have addresses 0, 1, 2, … If
word length is 32 bits, they successive words
are located at addresses 0, 4, 8,…
Big-Endian and Little-Endian
Assignments
Big-Endian: lower byte addresses are used for the most significant bytes of the word
Little-Endian: opposite ordering. lower byte addresses are used for the less significant
bytes of the word
Word
address Byte address Byte address

0 0 1 2 3 0 3 2 1 0

4 4 5 6 7 4 7 6 5 4

• •
• •
• •

k k k k k k k k k k
2 -4 2 -4 2 -3 2- 2 2 - 1 2 - 4 2- 1 2 - 2 2 -3 2 -4

(a) Big-endian assignment (b) Little-endian assignment

Figure 2.7. Byte and word addressing.

Memory Location, Addresses,
and Operation
● Address ordering of bytes
● Word alignment
● Words are said to be aligned in memory if they
begin at a byte addr. that is a multiple of the num
of bytes in a word.
● 16-bit word: word addresses: 0, 2, 4,….
● 32-bit word: word addresses: 0, 4, 8,….
● 64-bit word: word addresses: 0, 8,16,….
● Access numbers, characters, and character
strings
Memory Operation
● Load (or Read or Fetch)
Copy the content. The memory content doesn’t change.
Address – Load
Registers can be used
● Store (or Write)
Overwrite the content in memory
Address and Data – Store
Registers can be used
 Instruction and
Instruction Sequencing
“Must-Perform” Operations
● Data transfers between the memory and the
processor registers
● Arithmetic and logic operations on data
● Program sequencing and control
● I/O transfers
Register Transfer Notation
● Identify a location by a symbolic name
standing for its hardware binary address
(LOC, R0,…)
● Contents of a location are denoted by placing
square brackets around the name of the
location (R1←[LOC], R3 ←[R1]+[R2])
● Register Transfer Notation (RTN)
Assembly Language Notation
● Represent machine instructions and
programs.
● Move LOC, R1 = R1←[LOC]
● Add R1, R2, R3 = R3 ←[R1]+[R2]
CPU Organization
● Single Accumulator
● Result usually goes to the Accumulator
● Accumulator has to be saved to memory quite
often
● General Register
● Registers hold operands thus reduce memory
traffic
● Register bookkeeping
● Stack
● Operands and result are always in the stack
Instruction Formats
● Three-Address Instructions
● ADD R1, R2, R3 R1 ← R2 + R3
● Two-Address Instructions
● ADD R1, R2 R1 ← R1 + R2
● One-Address Instructions
● ADD M AC ← AC + M[AR]
● Zero-Address Instructions
● ADD TOS ← TOS + (TOS – 1)
● RISC Instructions
● Lots of registers. Memory is restricted to Load & Store

Opcode Operand(s) or Address(es)

Instruction Formats
Example: Evaluate (A+B) * (C+D)
● Three-Address
1. ADD R1, A, B ; R1 ← M[A] + M[B]
2. ADD R2, C, D ; R2 ← M[C] + M[D]
3. MUL X, R1, R2 ; M[X] ← R1 * R2
Instruction Formats
Example: Evaluate (A+B) * (C+D)
● Two-Address
1. MOV R1, A ; R1 ← M[A]
2. ADD R1, B ; R1 ← R1 + M[B]
3. MOV R2, C ; R2 ← M[C]
4. ADD R2, D ; R2 ← R2 + M[D]
5. MUL R1, R2 ; R1 ← R1 * R2
6. MOV X, R1 ; M[X] ← R1
Instruction Formats
Example: Evaluate (A+B) * (C+D)
● One-Address
1. LOAD A ; AC ← M[A]
2. ADD B ; AC ← AC + M[B]
3. STORE T ; M[T] ← AC
4. LOAD C ; AC ← M[C]
5. ADD D ; AC ← AC + M[D]
6. MUL T ; AC ← AC * M[T]
7. STORE X ; M[X] ← AC
 Instruction Formats
Example: Evaluate (A+B) * (C+D)
● Zero-Address
1. PUSH A ; TOS ← A
2. PUSH B ; TOS ← B
3. ADD ; TOS ← (A + B)
4. PUSH C ; TOS ← C
5. PUSH D ; TOS ← D
6. ADD ; TOS ← (C + D)
7. MUL ; TOS ← (C+D)*(A+B)
8. POP X ; M[X] ← TOS
Instruction Formats
Example: Evaluate (A+B) * (C+D)
● RISC
1. LOAD R1, A ; R1 ← M[A]
2. LOAD R2, B ; R2 ← M[B]
3. LOAD R3, C ; R3 ← M[C]
4. LOAD R4, D ; R4 ← M[D]
5. ADD R1, R1, R2 ; R1 ← R1 + R2
6. ADD R3, R3, R4 ; R3 ← R3 + R4
7. MUL R1, R1, R3 ; R1 ← R1 * R3
8. STORE X, R1 ; M[X] ← R1
Using Registers
● Registers are faster
● Shorter instructions
● The number of registers is smaller (e.g. 32
registers need 5 bits)
● Potential speedup
● Minimize the frequency with which data is
moved back and forth between the memory
and processor registers.
 Instruction Execution and
Straight-Line Sequencing
Addres Content
s s
Assumptions:
Begin execution i Mov A,R
here e 0 3-instruction - One memory operand
i+4 Ad B,R program
d 0 segment per instruction
i+8 Mov R0,
e C - 32-bit word length
- Memory is byte
addressable
A - Full memory address
can be directly specified
in a single-word instruction
B Data
the
for
program Two-phase procedure
-Instruction fetch
-Instruction execute
C
Page 43

Figure 2.8. A program for C ← [Α] + [Β].

 i Mov NUM1,R
e 0
i+4 Ad NUM2,R

Branching i+8
d
Ad
d
0
NUM3,R
0
•
•
•

i + 4n - 4 Ad NUMn,R
d 0
i + 4n Mov R0,SUM
e

•
•
•

SUM
NUM
1
NUM
2
•
•
•

NUMn

Figure 2.9. A straight-line program for adding n numbers.

 Mov N,R1
e
Clea R
r 0
Branching LOO
P Determine address
"Next"
of number and
Progra "Next"
add number to
m loo R0
p Decremen R
t 1
Branch> LOO
Branch target 0 P
Mov R0,SUM
e
Conditional branch
•
•
•

SUM
N n
NUM
1
Figure 2.10. Using a loop to add n numbers. NUM
2
•
•
•

NUMn
Condition Codes
● Condition code flags
● Condition code register / status register
● N (negative)
● Z (zero)
● V (overflow)
● C (carry)
● Different instructions affect different flags
Conditional Branch
Instructions
● Example: A: 11110000
● A: 1 1 1 1 0 0 0 0 +(−B): 1 1 1 0 1 1 0 0
● B: 0 0 0 1 0 1 0 0 11011100

C=1 Z=0
S=1
V=0
Status Bits

Cn-1
A B

Cn ALU
F
V Z S C
Fn-1

Zero Check
Addressing Modes
Generating Memory Addresses
● How to specify the address of branch target?
● Can we give the memory operand address
directly in a single Add instruction in the
loop?
● Use a register to hold the address of NUM1;
then increment by 4 on each pass through
the loop.
Addressing Modes

Opcode Mode ...

● Implied
● AC is implied in “ADD M[AR]” in “One-Address”
instr.
● TOS is implied in “ADD” in “Zero-Address” instr.
● Immediate
● The use of a constant in “MOV R1, 5”, i.e. R1 ←
5
● Register
● Indicate which register holds the operand
Addressing Modes
● Register Indirect
● Indicate the register that holds the number of the
register that holds the operand R1
MOV R1, (R2)
R2 = 3
● Autoincrement / Autodecrement
● Access & update in 1 instr. R3 = 5
● Direct Address
● Use the given address to access a memory
location
Addressing Modes
● Indirect Address
● Indicate the memory location that holds the
address of the memory location that holds the
data
AR = 101

100
101 0 1 0 4
102
103
104 1 1 0 A
Addressing Modes

● Relative Address
0
● EA = PC + Relative Addr
1
PC = 2 2

100
AR = 100
101
102 1 1 0 A
Could be Positive or 103
Negative 104
(2’s Complement)
 Addressing Modes
● Indexed
● EA = Index Register + Relative Addr

Useful with XR = 2
“Autoincrement” or
“Autodecrement”
+

100
AR = 100
101
Could be Positive or
Negative 102 1 1 0 A
(2’s Complement) 103
104
 Addressing Modes
● Base Register
● EA = Base Register + Relative Addr

Could be Positive or AR = 2
Negative
(2’s Complement)
+

100 0 0 0 5
BR = 100
101 0 0 1 2
102 0 0 0 A
Usually points to 103 0 1 0 7
the beginning of 104 0 0 5 9
an array
 Addressing Modes
Name Assemble syntax Addressin functio
● The different r g n
ways in which Immediate #Value O erand = Value
the location of p
an operand is Register Ri E = Ri
specified in an A
Absolute (Direct) LOC E = LOC
instruction are A
referred to as Indirect (Ri ) E = [Ri ]
addressing (LOC) A = [LOC
E
modes. A ]
Index X(R i) E = [Ri ] + X
A
Basewith index (Ri ,Rj ) E = [Ri ] + [Rj ]
A
Basewith index X(R i,Rj ) E = [Ri ] + [Rj ] + X
and offse A
t
Relative X(PC) E = [PC + X
A ]
Autoincrement (Ri ) E = [Ri ] ;
+ AIncrement Ri
Autodecrement − (Ri ) Decrement R i ;
E = [Ri]
A
Indexing and Arrays
● Index mode – the effective address of the operand is
generated by adding a constant value to the
contents of a register.
● Index register
● X(Ri): EA = X + [Ri]
● The constant X may be given either as an explicit
number or as a symbolic name representing a
numerical value.
● If X is shorter than a word, sign-extension is needed.
Indexing and Arrays
● In general, the Index mode facilitates access
to an operand whose location is defined
relative to a reference point within the data
structure in which the operand appears.
● Several variations:
(Ri, Rj): EA = [Ri] + [Rj]
X(Ri, Rj): EA = X + [Ri] + [Rj]
Relative Addressing
● Relative mode – the effective address is determined
by the Index mode using the program counter in
place of the general-purpose register.
● X(PC) – note that X is a signed number
● Branch>0 LOOP
● This location is computed by specifying it as an
offset from the current value of PC.
● Branch target may be either before or after the
branch instruction, the offset is given as a singed
num.
Additional Modes
● Autoincrement mode – the effective address of the operand is
the contents of a register specified in the instruction. After
accessing the operand, the contents of this register are
automatically incremented to point to the next item in a list.
● (Ri)+. The increment is 1 for byte-sized operands, 2 for 16-bit
operands, and 4 for 32-bit operands.
● Autodecrement mode: -(Ri) – decrement first
Move N,R
Move #NUM1,R
1 Initializatio
Clea 2
R n
LOOP r
Ad 0
(R2)+,R0
Decrement
d R
Branch> 1
LOOP
Move
0 R0,SU
M

Figure 2.16. The Autoincrement addressing mode used in the program of Figure 2.12.
Assembly Language
Types of Instructions
● Data Transfer Instructions
Name Mnemonic
Data value is
Load LD not modified
Store ST
Move MOV
Exchange XCH
Input IN
Output OUT
Push PUSH
Pop POP
 Data Transfer Instructions
Mode Assembly Register Transfer
Direct address LD ADR AC ← M[ADR]
Indirect address LD @ADR AC ← M[M[ADR]]
Relative address LD $ADR AC ← M[PC+ADR]
Immediate operand LD #NBR AC ← NBR
Index addressing LD ADR(X) AC ← M[ADR+XR]
Register LD R1 AC ← R1
Register indirect LD (R1) AC ← M[R1]
Autoincrement LD (R1)+ AC ← M[R1], R1 ← R1+1
 Data Manipulation Instructions
● Arithmetic Name Mnemonic
Increment INC
● Logical & Bit Manipulation Decrement DEC
Add ADD
● Shift Subtract SUB
Multiply MUL
Divide DIV
Name Mnemonic Add with carry ADDC
Clear CLR Subtract with borrow SUBB
Complement COM Negate NEG
Name Mnemonic
AND AND Logical shift right SHR
OR OR Logical shift left SHL
Exclusive-OR XOR Arithmetic shift right SHRA
Clear carry CLRC Arithmetic shift left SHLA
Set carry SETC Rotate right ROR
Complement carry COMC Rotate left ROL
Enable interrupt EI Rotate right through carry RORC
Disable interrupt DI Rotate left through carry ROLC
Program Control Instructions
Name Mnemonic
Branch BR
Jump JMP
Skip SKP
Subtract A – B but
Call CALL don’t store the result

Return RET
Compare
CMP
(Subtract) 10110001
Test (AND) TST
00001000

Mask
00000000
Conditional Branch
Instructions

Mnemonic Branch Condition Tested Condition

BZ Branch if zero Z=1
BNZ Branch if not zero Z=0
BC Branch if carry C=1
BNC Branch if no carry C=0
BP Branch if plus S=0
BM Branch if minus S=1
BV Branch if overflow V=1
BNV Branch if no overflow V=0
Basic Input/Output
Operations
I/O
● The data on which the instructions operate
are not necessarily already stored in memory.
● Data need to be transferred between
processor and outside world (disk, keyboard,
etc.)
● I/O operations are essential, the way they are
performed can have a significant effect on the
performance of the computer.
Program-Controlled I/O
Example
● Read in character input from a keyboard and
produce character output on a display
screen.
Rate of data transfer (keyboard, display, processor)
Difference in speed between processor and I/O device
creates the need for mechanisms to synchronize the
transfer of data.
A solution: on output, the processor sends the first
character and then waits for a signal from the display
that the character has been received. It then sends the
second character. Input is sent from the keyboard in a
similar way.
Program-Controlled I/O
Example

- Registers
- Flags
- Device interface
Program-Controlled I/O
Example
● Machine instructions that can check the state
of the status flags and transfer data:
READWAIT Branch to READWAIT if SIN = 0
Input from DATAIN to R1

WRITEWAIT Branch to WRITEWAIT if SOUT = 0

Output from R1 to DATAOUT
Program-Controlled I/O
Example
● Memory-Mapped I/O – some memory
address values are used to refer to peripheral
device buffer registers. No special
instructions are needed. Also use device
status registers.

READWAIT Testbit #3, INSTATUS

Branch=0 READWAIT
MoveByte DATAIN, R1
 Program-Controlled I/O
Example
● Assumption – the initial state of SIN is 0 and the
initial state of SOUT is 1.
● Any drawback of this mechanism in terms of
efficiency?
● Two wait loops processor execution time is wasted
● Alternate solution?
● Interrupt
Stacks
Home Work
● For each Addressing modes mentioned
before, state one example for each
addressing mode stating the specific benefit
for using such addressing mode for such an
application.
Stack Organization

Current
Top of Stack
● LIFO TOS 0
Last In First Out 1
2
3
4
5
SP 6 0 1 2 3
7 0 0 5 5
FULL EMPTY 8 0 0 0 8
9 0 0 2 5
Stack Bottom 10 0 0 1 5
Stack
Stack Organization

Current 1 6 9 0
Top of Stack
● PUSH TOS 0
SP ← SP – 1 1
M[SP] ← DR 2
3
If (SP = 0) then (FULL ← 1)
4
EMPTY ← 0 5 1 6 9 0
SP 6 0 1 2 3
7 0 0 5 5
FULL EMPTY 8 0 0 0 8
9 0 0 2 5
Stack Bottom 10 0 0 1 5
Stack
Stack Organization
Current
Top of Stack
● POP TOS 0
DR ← M[SP] 1
SP ← SP + 1 2
3
If (SP = 11) then (EMPTY ← 1)
4
FULL ← 0 5 1 6 9 0
SP 6 0 1 2 3
7 0 0 5 5
FULL EMPTY 8 0 0 0 8
9 0 0 2 5
Stack Bottom 10 0 0 1 5
Stack
Stack Organization
● Memory Stack
● PUSH PC 0
1
SP ← SP – 1 2
M[SP] ← DR
● POP AR 100
DR ← M[SP] 101
102
SP ← SP + 1

200
SP 201
202