DIGITAL SIGNAL PROCESSING

(Course Code: A8429)

Dept. of Electronics & Communication Engineering

Vardhaman College of Engineering (Autonomous)
 Module 5
Programmable DSP Devices

1. Basic Architectural features.

2. DSP Computational Building blocks.
3. Bus Architecture and Memory.
4. Data Addressing capabilities.
5. Address Generation Unit.
6. Programmability and Program Execution.
7. Speed Issues.
 BASIC ARCHITECTURAL FEATURES
 A Programmable DSP device provide instructions
similar to microprocessor.

 Programs can be designed using these instructions to

implement DSP algorithms

 The basic Computational Units provided by

instructions should include:
i. Arithmetic operations such as add, subtract and
multiply.
ii. Logic operations such as AND, OR, XOR and NOT.
iii. Multiply operations for scaling the signal before
and/or after and accumulate (MAC) operation.
iv. Signal Scaling digital signal processing.
 High speed hardware is required to carry out these
operations.
 Ex:

Multiply operation can be done much faster on a

hardware multiplier than on a microcoded multiplier
realized using shift and add technique (used in
microprocessors).

 In addition to Computational Unit, Support

Architecture should include following hardware
features:
i. On-chip registers for storage of intermediate results.
ii. On-chip memories for signal samples (RAM).
iii. On-chip program memory for programs and fixed
data such as filter coefficients (ROM).
 Example
• Investigate the basic features that should be provided
in DSP architecture to be used to implement the
following Nth order FIR filter:

Y(n)=σ𝑁−1
𝑖=0 ℎ 𝑖 𝑥 𝑛 − 𝑖 ; 𝑛 = 0,1,1, … …

Where x(n) denotes the input sample

y(n) denotes the output sample
h(i) is the ith filter coefficient
x(n-i) is the input sample I earlier than x(n)
Sol: The FIR filter requires the following basic features to
implement above equation
i. Memory for storage of signal samples x(n), x(n-1),…… etc
(RAM).
ii. Memory for storage of filter coefficients: h(0), h(1),…… etc
(ROM).
iii. A hardware multipler and an adder to carry out the multiply
and accumulate (MAC) operation.
iv. A register to keep track of accumulation (accumulator).
v. A register to point to the current signal sample being used
(Signal pointer).
vi. A register to point to the current filter coefficient being used
(coefficient pointer).
vii. A register to keep count of the MAC operations that remain
to be done (Counter).
viii. Capability to scale the signal value x(n) as it is read from the
memory and the computed signal y(n) as it is stored in the
memory (Shifters at input and output).
 DSP COMPUTATIONAL BUILDING BLOCKS
 The requirements for choosing building blocks are
Speed and Accuracy.

 The basic building blocks that are essential to carry out

DSP computations are:

i. Multiplier
ii. Shifter
iii. Multiply and Accumulate (MAC) unit
iv. Arithmetic logic unit (ALU)
 1. MULTIPLIER
 It is also called as Parallel or Array multipliers.

Need:
 Earlier multiplication schemes relied either on
software (shift and add algorithm) or on microcoded
controllers.

 Both these options require several processor cycles to

complete the multiplication.

 Hardware multiplier will implement complete

multiplication of two binary numbers to generate the
product in a single processor cycle.
 PARALLEL MULTIPLIER

Case 1: Multiplication of 2 unsigned numbers A and B

(Braun Multiplier).
 Let A is represented using m bits and B is represented
using n bits.
A=Am-1,Am-2…….A0
B=Bn-1,Bn-2………B0

 The multiplicand A, the multiplier B and the product P

are
 Product P will have a maximum of (m+n) bits.
 Each bit is obtained by a summation of bits AiBj using an array of
single-bit adders.
where index i takes on values from 0 to m-1
index j takes on values from 0 to n-1
The bits AiBj are formed using AND gates.
Ex: Let A and B has 4 bits
 The hardware structure of the multiplier (4x4 Braun
multiplier)

 For nxn multiplier, the number of adders required is n(n-1).

 It requires 12 - 3 input and 2 output adders.
 MULTIPLIER FOR SIGNED NUMBERS

 Brauns multiplier does not take into account the

signs of the numbers that are being multiplied.

 Additional hardware is required before and after the

multiplication when signed numbers, represented in 2’s
complement form are used.
Consider 2 numbers A and B represented in 2’s
complement format.
 Let A has m bits, B has n bits.

 The two subtractions can be expressed as additions of

2’s complement numbers.
 The modified structure for handling signed numbers is
called Baugh-Wooley multiplier.
 2. SHIFTER
 Shifters are required to scale down or scale up
operands and results to avoid errors resulting from
overflows and underflows during computations.

Ex 1: Compute sum of N numbers (each number is

represented by n bits)
 As the accumulated sum grows number of bits also increases.

 The maximum number of bits to which the sum grows is

(n+log2N).

 But, if each of N numbers is scaled down by log2N bits prior to

addition, the loss of the result due to overflow can be avoided.

 Accumulator will then hold the sum scaled down by log2N bits.

 The actual sum can be obtained by scaling up the result by log2N

bits when required.
Ex 2: When two numbers are multiplied (each number is
represented by n bits)

 The product can have a maximum of 2n bits.

 When this product is saved in memory, which is also n bits wide,

the lower-order n bits are generally discarded, resulting in loss of
accuracy.

 But, for multiplication of two signed numbers, accuracy can be

slightly improved by shifting the product by one bit position to the
left before saving n higher order bits.

 The accuracy improves because, instead of discarding all n lower

order bits, we now discard only (n-1) bits.
Ex 3: When carrying floating point additions

 To do this operation, the operands should be

normalized to have the same exponent.

 This is accomplished by shifting one of the operands by

the required number of bit positions so that it has the
same exponent as the other operand.
 PROBLEM
It is required to find the sum of 64 numbers each
represented by 16 bits.
i. How many bits should the accumulator have so that
the sum can be computed without the occurrence of
overflow error or loss of accuracy?
Sol: When N numbers are added, the sum can grow by a
maximum of (n+log2N).

So, to avoid overflow, the total number of bits the

accumulator should have
16+6=22.
ii. It is decided to have an accumulator with only 16 bits
but shift the numbers before the addition to prevent
overflow, by how many bits should each number be
shifted?

Sol: Since the sum can grow by 6 bits, in order to prevent

overflow, each number should be shifted by 6 bits to the
right before the addition.
iii. If all the numbers in the problem of Example 4.3 are
fixed-point integers, what is the actual sum of the
numbers?

Sol: Since each number has been shifted to the right by 6

bits, the sum should be shifted left by 6 positions to get
the actual value.

iv. What is the error in the computation of the sum?

Sol: Since the six lowest significant bits have been lost in
the process of summation, the sum could be off by as
much as 26 - 1 = 63.
 BARREL SHIFTER
 Need:

 In conventional microprocessors, shifting is

implemented by an operation similar to one performed
in a shift register.

 The operation takes one clock cycle for every single bit
shift.

 Such a scheme requires unduly large amounts of time

to implement multibit shifts.

But, in DSP, operation will be accomplished in a single-

cycle instruction execution. The circuit which does this
operation is called barrel shifter.
“The barrel shifter connects the input lines representing
a word to a group of output lines with the required shift
determined by its control inputs”.
 Control input also determines the direction of the shift (left or
right).
If the word has n bits, and shifts from 0 to n-1 bit positions to the
right or left, then the control input requires log2n lines to determine
the number of bits to be shifted.

Ex: If the shifter has 16 inputs (0 to 15 bits), then the number of

control lines required to implement the shifter are log216=4.

 Further, an additional line is also required for the control input to

indicate the direction of the shift.

Case 1: Left shift

Bits shifted out of the input word are discarded and the new bit
positions are filled with zeros.

Case 2: Right shift

The new bit positions are replicated with the most significant bit
(MSB) to maintain the sign of the shifted result.
Ex: Let four input bits are A=A3A2A1A0 and four output bits are
B=B3B2B1B0. Shift the bits right by using barrel shifter
Shift the bits right by 0,1,2 or 3 bit positions by setting the control
inputs (s0, s1, s2, or s3) high resp.

Only one of the control inputs can be high at any time and this input
closes all the switches controlled by it and enables the appropriate
paths between the inputs and the outputs.
 3. MULTIPLY AND ACCUMULATE (MAC) UNIT
 Need:
 Most DSP applications such as Filters require accumulation of the
products of a series of successive multiplications.
 In order to implement this accumulation, we need add/subtract
unit and an additional register called accumulator at the output of
multiplier.
Step1: MAC unit contains a multiplier that multiplies two n-bit
numbers X and Y and gives a product 2n bits wide.

Step 2: This is added to or subtracted from the contents of the

accumulator in the add/sub unit.

Step 3: The result is saved in the accumulator.

 The MAC unit can thus be used to implement functions of the type
A +BC.

 If the accumulator is cleared at the start of a series of

multiplications, it will contain the accumulated sum of the
products on completion of all the multiplications.

 At a time when the multiplier is computing a product, the

accumulator accumulates the product of the previous
multiplication.

 If N products are to be accumulated, N - 1 multiplies can overlap

with accumulations.
 During the very first multiply, the accumulator is idle since
there is nothing to accumulate.

 Likewise, during the very last accumulation, the multiplier

is idle since all the N products have been computed.

 Thus it takes a total of N + 1 instruction execution cycles to

compute the sum of products of N multiplications.

 Ex: If a sum of 256 products is to be computed using a

pipelined MAC unit, and if the MAC execution time of the
unit is 100 nsec, what will be the total time required to
complete the operation?
Sol: To carry out 256 MAC operations, 257 execution cycles are
required.
The total time required = (N+1)*t=257 x 100 x 10-9 sec = 25.7
µsec.
 E
 OVERFLOW AND UNDERFLOW

 When designing a MAC unit, one has to pay attention

to the word sizes encountered at the input of the
multiplier and the sizes of the add/subtract unit and
the accumulator, as overflow and underflow conditions
may be encountered otherwise.

 To prevent overflow and underflow conditions from

occurring in the MAC unit, need to provide
i. barrel shifters at the inputs and the output of the
MAC unit
ii. Guard bits in the accumulator, and
iii. Saturation logic.
 BARREL SHIFTERS
 Shifters are normally provided at the inputs/output of
the MAC unit.
 Input shifters:
It help to normalize data samples and/or filter
coefficients as, they are fed into the multiplier.

 Output shifters:
i. It is used to denormalize the result after the sum of
products computation, before being saved in the
memory.

ii. It also used to discard the redundant sign bit in 2's

complement product or to shift the output by the
required number of positions before saving to
preserve the maximum possible accuracy.
 GUARD BITS
 Need:
In order to preserve accuracy, the inputs to the
multiplier are not normalized.
In such a case, when repetitive MAC operations are
performed, the accumulated sum grows with each MAC
operation. This increases the number of bits required to
represent the result without loss of accuracy.

 One way to handle this growth is to provide extra bits

in the accumulator.

 These extra bits, called guard bits or extension bits,

allow for the growth of the accumulated sum as more
and more product terms are added up.

 When guard bits are provided in the accumulator, the

size of the add/subtract unit also increases
correspondingly.
 EXAMPLE
 Consider a MAC units whose inputs are 16-bit numbers. If 256
products are to be summed up in this MAC. how many guard
bits should be provided for the accumulator to prevent overflow
condition from occurring?
Sol: In general, the product of a 16 x 16 multiplication has 32 bits.
 Since 256 such products are ·to be summed, the sum can grow
by a maximum of log2 256 = 8 bits.
 Therefore, the number of guard bits required to prevent the
occurrence of overflow is 8.
 SATURATION LOGIC

 With or without guard bits, an, overflow condition

occurs when the accumulated result becomes larger
than the largest number it can hold.

 When handling a negative number, an underflow will

occur if the contents of the accumulator become
smaller than the smallest number it can hold.

 In such situations, it may be better to limit the

accumulator contents to the most positive (or the
most negative) value to avoid an error known as the
wrap around error.
 Limiting the accumulator contents to its saturation limits is achieved
with a simple logic circuit called the saturation logic.

 It detects the overflow and underflow condition and accordingly loads

the accumulator with the most positive or the most negative value,
overriding the value computed by the MAC unit.

 The overflow/underflow condition is detected, by monitoring the carry

into the MSB and the carry out of the MSB.

 If carry-in is not equal to carry-out, the overflow/underflow condition

occurs.

 The selection between the most negative and the most positive
numbers ‘is made based on the sign bit of the number.
 4. ARITHMETIC AND LOGIC UNIT (ALU)
 ALU operations are: add, subtract, increment,
decrement, negate, AND,OR, NOT, EXOR, and·
compare.
 ALU of a DSP is similar to the ALU of a microprocessor
but with additional features such as shift and multiply
 FEATURES OF ALU

 Apart from providing arithmetic, and logic

functions, the design of an ALU for a DSP
incorporates several other features:
i. Status Flags
ii. Overflow Management
iii. Register File
Status Flag:
 Status of the accumulator after arithmetic or a
logic operation is used for program sequencing
and scaling.

 These flags include sign, zero, carry, and

overflow.
Overflow Management
 Features of MAC are also required in ALU for
overflow management.

 MAC features are combined with the status flags.

 Ex:
Depending on the status of the overflow and the
sign flags, the saturation logic can come into effect
to limit the accumulator contents to its most
positive or the most negative value.
Register File

 A feature that improves the efficiency of an ALU is

the implementation of a large general purpose
register file.

 Need:
i. Instead of moving data in and out of the ALU to
memory during the course of an arithmetic
computation, it may be faster to have
intermediate results of arithmetic computations
stored in the ALU until the computation is
complete and the result is ready to be saved.
[Link]
is possible by providing a file of general-
purpose registers in addition to the accumulator
as part of the ALU architecture.
 BUS ARCHITECTURE AND MEMORY
 Conventional Microprocessors: Von Neumann
Architecture (same memory for program and data,
single bus)

 Disadvantages:
 Both program and data reside in the same memory and
a single bus is used to access both.
 Slows down the program execution.
 Harvard Architecture (two separate memories for
program and data, two buses)

 Disadvantages:
 For example, the multiplication operation requires two
operands to be fetched from the memory; one may be a
data sample and the other, a coefficient.
 Even with separate memories for the program and
data, it is not possible to fetch the two operands
required for the multiplication along with the program
instruction, and the processor has to 'wait for the
second operand.
 Architecture (dual data memories and a program
memory each with a separate bus)

 Disadvantages:
It require a lot of hardware and interconnections to
implement, thereby increasing the cost.

Remedy
On-chip Memory
On-chip Memory

 To avoid the problem, need some of the memories along

with their buses on-chip.

 On-chip memories can have dedicated address and data

buses unlike off-chip memories, whose buses are often
multiplexed to reduce the pin count on the DSP.
 DATA ADDRESSING CAPABILITIES
 The data processed by a DSP consist of Signal samples
and filter coefficients.

 The data addressing capabilities of a programmable

DSP device is provided by means of addressing modes.

 The addressing modes are:

i. Immediate addressing mode

ii. Register addressing mode

[Link] addressing mode

iv. Indirect addressing mode

 IMMEDIATE ADDRESSING MODE
 The capability to include data as part of the instruction
is provided by the immediate addressing mode.

 Format: ADD #imm

 Ex: Add the value represented by imm to accumulator

register A
 REGISTER ADDRESSING MODE
 In the register addressing mode a processor register
provides the operand.

 Format: ADD reg

 Ex: Add the value represented by reg to accumulator

register A
 DIRECT ADDRESSING MODE
 In the direct addressing mode a memory operand is
specified by providing its memory address.

 Format: ADD mem

 Ex: Add the value represented by mem to accumulator

register A

 A signal sample stored in a memory location can be

accessed using direct addressing mode.

 This mode however requires an explicit knowledge of

the memory address, mem.
 INDIRECT ADDRESSING MODE
 In the indirect addressing mode an operand is accessed
using a pointer A.

 Pointer is typically a register that holds the address of

the location where the operand resides.

 Format: ADD *addrreg

 Ex: To add to the accumulator, A, the content of the

memory location whose address is held in addrreg
 Indirect addressing mode can be enhanced by
providing an automatic capability to manipulate the
pointer register just before (pre) or just· after (post) the
use.
 The pointer register may be incremented or
decremented.
 The enhanced indirect addressing modes are:
 What are the memory addresses of the operands in
each of the following cases of indirect addressing
modes? In each case, what will be the content of the
addrreg after the memory access? Assume that the
initial contents of the addrreg and the·0ffsetreg are
0200h and 00l0h, respectively.
a. ADD *addrreg-.
b. ADD+ *addrreg
c. ADD offsetreg+, *addrreg
d. ADD *addrreg, offsetreg-
Sol:
 SPECIAL ADDRESSING MODES
 To compute DFT using FFT algorithms and real time
signal processing, special addressing modes are
required.

i. Circular Addressing Mode

ii. Bit-Reversed Addressing Mode
 CIRCULAR ADDRESSING MODE
 The provision of a circular buffer allows one to handle a
continuous' stream of incoming data samples.

 In a circular buffer, successive data samples are stored in

sequential buffer locations until the end of the buffer is reached.

 After reaching the end, we start all over from the beginning, of the
buffer.

 To access a data sample from a circular buffer, a circular

addressing mode is used.

 The implementation of such an addressing mode in hardware

requires three registers:
i. Pointer register(PNTR) to keep track of current address,
ii. Start, address register (SAR) to hold the start address of the
buffer, and
iii. End address register (EAR) to hold the end address of the
buffer.
 Different forms of the indirect addressing mode for the pointer register are
required in order to update the pointer for different applications.
 The pointer updating algorithm is shown below:
 The different cases that are encountered during the updating process
of the pointer are :
1. SAR < EAR, and updated PNTR > EAR
2. SAR < EAR, and updated PNTR < SAR
3. SAR > EAR, and updated PNTR > SAR
4. SAR > EAR, and updated PNTR < EAR

 The buffer size in the first two cases = (EAR - SAR + 1) and
last two it is = (SAR - EAR + 1).
 A DSP has a circular buffer with the start and the end
addresses as 0200h and 020Fh, respectively. What
would be the new values of the address pointer of the
buffer if, in the course of address computation, it gets
updated to (a) 0212h, (b) 0lFCh?
Sol: SAR= 0200h
EAR=020Fh
SAR<EAR
The buffer size = (EAR - SAR + 1)= 020Fh - 0200h + 1 = 10h
a. The new value of the pointer = updated value - buffer
length =0212h-0010h 0202h.
b. The new value of the pointer = updated value +buffer
length = OlFCh + 0010h .-:- 020Ch.
 BIT-REVERSED ADDRESSING MODE
 In DIT-FFT, naturally ordered data needs to be accessed according
to the indices for an 8-point FFT.

 The input data x(0), x(I), x(2), x(3), x(4), x(5), x(6) and x(7) need to be accessed in
the order x(0), x(4), x(2), x(6), x(l), x(5), x(3), and x(7).
 Addition, however, is different in the sense that during addition
the carry must propagate from the MSB to LSB.

 Reverse-carry-add operation is provided in the architecture to

implement this special addressing mode.

 The architecture will require a register to keep track of the index

at any time in addition to the capability to propagate the carry in
the reverse direction during the add operation in order to generate
the next index to be used to access data.
 EXAMPLE
 Compute the sequence in which .the input data should be ordered for a 16point DIT
FFT.
Sol:
 Assuming that the first sample .is located at address 0, the next sample should be
located at address 0+ B(length of FFT/2) = 0 +8 = 8.
 This address can be arrived at by carrying out binary addition with reverse carry
propagation as follows:.
 Initial address in binary = 0000 (0)
Half the length of the 'FFT in binary = 1000 (8)
Next address (add with reverse carry propagation) = 1000 (8)
 To compute the address of the third sample, repeat the operation.
Initial address in binary 1000 (8)
Half the length of the FFT in binary = 1000
Next address (add with reverse carry propagation)= 0100 (4)
 The process is repeated until the addresses
of all the 16 samples are computed.
 ADDRESS GENERATION UNIT
 The function of the address generation unit is to provide the addresses of the
operands required to carry out the DSP operations.

 In order to carry out the computations required for the specialized addressing
modes, the address generation unit in a DSP implementation is provided with
a separate arithmetic unit of its own.

 Address generation typically involves one of the following operations:

i. Getting a new value from an immediate operand, a register, or a memory
location.
ii. Incrementing or decrementing the current address.

iii. Adding or subtracting an offset to the current address.

iv. Adding or subtracting an offset to the current address, comparing the new
address with the limits defined for a circular addressing mode, and
generating a new address as per the circular addressing mode algorithm.
v. Generating a new address from the current address by applying the bit-
reversed addressing mode algorithm.
 PROGRAMMABILITY AND PROGRAM EXECUTION
 A programmable DSP device needs to provide programming capability
similar to that of a microprocessor.

 It should be possible to write programs involving branching, loops, and

subroutines.

 The branching capability is needed in order to alter conditionally or

unconditionally the normal execution sequence.

 The looping operation is desirable in order to repeat a section of the program

the desired number of times.

 The subroutine handling instructions provide the capability to develop

structured software.
 PROGRAM CONTROL
 Like microprocessors, a DSP requires a control unit, which provides the
necessary control and timing signals for proper execution of instructions.

Microprocessor:
 The control unit is generally implemented by means of a microcoded
sequencer.
 Each instruction of the microprocessor is broken down into several
microinstructions and stored in a microstore as a microcode.
 Whenever one of the instructions is to be executed, the corresponding
microcode is called from the microstore and executed, in a manner very
similar to the execution of subroutines in a program.
 This type of control unit is easy to design and implement and uses less
hardware.
 Disadvantage:

It is not very fast since execution of each instruction requires several

accesses to the microstore.
DSP:

 The speed of execution of instructions is a critical issue.

 For this reason, the design of various building blocks is

optimized for speed.

 The microcoded control unit is replaced by a hardwired design.

 In a hardwired design, the control unit is designed as a single,

comprehensive, hardware unit taking into account the complete
instruction set of the DSP.
 PROGRAM SEQUENCER
 The program sequencer, which is a part of the control
unit, generates instruction addresses in the sequence
needed to access instructions.

 The program sequencer hardware computes the

instruction address under various conditions.

 After fetching each instruction from the program

memory, the sequencer generates the address from
which the. next instruction is to be fetched.
 The next address is from one of the following sources:

i. The program counter, which is incremented after

each instruction fetch.

ii. The instruction register, which holds the address of

the instruction in branching, looping, and
subroutine calls.

iii. The interrupt vector table, in the case of interrupt

service routines.

iv. The stack, which holds the return addresses in the

case of return from subroutines, return from
interrupt service routines, and end of loops.
 The program sequencer, in effect, acts as a multiplexer,
which selects the address of the next instruction to be
obtained from one of the sources listed above.

 In order to carry out this task, several hardware

features are incorporated in the program sequencer.

 Program Counter: It will update after every fetch.

Counters are provided to hold the counts in the case of
loop and repeat instructions.

 Stack: It push the return addresses for subroutines and

interrupt service routines and while executing loops
and repeat instructions.
 Condition logic:

i. It is a logic block to test cconditions under which

jump and loop instructions are executed as well as
to determine when· to terminate loop and repeat
instructions.

ii. It also tests various arithmetic conditions by means

of status flags to decide if conditional jump and loop
instructions are to be executed.
 SPEED ISSUES
 Fast execution of algorithms is an essential
requirement of a digital signal processing architecture.

 In order to meet this requirement, DSP architecture

must include features that facilitate high speed of
operation and large throughputs.
 HARDWARE ARCHITECTURE
 By providing on-chip memories and an instruction
cache, program execution is speeded up considerably.

 Further, these on-chip memories can also be accessed

twice in a clock cycle, thereby reducing the number of
separate memories and buses required in a device.

 Techniques used in DSP architectures to increase their

speed of operation are:
i. Parallelism

ii. Pipelining
 PARALLELISM
 “Provision of functional units, which may operate in parallel
and increase the throughput”.
 An ideal parallelism in the DSP architecture with regard to
the multiply and accumulate operation, should be able to
accomplish the following operations in a single clock cycle:
i. Fetch instructions and multiple data required for the
computation.
ii. Shift data as they are fetched in order to accomplish
scaling.
iii. Carry out a multiplication operation on the fetched data.

iv. Add the product to the previously computed result in the

accumulator.
v. Save the accumulator contents in the memory storage, if
required, and
vi. Compute new addresses for the instruction and data
required for the next operation.
 PIPELINING
 An architectural feature to increase the speed of the
DSP algorithm is pipelining.

 In a pipelined architecture, an instruction to be

executed is broken into a number of steps.

 A separate unit of the architecture performs each of

these steps.

 When the first of these units performs the first step on

the current instruction, the second unit will be
performing the second step on the previous instruction,
the third unit will be performing the third step on the
instruction prior to that, etc.
 If p steps were required to complete the execution of each
instruction, it would take p units of time for the complete
execution of each instruction.
 However, since all the units will work all the time, one output
will flow out of the architecture at the end of each time unit, and
the throughput can be maintained as one instruction per unit
time.
Disadvantage:
i. A problem with this approach is dividing each instruction into
steps taking equal amounts of time to perform and designing
the architectural units accordingly.
ii. A second problem is the extra time required at the start of
algorithm execution, as the pipeline has to be filled before the
result of the first instruction can start to flow out.
 This initial delay in units of time, called the pipeline latency, is
related to the number of units in the pipeline.
 EXAMPLE
 let us assume that the execution of an instruction can be broken into
five steps: instruction fetch, instruction decode, operand fetch,
execute, and save the result.

 As we can see from the figure, the output corresponding to the first
instruction is available after 5 units of time. However, once the result
starts to come out, we get an output after each unit of time.
 In other words, the steady-state throughput of the system is one
instruction per unit time.
 SYSTEM LEVEL PARALLELISM AND PIPELINING
 Consider the example of an 8-tap (8 coefficients) FIR ,filter given by

i. Implementation using a Single MAC unit

 If only one multiplier and accumulator· is available, it must be used 8 times to
compute the eight product terms and find their sum.
Operation
 Each input sample is delayed from the previous sample by 8T, where T is the
time taken by the multiplier and accumulator to compute one product term and
add it to the previously accumulated sum in the accumulator.
 Input samples and the filter coefficients are fed to the multiplier through
multiplexers, which are controlled such that the correct combination of a sample
and the corresponding filter coefficient are fed to the multiplier at a given time.
 As each product term is generated, it is added to the previously accumulated
sum in the MAC unit.
 After all the eight product terms are accumulated, the MAC contents are
available as the output..
 Output y(n) is available 8T units of time after x(n) is made available to the
filter.
 At this time, a new sample x(n + 1) is applied to the filter. The filter then uses
eight samples, namely, x(n+ 1), x(n), x(n 1), ... , x('n - 6) to compute y(n + 1)
after another 8T units of time.
 Thus, this implementation can take in a fresh input sample once every 8 T units
of time and generate an output sample at the same rate.
 In other words, the maximum sampling rate that this filter implementation can
handle is 1/8T.
ii. Pipelined Implementation using 8 Multipliers and 8 Accumulators
 The implementation of the FIR filter of above Equation can be
speeded up if more multipliers and accumulators are available.

 Let us assume that there are 8 multipliers and 8 accumulators

connected in a pipelined structure
 Each multiplier computes one product term and passes it on to the
corresponding accumulator, which in turn adds it to the summation
passed on from the previous accumulator.

 Since all the multipliers and accumulators work all the time, a new
output sample is generated once every T units of time.

 This is the time required by the multiplier and accumulator to

compute one product term and add it to the sum passed on from the
previous stage of the pipeline.

 This implementation can take in a new input sample once every T

units of time and generate an output sample at the same rate.

 In other words, this filter implementation works 8 times faster than .

the simple one MAC implementation.
iii. Parallel Implementation using Two MAC units
 This implementation uses two MAC units and an adder at the output.
Each MAC computes four of the eight product terms in above
Equation.
 Input samples and the filter coefficients are fed to the MAGs using
multiplexers that are controlled such that correct combinations of
samples and the corresponding filter coefficients are fed to the two
MACs at any given time.
 If T time units are required to compute one pair of products and add
them to the previously accumulated sum in the MAC units, it will
require 4T units of time to generate the final output by adding the
outputs of the two MACs.
 At this time, a new input sample can be applied to the filter for
computation of the next output sample:
 Advantage:

The speed of this implementation is 2 times that of one MAC

implementation of method 1 and one fourth of that of the pipelined eight
multiplier, eight-accumulator implementation of second method.

 The maximum rate at which input samples can be applied to this

filter implementation is 2 times that of the first implementation and
one fourth that of the second.
 Table summarizes the performance of the three implementations.

 The example shows that it is possible to achieve higher-speed

implementation by the use of parallelism and/or pipelining.

 This, however, increases the hardware complexity.

THANK YOU…