MODULE-II: Sequential Logic Design

CONTENT:
Flip Flops, Clocked SR, JK, T, D and MS-JK flip-flop,
Excitation table of flip-flops, Conversion of flip-
flops, Applications of flip-flops: Counters:
Synchronous and Asynchronous counters using
flip-flops and IC 7490 and IC 74191. Shift
registers, Ring counter, Johnsons Counter and
pulse train generators using D flip flop and IC
[Link] Generators.
Mealy and Moore machines Representation.
 Sequential Circuits vs Combinational
Circuits

• Sequential circuits are those which are dependent

on clock cycles and depends on present inputs as
well as the output generated by past inputs.

• Combinational circuits are defined as the time

independent circuits which depends on current
inputs and do not depends upon output generated
by previous inputs.
 Sequential Circuits
• In this output depends upon present
input and output generated by past
input.
• Speed is slow.
• It is designed complex as compared
to combinational circuits.
• There exists a feedback path
between input and output.
• This is time dependent.
• Elementary building blocks: Flip-flops
• Mainly used for storing data.
• Sequential circuits have capability to
store any state or to retain earlier
state.
• These circuits have memory element.
• It is not easy to use and handle.
• Examples – Flip-flops, Counters
Example: Counter
• ‘Memory’ block is
nothing but Flip-Flop.

• Flip-Flop stores bits.

• Various circuits can be

implemented to store
the bit.
oEg. Cascaded NOT
gates.
 Sequential Circuits
• A memory element is some medium in which one bit of
information (1 or 0) can be stored or retained until necessary, and
there after its contents will be replaced by a new value.
• The contents of memory element can be changed by combinational
circuit which is connected to its input.
• Combinational circuit performs certain operations, some of which
are used to determine digital signals to be stored in memory
elements.
 Sequential Circuits
• FlipFlops
– SR, JK, D, T

• Registers
– SISO, SIPO,PISO,PIPO
– Shift Register, Bidirectional Shift Register
– Ring Counter

• Universal Shift Register Counters

– Asynchronous, Synchronous, BCD, Johnson, Mod of counter
(7490)

• Synchronous sequential circuit design

– Moore and Mealy
– Sequence generator and detector
 Clock
• Clock signal as a particular type of signal that oscillates between a
high and a low state.

• The signal acts like a metronome, which the digital circuit follows
in time to coordinate its sequence of actions.

• Digital circuits rely on clock signals to know when and how to

execute the functions that are programmed.
Positive level
triggering: Operated
when Logic HIGH

Negative level
triggering: Operated
when Logic LOW

Positive edge
triggering:
transitioning from
Logic Low to Logic
High

Negative edge
triggering:
transitioning from
Logic High to Logic
Low
level triggered and edge triggered
 Types of Sequential Circuits
• Following are the two types of sequential circuits −
– Asynchronous sequential circuits
– Synchronous sequential circuits

• Asynchronous sequential circuits

– If some or all the outputs of a sequential circuit do not
change (affect) with respect to active transition of clock
signal, then that sequential circuit is called
as Asynchronous sequential circuit.
– That means, all the outputs of asynchronous sequential
circuits do not change (affect) at the same time.
– Therefore, most of the outputs of asynchronous
sequential circuits are not in synchronous with either only
positive edges or only negative edges of clock signal.
• Synchronous sequential circuits
– If all the outputs of a sequential circuit change (affect)
with respect to active transition of clock signal
(memory elements are affected only at discrete
instants of time), then that sequential circuit is called
as Synchronous sequential circuit.
– That means, all the outputs of synchronous sequential
circuits change (affect) at the same time.
– Therefore, the outputs of synchronous sequential
circuits are in synchronous with either only positive
edges or only negative edges of clock signal.
 Latches
• Latches are the memory elements used to store
information or Basic storage element is called Latch.

• One latch can store one bit of information either '1' or

'0'.

• It is called a 'latch' because it can lock or latch one bit of

information. Latch is also known as ‘bistable element’.

• A bistable element is the simplest storage element which

is constructed with two inverters connected sequentially
in a loop.
• The circuit have two outputs Q and Q’ but no input.

• There are two stable states

– Q=1
– Q=0
• Let us assume that initially Q = 1. Q being the input to
the bottom inverted makes the output of bottom
inverter Q’ = 0. This ‘0’ in input to top inverter and
gives the output as ‘1’. Therefore Q = 1 and Q’ = 0 is a
stable state of the element.

• Similarly, if we assume Q = 0, we get that Q = 0 and Q’

= 1 is also the stable state.

• Therefore, we can say this element has two stable

states Q = 1, Q’ = 0 and Q = 0, Q’ = 1.

• There are four types of latches namely S-R, J-K, T and D

latch.
SR Latch using NOR gate
NOR Gate
 Latch vs Flip-flops
• latch is level-triggered: outputs can change as soon
as the inputs changes

• Flip-Flop is edge triggered: only changes state when

a control signal goes from high to low or low to high

• Latch: Less gates (Less area, less power, less

complex) but Require more tool manipulation and
more hand-calculations to verify that they meet
timing.
 FlipFlops
• Flip-flops are the basic piece of sequential logic. They effectively
store a single binary digit of state. OR a basic digital memory circuit
is known as FLIP-FLOP.

• Sequential Circuits have a memory element in addition to

a combinational circuit so it remembers one bit of information.

• Flip flop is a sequential circuit which generally samples its inputs

and changes its outputs only at particular instants of time and not
continuously.

• Flip flop is said to be edge sensitive or edge triggered rather than

being level triggered like latches
• Flip-Flop has two stable states, 1 state and 0 state.
• If Q=1 then Q’=0, similarly Q=0 then Q’=1
• It can be obtained using NAND or NOR gates.
• Since this information is locked or latched in this
circuit, therefore it is referred as a latch.
• In above circuit, there is no way of entering the
desired digital information to be stored in it.

• Infact when power is switched on, the circuit

switches to one of the stable state (Q=1 or 0) and
it is not possible to predict the state.

• So let us replace the inverters G1 and G2 with

two NAND gates, and other input terminals of the
NAND gates can be used to enter desired digital
information.
NAND Gate
NAND Gate
 Clocked SR FlipFlop
• It is often required to set or reset memory cell in
synchronization with a train of pulses called Clock. Such
circuit is called as Clocked SR FlipFlop.

• CLK is a control input.

• If CLK=1, circuit is operational.

• If CLK=0, gates G3 and G4 are inhibited i.e. their outputs are 1

irrespective of the values S or R.

• Means circuit responds to the inputs S and R only when

clock is present.
Clocked SR FlipFlop
NAND Gate
 Preset and Clear
• In Clocked SR FlipFlop, when power is switched on, state
of the circuit is uncertain.
• It may come to set (Q=1) or reset(Q=0)state.
• In many applications initial state of FLIP-FLOP is to be
assigned.

• Asynchronous inputs on a flip-flop have control over the

outputs (Q and not-Q) regardless of clock input status.
These inputs are called the preset (PRE) and clear (CLR).
• The preset input drives the flip-flop to a set state while
the clear input drives it to a reset state.
• This inputs can be applied at any time between clock
pulses but in synchronism with the clock.
 NAND Gate

Clk Inputs Output Operation

Cr Pr performed
1 1 1 SR- Table Normal Flip-flop

0 1 0 1 Preset

0 0 1 0 Clr
J-K Flip-Flop
 JK FF Operation

The 4 modes of
operation are:
hold, set, reset, toggle

Truth Table of JK

J K Q Q’ Mode
0 0 Q Q’ Hold
1 0 1 0 Sets
0 1 0 1 Resets
1 1 Q’ Q Toggle
 NAND Gate
Mode of Operation: Hold

Hold: no change in Q.

J K Next state Q’ Orig. Q Orig. Q’

Q
0 0 1 0 1 0
 NAND Gate

Mode of Operation: Reset

Reset: Q = 0.

J K Q Q’ Orig. Q Orig. Q’

0 1 0 1 1 0
 NAND Gate

Mode of Operation: Set

Set: Q = 1.

J K Next State Q’ Orig. Q Orig. Q’

Q
1 0 1 0 0 1
 NAND Gate
Mode of Operation: Toggle

Toggle: Q =
Q’.

J K Q Q’ Orig. Q Orig. Q’

1 1 1 0 0 1
 NAND Gate

Mode of Operation: Toggle

Toggle: Q =
Q’.

J K Q Q’ Orig. Q Orig. Q’

1 1 0 1 1 0
 Race Around Condition
• When J=K=1, then race around condition occurs.

• It occurs, when the time period of the clock pulse (pulse

width) is greater than the propagation delay of the flip flop.
Due to that output changes or toggles in a single clock period.

• Propagation delay is the speed of operation of circuit.

• We can’t make clock pulse smaller than propagation delay, so

to avoid it two options:
1. Master slave JK FF
2. Edge triggered JK FF
Race Around Condition
 Master Slave FF
• The Master-Slave Flip-Flop is basically two gated SR flip-flops
connected together in a series configuration with the slave
having an inverted clock pulse.

• The outputs from Q and Q’ from the “Slave” flip-flop are fed
back to the inputs of the “Master” with the outputs of the
“Master” flip flop being connected to the two inputs of the
“Slave” flip flop.

• When clock is ‘high’, master SR latch will lock the input

conditions and as clock is inverted to slave , slave SR latch
will not toggles.

• When clock goes low, the outputs from master FF are latched
and any additional changes to its inputs are ignored. Now
gated slave FF are now responds.
 Master Slave FF

• On low to high transitions of clock pulse the inputs of master

FF are fed through to the gated inputs of slave FF and on
High-to-Low” transition the same inputs are reflected on the
output of the “slave” making this type of flip flop edge or
pulse-triggered.

• Then, the circuit accepts input data when the clock signal is
“HIGH”, and passes the data to the output on the falling-edge
of the clock signal.

• Master-Slave JK Flip flop is a “Synchronous” device as it only

passes data with the timing of the clock signal.
Input Output waveform of Master Slave flip
flop
 D-Type Flip Flop
• If you have only two middle rows of Truth table of JK
or SR flipflop, then we get D flipflop.

• It has only 1 i/p line.

• D – means Delay. The Q output always takes on the

state of the D input at the moment of a rising clock
edge.

• The output takes the value of the D input or Data

input, and Delays it by one clock count.
• After observing truth table, this is equivalent
to say that the input data appears at the
output at the end of clock pulse. Thus the
transfer of the input data to the output is
delayed.

• So it is used to delay the data or to store the

data.
 T -Type Flip Flop (Toggle)

• In J K Flip Flop, if J=K=1, the resulting Flip flop is

referred to as a T- type Flip Flop.

• It has only one input.

• After observing truth table, it is clear that when T=1,

it act as a toggle switch.
 Excitation Tables
• Two tables are there:-

[Link] table (Characteristics table):- shows operation

of circuits i.e. shows changes in output whenever
changes in inputs. Mapping between input to
output.

[Link] table:- Sometimes there is need to find

input condition from the given output conditions, we
need excitation table. In this case for the desired
output, we need to find out input conditions
 S R Flip Flop
SR truth table
Characteristics state table
S R Qn+1
0 0 Qn
0 1 0 S R Qn Qn+1
1 0 1
1 1 ? 0 0 0 0
0 0 1 1
SR excitation table 0 1 0 0
0 1 1 0
Qn Qn+1 S R
1 0 0 1
0 0 0 X
1 0 1 1
0 1 1 0
1 1 0 ?
1 0 0 1
1 1 1 ?
1 1 X 0
 J K Flip Flop
JK truth table

J K Qn+1
Characteristics state table

0 0 Qn
0 1 0 J K Qn Qn+1
1 0 1
1 1 Qn’ 0 0 0 0
0 0 1 1
JK excitation table = ?? 0 1 0 0
0 1 1 0
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 0
 J K Flip Flop
JK truth table

J K Qn+1
Characteristics state table

0 0 Qn
0 1 0 J K Qn Qn+1
1 0 1
1 1 Qn’ 0 0 0 0
0 0 1 1
JK excitation table 0 1 0 0
0 1 1 0
Qn Qn+1 J K
1 0 0 1
0 0 0 X
1 0 1 1
0 1 1 X
1 1 0 1
1 0 X 1 1 1 1 0
1 1 X 0
 D Flip Flop

D truth table
Characteristics state table

D Qn+1
D Qn Qn+1
0 0
0 0 0
1 1
0 1 0
1 0 1
D excitation table= ? 1 1 1
 D Flip Flop

D truth table
Characteristics state table

D Qn+1
D Qn Qn+1
0 0
0 0 0
1 1
0 1 0
1 0 1
D excitation table 1 1 1
Qn Qn+1 D
0 0 0
0 1 1
1 0 0
1 1 1
 T Flip Flop
T truth table
Characteristics state table

T Qn+1
0 Qn T Qn Qn+1
1 Qn’ 0 0 0
0 1 1
1 0 1
T excitation table= ? 1 1 0
 T Flip Flop
T truth table
Characteristics state table

T Qn+1
0 Qn T Qn Qn+1
1 Qn’ 0 0 0
0 1 1
1 0 1
T excitation table 1 1 0

Qn Qn+1 T
0 0 0
0 1 1
1 0 1
1 1 0
 Conversion of FF

• Identify available and required flip flop

• Make characteristic table (Truth Table) for

required flip flop.

• Make excitation table for available flip flop.

• Write Boolean expression for available flip flop.

• Draw the circuit.

Example
 Conversion of SR flip flop to JK flip flop
1) available flip flop – SR 2) T truth/characteristics 3) SR excitation table
required flip flop - JK table (required flip flop)

J K Qn+1 Qn Qn+1 S R
4) Write Boolean expression
0 0 Qn
Qn
0 0 0 X
Qn J K S R 0 1 0
+1 0 1 1 0
1 0 1
0 0 0 0 0 X 1 0 0 1
1 1 Qn’
1 1 X 0
0 0 1 0 0 X JK
Qn 00 01 11 10
0 1 0 1 1 0
0 0 0 1 1 S = Qn’.
0 1 1 1 1 0 1 X 0 0 X J
1 0 0 1 X 0
1 0 1 0 0 1 JK
1 1 0 1 X 0 Qn 00 01 11 10
0 X X 0 0 R = Qn. K
1 1 1 0 0 1
1 0 1 1 0
 Conversion of JK to D Flip
1) available flip flop - JK
2) D truth/characteristics 3) JK excitation table
required flip flop - D
table (required FF)

D Qn+1 Qn Qn+1 J K
0 0 0 0 0 X
1 1 0 1 1 X
1 0 X 1
1 1 X 0
4) Write Boolean expression

D
Qn D Qn+1 J K 0 1 D
Qn
Qn 0 1
0 0 0 0 X
00 1
0 1 1 1 X 0x x
1X X
1 0 0 X 1 11 0
1 1 1 X 0 J=D K=D’
 Conversion of T flip flop to D flip flop
2) T truth/characteristics 3) T excitation table
1) available flip flop – T table (required flip flop)
required flip flop - D
Qn Qn+1 T
D Qn+1 0 0 0
0 0 0 1 1
1 1 1 0 1
1 1 0
4) Write Boolean expression

D
Qn D Qn+1 T
Qn 0 1
00 1
0 0 0 0
11 0
0 1 1 1
1 0 0 1 T=Q’ D + Q D’
1 1 1 0 =Q⊕D
 Applications of Flip Flops
• Bounce Elimination Switch: They are employed in
digital system as input devices by which digital
information (0 or 1) is entered in the system.

• Latch: Stores 1 bit information.

• Register: Group of Flip-Flops to store bits of the

information.

• Counter: often needed to count events.

• Random Access Memory

Answers
 Registers
• Registers hold larger quantities of data than
individual flip-flops.
▫ Registers are central to the design of modern processors.
▫ There are many different kinds of registers.

• A register is an extension of a flip-flop that can store

multiple bits.

• Registers are commonly used as temporary storage

in a processor.
▫ They are faster and more convenient than main memory.
▫ More registers can help speed up complex calculations.
 Registers
• Registers are composed with multiple FlipFlops
together to store group of bits.
• To store N bit word, we need N FlipFlops.
• Microprocessors makes copy of the data
before performing operations, registers are
used for storing that temporary data.
– Eg. 8086 have, 8 sixteen bit registers and 1 sixteen
bit flag register.

• Data can be entered serially (temporal code)

or parallel (Spacial code).
 Types of Registers

• Buffer Register

• Shift Register
i. Serial In Serial Out (SISO)
ii. Serial In Parallel Out (SIPO)
iii. Parallel In Serial Out (PISO)
iv. Parallel In Parallel Out (PIPO)
v. Bidirectional Shift Register
vi. Universal Shift Register
 Shift Registers

• SISO: Serial In, Serial Out 10110 10110

10110

• SIPO: Serial In, Parallel Out 10110

10110

• PISO: Parallel In, Serial Out 10110

10110

• PIPO: Parallel In, Parallel Out

10110
 Buffer registers
• Buffer registers are a type of registers used to store a binary
word. These can be constructed using a series of flip-flops as
each flip-flop can store a single bit.
• This means that in order to store an n-bit binary word one
should design an array of n flip-flops.
• Figure shows a 4 bit synchronous buffer register formed by
cascading four positive edge triggered D flip-flops.
• Here the entire input
data word B1B2B3B4 is
loaded onto the register
at a single clock tick.

• This means that at

every leading edge of
the clock the values of
flip-flop outputs follow
their input bits i.e. Q1 =
B1, Q2 = B2, Q3 = B3 and
Q4 = B4 as shown by
Figure 2.
Shift Register
 Regis
ters
1.87
Shift Register Construction

• Shift registers are comprised of D Flip-Flops that share a

common clock input.

D Q D Q D Q

Q Q Q
 Regist
SISO Flip-Flop Shift Register ers
1.88

• a Serial In Serial Out shift register has a single input and a

single output

Input D Q D Q D Q Output

Q Q Q
 SIPO Flip-Flop Shift Register Regist
ers
1.89
• A Serial In Parallel Out shift register has a single input and
access to all outputs

Output Output Output

Input D Q D Q D Q

Q Q Q
 Regis
PISO Flip-Flop Shift Register ters
1.90

• A Parallel In Serial Out shift register requires additional gates,

and the parallel input must revert to logic low for serial
output.

Input
Input Input
Output

D Q D Q
D Q
Q Q
Q
 Regist
PIPO Flip-Flop Shift Register ers
1.91

• A Parallel In Parallel Out register has the simplest

configuration. It represents a memory device.

Input Input Input

D Q D Q D Q

Q Q Q

Output Output Output

Bidirectional Shift Register
Bidirectional Shift Register
 Regis
ters
1.94
Universal Shift Register
• If the register has both shifts (right shift and left shift) and
parallel load capabilities, it is referred to as universal shift
register.
 Regis
Shift Register Applications ters
1.97

• Temporary data storage.

• Bit manipulation.
• Serial to parallel convertor.
• Parallel to serial convertor.
• Computer and Data Communications.
• Serial and Parallel Communications.
• Multi-bit number storage.
• Sequence generator.
• Sequence Detector.
• Logical operations.
Shift Register
Ring Counter
Twisted Ring Counter
 Counters
• Digital counters are often needed to count
events.

• The counter are also composed of Flip Flops.

• A circuit with n Flip Fops has 2n possible

states.
Asynchronous vs. Synchronous
The 2-bit UP-Counter counts the binary number
from 0 to 7
Qn1 Qn0 Q1 Q0 JB KB JA KA
0 0 0 1
0 1 1 0
1 0 1 1
1 1 0 0

Q represents the previous output, Qn Qn+1 J K

and Qn represents the current
output.
0 0 0 X
0 1 1 X
1 0 X 1
1 1 X 0
The 3-bit UP-Counter counts the binary number from
0 to 7

JK
Excitation
table

Q Q J K
n n+
1
0 0 0 X
0 1 1 X
1 0 X 1
1 1 X 0
K-Map and Simplification
Synchronous UP-Count Circuit Diagram
4 bit UP Counter
IC’s Available
3 bit DOWN Counter
UP-DOWN Counter
74191
Design & implement Sequence generator using MS
JK flip-flop

1 3 5 6 7

A circuit which generates a prescribed sequence of bits, in

synchronium with a clock, is referred to as a Sequence Generator.
• Sequence Generators can be used for:
– Counters
– Random bit generators
– Prescribed period and Sequence generator
1 3 5 6 7
K-Map & Simplification:
K-Map & Simplification:
Sequence Generator Circuit Diagram

Input
Expressions
for Flip-Flop
• Mealy Machine:-

– Output of the circuit depends on present state as

well as on the inputs, called mealy m/c.
• Moore Machine:-

– Output of the circuit depends only on present

state of FF, then it is Moore machine.