ECE 270: Embedded Logic Design
Integrated Circuits (IC)
• Integrated circuit technology has improved to allow more and more
components on chip
FPGA: Field Programmable Gate Array
• Array of generic logic gates
• Gates where logic function can be programmed
• Programmable interconnection between gates
• Field: System can be reprogrammed in the field (After fabrication)
Look up Table (LUT)
Generic FPGA Design Flow
FPGA Design Flow
• All the designs start with design requirements
and design specifications
• Next step is to formulate the design
conceptually either at block diagram level or
at an algorithmic level
FPGA Design Flow
• Design Entry:
• Olden days: Hand-drawn schematic
• Now, computer-aided design (CAD) tools: Mostly
using HDLs
FPGA Design Flow
• Behavioral simulation to ensure that the
design is functionally correct
• Can be done using: Test benches, test bench
waveforms
Functional (HDL/RTL) Simulation
HDL/RTL Simulation
• Self-checking test bench: Contains output data and self-checking
code that can be used to compare the data from later simulation
runs
• When running a simulation with this kind of test bench, simulation
outputs will be monitored. If a difference is detected between the
predicted and the actual outputs, an error is reported.
• Automate the task of verifying simulation results i.e. no need to
manually check waveform results
HDL/RTL Simulation
FPGA Design Flow
FPGA Design Flow
FPGA Design Flow
Translation
• Translate process merges all of
the input netlists and design
constraints and outputs a Xilinx
native generic database (NGD)
file
Mapping
• The Map process maps the
logic defined by an NGD file
into FPGA elements, such as
CLBs and IOBs.
• The output design is a
native circuit description
(NCD) file that physically
represents the design
mapped to the components
in the FPGA.
Post-map Static Timing
• You can generate a post-map static timing report for your design.
• It lists only the signal path delays in your design, derived from the
design logic.
• Useful in evaluating timing performance of the logic paths,
particularly if your design does not meeting timing requirements
• Route delays are not accounted (You can eliminate potential problems
before investing time in examining routing delays)
• To eliminate problems, you may choose to redesign the logic paths to
use fewer levels of logic, tag the paths for specialized routing
resources, move to a faster device, or allocate more time for the path.
Placing
• The Place and Route process takes a mapped
NCD file, places and routes the design, and
produces an NCD file that is used as input for
bitstream generation.
Routing
Routing
Post-place and Route Static Timing
• Incorporates timing delay (signal and routing delay) information to
provide a comprehensive timing summary of your design
• If you identify problems in the timing report, you can try fixing the
problems by increasing the placer effort level, using re-entrant
routing, or using multi-pass place and route.
• You can also redesign the logic paths to use fewer levels of logic,
move to a faster device, or allocate more time for the paths.
• If a placed and routed design has met all of your timing constraints,
then you can then create configuration data.
FPGA Design Flow
• FPGA programming simply involves writing a
sequence of 0 and 1 into the programmable
cells of FPGAs
• Once a design is implemented, you must
create a file that the FPGA can understand.
This file is called a bitstream: a BIT file (.bit
extension)
• The BIT file can be downloaded directly to the
FPGA or can be converted into a PROM file
which stores the programming information.
FPGA Design Process
ASIC Design Flow
• In ASIC, routed design is used to generate
photomask for producing integrated circuits