Microprocessor Laboratory Experiment 2

Experiment 2
Addition of Binary and BCD Numbers using Intel
8085 Microprocessor

Laboratory Manual cum Journal

Contents
1 Aim 2

2 Activity 1: Understanding Binary Addition 3

3 Activity 2: Binary Addition in the Intel 8085 Microprocessor 8

3.1 Task 1: Addition of an Immediate Operand . . . . . . . . . . . . . . . . 9
3.2 Task 2: Addition of Register Contents . . . . . . . . . . . . . . . . . . . 11
3.3 Task 3: Addition of Data Stored in Memory . . . . . . . . . . . . . . . . 13

4 Activity 3: Observing Carry Using the Flag Register 17

5 Activity 4: Multi-Byte Binary Addition 22

6 Activity 5: Addition of BCD Numbers 26

7 Summary of Instructions Learned 30

8 Viva Questions 30

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1 Aim
After completing this experiment, the student should be able to:

1. Understand the principles of binary addition and explain the generation of carry
during arithmetic operations.

2. Perform binary addition using immediate data, registers and memory operands in
the Intel 8085 microprocessor.

3. Observe and interpret the Carry flag generated during binary addition and under-
stand its significance in arithmetic operations.

4. Perform multi-byte binary addition using the ADC instruction and understand the
concept of carry propagation.

5. Perform addition of packed BCD numbers using the DAA instruction and distinguish
between binary and BCD arithmetic.

6. Develop assembly language programs for binary and BCD addition, convert them
into machine language programs, and execute them using the Intel 8085 program-
ming trainer kit.

7. Observe and interpret the contents of processor registers, memory locations and
status flags during program execution.

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2 Activity 1: Understanding Binary Addition

Problem Statement
Binary addition is the fundamental arithmetic operation performed by all digital systems
and microprocessors. Unlike decimal addition, binary addition uses only two digits, 0
and 1, and follows a simple set of logical rules. Every arithmetic operation executed by a
microprocessor, including addition, subtraction, multiplication and division, is ultimately
performed using binary arithmetic.
In this activity, the principles of binary addition are introduced beginning with one-
bit operands. The generation of the Sum and Carry bits using logical operations, the
propagation of Carry during multi-bit addition, and the extension of the same procedure
to larger binary numbers are discussed. These concepts form the mathematical founda-
tion for implementing arithmetic operations using the Intel 8085 microprocessor in the
subsequent activities.

Concept Introduced
This activity introduces the following concepts:
• Binary addition
• Sum bit and Carry bit
• XOR gate and AND gate
• Carry propagation
• Multi-bit binary addition

One-Bit Binary Addition

The addition of binary numbers is performed one bit at a time. During multi-bit addition,
the addition process begins with the least significant bit (LSB) and proceeds towards the
most significant bit (MSB). Consequently, understanding the addition of two single-bit
binary digits provides the basis for binary addition of numbers of any length.
A one-bit binary addition produces two outputs: a Sum bit and a Carry bit. The Sum
bit represents the result at the current bit position, whereas the Carry bit is transferred
to the next higher bit position whenever required.

Exclusive OR (XOR) Gate

The Exclusive OR (XOR) gate is a digital logic gate that produces a logic HIGH output
only when the two input bits are different. If both input bits are identical, the output
remains logic LOW. The logical symbol for an XOR gate is shown in Figure 1.

A Output
B

Figure 1: IEC symbol for an Exclusive OR (XOR) gate.

The logical operation performed by the XOR gate is summarized in Table 1.

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Table 1: Truth Table for the XOR Gate

Input A Input B Output

0 0 0
0 1 1
1 0 1
1 1 0

AND Gate
The AND gate is a digital logic gate that produces a logic HIGH output only when both
input bits are logic HIGH. If either input is logic LOW, the output remains logic LOW.
The logical symbol for an AND gate is shown in Figure 2.

A Output
B

Figure 2: IEC symbol for an AND gate.

The logical operation performed by the AND gate is summarized in Table 2.

Table 2: Truth Table for the AND Gate

Input A Input B Output

0 0 0
0 1 0
1 0 0
1 1 1

One-Bit Binary Addition Using Logic Gates

Comparison of the truth tables for the XOR and AND gates with the results of one-
bit binary addition shows that the output of the XOR gate is identical to the Sum bit,
whereas the output of the AND gate is identical to the Carry bit. Therefore, one-bit
binary addition can be realized using a combination of XOR and AND logic gates.
The relationship between the logical operations and the outputs of one-bit binary
addition is expressed as

Sum = A ⊕ B (1)

Carry = A · B (2)
where ⊕ denotes the Exclusive OR (XOR) operation and · denotes the logical AND
operation.
During the addition of multi-bit binary numbers, the Carry generated at one bit posi-
tion is transferred to the next higher bit position, where it participates in the subsequent
addition. This transfer of Carry from one bit position to the next is known as carry
propagation and forms the basis of multi-bit binary addition.

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Carry Propagation
During one-bit binary addition, the Carry bit is generated only when both input bits
are equal to 1. While this Carry bit is not required for one-bit addition, it becomes
essential when adding binary numbers containing two or more bits. In such cases, the
Carry generated at one bit position is added to the next higher bit position. This process
is known as carry propagation.
The addition of multi-bit binary numbers therefore consists of a sequence of one-bit
additions, beginning with the least significant bit (LSB) and proceeding towards the most
significant bit (MSB). At each stage, the Sum bit is recorded at the current bit position,
while the Carry bit, if generated, is propagated to the next higher bit position.

Carry Propagation
During one-bit binary addition, the Carry bit generated at one bit position is added to
the next higher bit position whenever binary numbers containing two or more bits are
added. This transfer of the Carry from one bit position to the next is known as carry
propagation. Consequently, multi-bit binary addition is performed as a sequence of one-
bit additions, beginning with the least significant bit (LSB) and proceeding towards the
most significant bit (MSB).
The following examples illustrate the process of carry propagation during binary ad-
dition.

Example 1: Two-Bit Binary Addition

Consider the addition of the binary numbers 11 and 01.

1
1 1
+ 0 1
1 0 0
The addition begins with the least significant bit. The addition of 1 + 1 produces
a Sum of 0 and generates a Carry of 1. This Carry is propagated to the next higher
bit position, where it is added along with the remaining input bits. The final result is
therefore 100.

Example 2: Four-Bit Binary Addition

Carry propagation becomes more evident when binary numbers containing several bits
are added.

1 1
1 0 1 1
+ 0 1 1 0
1 0 0 0 1
In this example, Carry is generated at successive bit positions and propagated towards
the higher-order bits until the complete addition is performed. The same procedure is
followed irrespective of the number of bits present in the operands.

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Multi-Bit Binary Addition

The principles of one-bit binary addition and carry propagation can be extended to
binary numbers containing any number of bits. During multi-bit binary addition, the
corresponding bits of the two operands are added beginning with the least significant bit
(LSB). At each bit position, the Sum bit is recorded, while the Carry bit, if generated,
is propagated to the next higher bit position. The procedure is repeated until all bit
positions have been processed.
The following example illustrates the addition of two eight-bit binary numbers. The
binary numbers shown below correspond to the hexadecimal operands B6H and 5DH .

1 1 1 1 1 1
1 0 1 1 0 1 1 0
+ 0 1 0 1 1 1 0 1
1 0 0 0 1 0 0 1 1
Therefore,

B6H + 5DH = 113H

which is equivalent to

101101102 + 010111012 = 1 000100112 .

Although the operands are represented in hexadecimal notation for convenience, the
addition is performed internally using binary arithmetic. The hexadecimal representation
simply provides a compact way of expressing the binary operands and the final result.
In the above example, Carry is generated at several intermediate bit positions and is
propagated successively towards the most significant bit (MSB). The final Carry gener-
ated after the addition of the most significant bits becomes the most significant bit of the
result.
The same procedure is applicable to binary numbers of any length, such as 16-bit,
32-bit and 64-bit operands. Thus, multi-bit binary addition is performed by repeatedly
applying the rules of one-bit binary addition together with carry propagation.

Exercise
Complete the following table (Table 3) by converting the given hexadecimal operands
into their binary equivalents. Perform the binary addition and record the final result in
both binary and hexadecimal formats.

Observe and Infer

Answer the following questions.

Q-1: Why are XOR and AND gates sufficient to implement one-bit binary addition?

Q-2: Under what condition is a Carry generated during one-bit binary addition?

Q-3: What is meant by carry propagation? Why is it necessary during multi-bit binary
addition?

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Table 3: Binary Addition Exercises

Operand 1 Operand 2 Sum

Hex Binary Hex Binary Hex Binary
25H 13H
3AH 47H
5CH 2EH
A6H 5DH
B6H 5DH
9A7CH 4B2DH

Q-4: Why does binary addition always begin with the least significant bit (LSB)?

Q-5: Why are hexadecimal numbers commonly used to represent binary data in micro-
processor programming, even though arithmetic operations are performed using
binary numbers?

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3 Activity 2: Binary Addition in the Intel 8085 Mi-

croprocessor
Problem Statement
The Intel 8085 microprocessor performs binary addition using its arithmetic and logic
circuitry, with the accumulator serving as the primary register for arithmetic operations.
The operands involved in an addition may be supplied as immediate data, stored in
processor registers, or stored in memory.
In this activity, binary addition is implemented using different operand sources sup-
ported by the Intel 8085. The addition of immediate data using the ADI instruction is
introduced first, followed by addition using the contents of a register with the ADD instruc-
tion. The use of data stored in memory is then explored, first by transferring memory
data to a register and subsequently by using the memory operand directly through the
H-L register pair with the ADD M instruction.
The results of the different methods are stored in memory locations and examined
using the Intel 8085 programming trainer kit. This provides a progressive understanding
of how the same binary addition operation can be performed with operands obtained
from different sources.

Concept Introduced
This activity introduces the following concepts:

• Immediate data and immediate addressing

• Register-based addition

• Addition using data stored in memory

• Use of the H-L register pair for memory addressing

• Addition using the ADI instruction

• Addition using the ADD instruction

• Addition using the memory operand ADD M

Addition Instructions of the Intel 8085

The Intel 8085 provides different instructions for adding an 8-bit operand to the contents
of the Accumulator. The operand may be supplied as immediate data, obtained from a
processor register, or obtained from the memory location addressed by the H-L register
pair.

Addition of Immediate Data: ADI

The ADI instruction adds an 8-bit immediate operand to the contents of the Accumulator.
The operation is expressed as

A ← A + data (3)

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The immediate operand forms part of the instruction. For example,

1 ADI 13H

adds 13H to the current contents of the Accumulator.

Addition of Register Contents: ADD r

The ADD instruction adds the contents of a specified 8-bit register to the contents of the
Accumulator. The operation is expressed as

A←A+r (4)
where r may be one of the general-purpose registers B, C, D, E, H or L. For example,
1 ADD C

adds the contents of register C to the Accumulator.

Addition of a Memory Operand: ADD M

The ADD M instruction adds the contents of the memory location whose address is con-
tained in the H-L register pair to the Accumulator. The operation is expressed as

A ← A + [HL] (5)
where [HL] denotes the contents of the memory location addressed by the H-L register
pair.
For example, if the H-L register pair contains 2050H and the contents of that memory
location are 25H, the instruction
1 ADD M

performs

A ← A + 25H.
In all three cases, the result of the addition is placed in the Accumulator. The three
instructions therefore differ in the source from which the second operand is obtained.

3.1 Task 1: Addition of an Immediate Operand

Problem Statement
Binary addition in the Intel 8085 microprocessor can be performed by supplying one
operand as immediate data to the ADI instruction. The other operand is first placed in
the Accumulator, which serves as the primary register for arithmetic operations.
In this task, two 8-bit hexadecimal numbers are added using the ADI instruction.
The first operand is loaded into a register and transferred to the Accumulator using
instructions learned in the previous experiment. The second operand is then added as
immediate data. The result of the addition is stored in a specified memory location for
observation.

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Assembly Language Program

The following assembly language program demonstrates the addition of an immediate
operand using the ADI instruction. The first operand is stored at memory location 2050H
and loaded into the Accumulator using the LDA instruction. The second operand is
supplied as immediate data to ADI. The result is then stored at memory location 2051H.
1 LDA 2050H
2 ADI 13H
3 STA 2051H
4 HLT

Machine Language Program

Using the Intel 8085 Instruction Set provided in the instruction set appendix, determine
the corresponding machine code for each assembly language instruction. Record the
answers in the table below before entering the program into the trainer kit.

Table 4: Machine Language Program for Addition Using Immediate Data

Memory Address Machine Code Assembly Instruction

2000H LDA 2050H
2001H
2002H
2003H ADI 13H
2004H
2005H STA 2051H
2006H
2007H
2008H HLT

Procedure
1. Press the RESET key to initialize the trainer kit.

2. Press the EXMEM key and enter the memory address 2050H.

3. Enter the first operand 25H at memory location 2050H using the DATA INS key.

4. Press the RESET key.

5. Press the EXMEM key and enter the starting memory address 2000H.

6. Using the machine code determined in the previous section, enter the complete
program into memory. Press the DATA INS key after entering each byte and use
the NEXT key to advance to the next memory location.

7. Press the RESET key.

8. Press the GO key and enter the starting address 2000H. The program executes the
addition and stores the result at memory location 2051H.

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9. Press the EXMEM key and enter the memory address 2051H. Record the contents
of memory location 2051H in Table 5.

Results
Repeat the addition using the operand combinations given below. For each case, modify
the contents of memory location 2050H and the immediate operand in the ADI instruction.
Execute the program and record the result stored at memory location 2051H.

Table 5: Results of Addition Using Immediate Data

Contents of 2050H Operand in ADI Contents of 2051H

25H 13H
45H 20H
7AH 15H
F5H 20H
A6H 5DH

Observe and Infer

Answer the following questions based on the observations.

Q-1: What value was initially stored at memory location 2050H?

Q-2: What value was stored at memory location 2051H after program execution?

Q-3: Which instruction loaded the first operand into the Accumulator?

Q-4: Which instruction performed the addition of the immediate operand?

Q-5: Why is the result stored at a different memory location from the original operand?

3.2 Task 2: Addition of Register Contents

Problem Statement
The Intel 8085 can perform binary addition using an operand stored in one of its general-
purpose registers. The ADD instruction adds the contents of the specified register to the
contents of the Accumulator, with the result being stored in the Accumulator.
In this task, two 8-bit hexadecimal numbers are loaded into registers B and C. The
contents of register B are transferred to the Accumulator, and the contents of register C
are then added using the ADD instruction. The result is subsequently stored in a memory
location for observation.

Assembly Language Program

The following assembly language program demonstrates binary addition using operands
stored in memory. The first operand is loaded from memory location 2050H into the Ac-
cumulator and then transferred to register B. The second operand is loaded from memory
location 2051H into the Accumulator. The ADD B instruction then adds the first operand

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stored in register B to the second operand in the Accumulator. The result is stored at
memory location 2052H.
1 LDA 2050H
2 MOV B,A
3 LDA 2051H
4 ADD B
5 STA 2052H
6 HLT

Machine Language Program

Using the Intel 8085 Instruction Set provided in the instruction set appendix, determine
the corresponding machine code for each assembly language instruction. Record the
answers in the table below before entering the program into the trainer kit.

Table 6: Machine Language Program for Addition Using Register Contents

Memory Address Machine Code Assembly Instruction

2000H LDA 2050H
2001H
2002H
2003H MOV B,A
2004H LDA 2051H
2005H
2006H
2007H ADD B
2008H STA 2052H
2009H
2010H
2011H HLT

Procedure
1. Press the RESET key to initialize the trainer kit.

2. Press the EXMEM key and enter the memory address 2051H.

3. Enter the first operand 25H at memory location 2051H using the DATA INS key.

4. Press the EXMEM key and enter the memory address 2052H.

5. Enter the second operand 13H at memory location 2052H using the DATA INS
key.

6. Press the RESET key.

7. Press the EXMEM key and enter the starting memory address 2000H.

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8. Using the machine code determined in the previous section, enter the complete
program into memory. Press the DATA INS key after entering each byte and use
the NEXT key to advance to the next memory location.

9. Press the RESET key.

10. Press the GO key and enter the starting address 2000H. The program executes the
addition and stores the result at memory location 2053H.

11. Press the EXMEM key and enter the memory address 2053H. Record the contents
of memory location 2053H in Table 7.

Results
Repeat the addition using the operand combinations given below. Modify the contents
of memory locations 2050H and 2051H before each execution. Record the contents of
memory location 2052H after program execution.

Table 7: Results of Addition Using Register Contents

Contents of
2050H 2051H 2052H
18H 27H
36H 49H
68H 17H
C4H 2BH
D8H 3AH

Observe and Infer

Answer the following questions based on the observations.

Q-1: Which memory location contains the first operand?

Q-2: Which memory location contains the second operand?

Q-3: Which instruction transfers the first operand from memory to register B?

Q-4: Which instruction adds the contents of register B to the Accumulator?

Q-5: How does the method of addition in this task differ from the use of ADI in Task 1?

3.3 Task 3: Addition of Data Stored in Memory

Problem Statement
Multiple data values required for an arithmetic operation may be stored in consecutive
memory locations. The H-L register pair can be used to access these memory locations
sequentially. The ADD M instruction adds the contents of the memory location addressed
by the H-L register pair to the Accumulator.

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In this task, five 8-bit hexadecimal numbers stored in consecutive memory locations
are added. The first number is loaded into the Accumulator, and the remaining numbers
are added sequentially using the ADD M instruction. The INR L instruction is used to
advance the H-L register pair to the next memory location after each addition. The final
result is stored at a specified memory location.
For example, if five numbers are stored at memory locations 2050H to 2054H, the
result of their addition is stored at memory location 2060H.

Assembly Language Program

The following assembly language program demonstrates the addition of five 8-bit hex-
adecimal numbers stored in consecutive memory locations. The H-L register pair is used
to access the memory locations sequentially. The first number is loaded into the Accu-
mulator, and each subsequent number is added using the ADD M instruction. The INR
L instruction advances the H-L register pair to the next memory location after each
addition.
The final result is stored at memory location 2060H.
1 LXI H,2050H
2 MOV A,M
3 INR L
4 ADD M
5 INR L
6 ADD M
7 INR L
8 ADD M
9 INR L
10 ADD M
11 STA 2060H
12 HLT

Machine Language Program

Using the Intel 8085 Instruction Set provided in the instruction set appendix, determine
the corresponding machine code for each assembly language instruction. Record the
answers in the table below (Table 8) before entering the program into the trainer kit.

Procedure
1. Press the RESET key to initialize the trainer kit.

2. Press the EXMEM key and enter the memory address 2050H.

3. Enter the five operands at memory locations 2050H to 2054H using the DATA INS
key and the NEXT key to advance to the next memory location.

4. Press the RESET key.

5. Press the EXMEM key and enter the starting memory address 2000H.

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Table 8: Machine Language Program for Addition of Data Stored in Memory

Memory Address Machine Code Assembly Instruction

2000H LXI H,2050H
2001H
2002H
2003H MOV A,M
2004H INR L
2005H ADD M
2006H INR L
2007H ADD M
2008H INR L
2009H ADD M
2010H INR L
2011H ADD M
2012H STA 2060H
2013H
2014H
2015H HLT

6. Using the machine code determined in the previous section, enter the complete
program into memory. Press the DATA INS key after entering each byte and use
the NEXT key to advance to the next memory location.

7. Press the RESET key.

8. Press the GO key and enter the starting address 2000H. The program accesses the
five operands sequentially using the H-L register pair and adds them using the ADD
M instruction. The final result is stored at memory location 2060H.

9. Press the EXMEM key and enter the memory address 2060H. Record the contents
of memory location 2060H in Table 9.

Results
Repeat the addition using the sets of operands given below (Table 9). Store the five
operands at memory locations 2050H to 2054H, execute the program, and record the
result stored at memory location 2060H.

Table 9: Results of Addition of Data Stored in Memory

Contents of
2050H 2051H 2052H 2053H 2054H 2060H
12H 23H 14H 31H 10H
25H 36H 17H 24H 12H
A5H 38H 27H 16H 14H

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Observe and Infer

Answer the following questions based on the observations.

Q-1: Which memory locations contain the five operands used in the addition?

Q-2: Which register pair is used to access the operands stored in memory?

Q-3: What is the purpose of the INR L instruction in the program?

Q-4: How does the ADD M instruction obtain the operand to be added to the Accumula-
tor?

Q-5: What happens to the result when the sum of the values exceeds FFH?

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4 Activity 3: Observing Carry Using the Flag Reg-

ister
Problem Statement
During an 8-bit binary addition, the result may exceed the maximum value that can be
represented by the 8-bit Accumulator. In such a case, the additional bit is indicated by
the Carry flag of the Intel 8085. The Carry flag therefore provides information about the
result of an addition that cannot be obtained from the 8-bit result alone.
In this activity, the Carry generated during 8-bit binary addition is observed through
the Flag Register. Two 8-bit operands are added using the ADD M instruction. The result
is stored in one memory location, while the contents of the Flag Register are transferred
to another memory location for observation.
Since the trainer kit does not provide direct examination of the Flag Register through
the EXREG facility, the Program Status Word is used. The PUSH PSW instruction
transfers the contents of the Accumulator and Flag Register to the stack, and POP D
transfers these values to the register pair D-E. The Flag Register is thereby made available
in register E and can subsequently be stored in memory.
The observed Flag Register value is then examined to determine whether a Carry
was generated during the addition. Several combinations of 8-bit operands are used to
compare additions that generate a Carry with those that do not.

Concept Introduced
This activity introduces the following concepts:

• Carry generated during 8-bit binary addition

• Carry flag of the Intel 8085

• Flag Register

• Program Status Word (PSW)

• PUSH PSW instruction

• POP D instruction

• Transfer of the Flag Register to memory through register E

Carry in 8-Bit Binary Addition

The Intel 8085 is an 8-bit microprocessor, and the Accumulator can therefore hold values
from 00H to FFH. During the addition of two 8-bit numbers, the mathematical result may
require more than 8 bits. The additional bit generated beyond the most significant bit is
indicated by the Carry flag.
For example,

F5H + 20H = 115H.

The Accumulator can store only the lower 8 bits of the result. Therefore,

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A = 15H
and the additional bit is indicated by

CY = 1.
For an addition that does not exceed FFH, no Carry is generated. For example,

25H + 13H = 38H,

and therefore,

CY = 0.
Thus, the 8-bit result stored in the Accumulator and the Carry flag together provide
information about the complete result of an 8-bit addition.

Accessing the Program Status Word Using PUSH PSW

The Accumulator and Flag Register together form the Program Status Word (PSW). The
PUSH PSW instruction places the contents of the PSW onto the processor stack. Thus,
both the Accumulator and the Flag Register generated during an arithmetic operation
can be preserved for subsequent examination.
The instruction
1 PUSH PSW

does not alter the contents of the Accumulator or the Flag Register. Instead, it saves
their current contents on the stack.

Transferring the Flag Register Using POP D

The POP D instruction transfers two bytes from the stack to the D-E register pair. When
the stack contains the PSW placed there by PUSH PSW, the contents are transferred as
follows:

D←A

E←F
where F denotes the Flag Register.
Thus, the Flag Register becomes available in register E. Its contents can then be stored
in memory using a memory-transfer instruction. This provides a means of observing the
Flag Register when it cannot be examined directly through the trainer kit’s register
examination facility.

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Assembly Language Program

The following assembly language program performs the addition of two 8-bit numbers
stored at consecutive memory locations. The H-L register pair is used to access the
operands. The result of the addition is stored at memory location 2053H. The Program
Status Word is then transferred to the D-E register pair using PUSH PSW and POP D.
The contents of register E, which contain the Flag Register, are subsequently stored at
memory location 2054H.
1 LXI H,2051H
2 MOV A,M
3 INR L
4 ADD M
5 PUSH PSW
6 POP D
7 INR L
8 MOV M,D
9 INR L
10 MOV M,E
11 HLT

Machine Language Program

Using the Intel 8085 Instruction Set provided in the instruction set appendix, determine
the corresponding machine code for each assembly language instruction. Record the
answers in the table below before entering the program into the trainer kit.

Table 10: Machine Language Program for Observing the Carry Flag

Memory Address Machine Code Assembly Instruction

2000H LXI H,2051H
2001H
2002H
2003H MOV A,M
2004H INR L
2005H ADD M
2006H PUSH PSW
2007H POP D
2008H INR L
2009H MOV M,D
2010H INR L
2011H MOV M,E
2012H HLT

Procedure
1. Press the RESET key to initialize the trainer kit.

2. Press the EXMEM key and enter the memory address 2051H.

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Microprocessor Laboratory Experiment 2

3. Enter the first operand F5H at memory location 2051H using the DATA INS key.

4. Press the EXMEM key and enter the memory address 2052H.

5. Enter the second operand 20H at memory location 2052H using the DATA INS
key.

6. Press the RESET key.

7. Press the EXMEM key and enter the starting memory address 2000H.

8. Using the machine code determined in the previous section, enter the complete
program into memory. Press the DATA INS key after entering each byte and use
the NEXT key to advance to the next memory location.

9. Press the RESET key.

10. Press the GO key and enter the starting address 2000H. The program performs
the addition, stores the result at memory location 2053H, and stores the contents
of the Flag Register at memory location 2054H.

11. Press the EXMEM key and examine memory locations 2051H to 2054H. Record
the observed values in Table 11.

Results
Repeat the addition using the operand combinations given below. Store the two operands
at memory locations 2051H and 2052H, execute the program, and record the result and
Flag Register contents at memory locations 2053H and 2054H, respectively.

Table 11: Observation of Carry During 8-Bit Addition

Contents of
2051H 2052H 2053H 2054H
68H 27H
B7H 5AH
D4H 3EH
E9H 47H
34H 25H
72H 16H

Observe and Infer

Answer the following questions based on the observations.

Q-1: For which operand combinations was a Carry generated?

Q-2: For an addition that generated a Carry, what was the value stored at memory
location 2053H?

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Microprocessor Laboratory Experiment 2

Q-3: For an addition that generated a Carry, what was the corresponding value of the
Carry flag in the Flag Register stored at memory location 2054H?

Q-4: Compare the mathematical sum of the two operands with the value stored at mem-
ory location 2053H. What happens when the mathematical sum exceeds FFH?

Q-5: Which bit of the Flag Register represents the Carry flag?

Q-6: Why is the Flag Register required in addition to the 8-bit result stored in the
Accumulator?

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Microprocessor Laboratory Experiment 2

5 Activity 4: Multi-Byte Binary Addition

Problem Statement
The Intel 8085 is an 8-bit microprocessor, and a number containing more than 8 bits must
therefore be processed in separate bytes. During the addition of multi-byte numbers, the
lower-order bytes are added first. If this addition generates a Carry, the Carry must be
included in the addition of the next higher-order bytes.
In this activity, multi-byte binary addition is performed by adding the lower-order
bytes using the ADD instruction and the higher-order bytes using the ADC instruction. The
ADC instruction includes the Carry generated during the preceding lower-byte addition.
Three-digit hexadecimal numbers are used as examples. Each operand is represented
internally by two 8-bit bytes, with the lower-order byte processed first. The result is
assembled from the lower-order and higher-order bytes and stored in consecutive memory
locations.

Concept Introduced
This activity introduces the following concepts:

• Multi-byte binary numbers

• Addition of lower-order and higher-order bytes

• Carry propagation between bytes

• Addition using the ADC instruction

• Representation of multi-byte numbers in consecutive memory locations

Addition of Multi-Byte Binary Numbers

The Intel 8085 processes one byte at a time because its data path is 8 bits wide. There-
fore, a number larger than 8 bits is divided into groups of 8-bit bytes before performing
arithmetic operations. The lower-order byte is added first, followed by the higher-order
byte.
Consider the addition

F 52H + 1E0H .
The operands can be written as

0F 52H + 01E0H .
The lower-order bytes are added first:

52H + E0H = 132H .

Since the Accumulator can store only 8 bits, the lower-order result is 32H , while the
additional bit is stored in the Carry flag.
The higher-order bytes must then be added together with the Carry generated by the
lower-byte addition. Thus, the higher-order addition is

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 Microprocessor Laboratory Experiment 2

0FH + 01H + CY = 0FH + 01H + 1 = 11H .

The complete result is therefore

1132H .
The inclusion of the Carry from the lower-order byte is essential for obtaining the
correct multi-byte result.

Addition with Carry Using ADC

The ADC instruction adds the contents of a specified register or memory location to the
Accumulator together with the Carry flag. The operation performed by ADC is

A ← A + operand + CY (6)
During multi-byte addition, the lower-order bytes are added first using ADD. If this
addition produces a Carry, the Carry flag is set to logic HIGH. The higher-order bytes
are then added using ADC, so that the Carry generated by the lower-order addition is
included automatically.

Assembly Language Program

The following assembly language program performs the addition of two 16-bit binary
numbers stored as two bytes each in consecutive memory locations. The lower-order
bytes are added first using the ADD instruction. The Carry generated during this addition
is preserved and included in the higher-order byte addition using the ADC instruction.
The lower-order result is temporarily stored in register D, while the higher-order byte
of the first operand is stored in register B. The final 16-bit result is stored in consecutive
memory locations 2054H and 2055H.
1 LXI H,2050H ; HL points to the LSB of the first operand
2 MOV A,M ; Load LSB of first operand into A
3 INX H ; Move to MSB of first operand
4 MOV B,M ; Store MSB of first operand in B
5 INX H ; Move to LSB of second operand
6 ADD M ; Add LSBs; Carry is generated if required
7 MOV D,A ; Store the lower-byte result in D
8 INX H ; Move to MSB of second operand
9 MOV A,B ; Load MSB of first operand into A
10 ADC M ; Add MSBs along with the Carry from lower-byte addition
11 INX H ; Move to result location for the LSB
12 MOV M,D ; Store lower-byte result
13 INX H ; Move to result location for the MSB
14 MOV M,A ; Store higher-byte result
15 HLT ; Stop program execution

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Microprocessor Laboratory Experiment 2

Machine Language Program

Using the Intel 8085 Instruction Set provided in the instruction set appendix, determine
the corresponding machine code for each assembly language instruction. Record the
answers in the table below before entering the program into the trainer kit.
Table 12: Machine Language Program for Multi-Byte Binary Addition

Memory Address Machine Code Assembly Instruction

2000H LXI H,2050H
2001H
2002H
2003H MOV A,M
2004H INX H
2005H MOV B,M
2006H INX H
2007H ADD M
2008H MOV D,A
2009H INX H
2010H MOV A,B
2011H ADC M
2012H INX H
2013H MOV M,D
2014H INX H
2015H MOV M,A
2016H HLT

Procedure
1. Press the RESET key to initialize the trainer kit.
2. Press the EXMEM key and enter the memory address 2050H.
3. Enter the four bytes of the two operands at memory locations 2050H to 2053H using
the DATA INS key and the NEXT key to advance to the next memory location.
4. Press the RESET key.
5. Press the EXMEM key and enter the starting memory address 2000H.
6. Using the machine code determined in the previous section, enter the complete
program into memory. Press the DATA INS key after entering each byte and use
the NEXT key to advance to the next memory location.
7. Press the RESET key.
8. Press the GO key and enter the starting address 2000H. The program performs
the lower-byte addition using ADD M and the higher-byte addition using ADC M. The
result is stored at memory locations 2054H and 2055H.
9. Press the EXMEM key and examine memory locations 2054H and 2055H. Record
the observed result in Table 13.

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Microprocessor Laboratory Experiment 2

Results
Perform the multi-byte addition for the operand pairs given below. Express each operand
as two 8-bit bytes and store the lower-order byte first in memory locations 2050H–2051H
and 2052H–2053H, respectively. Execute the program and record the contents of the
result locations 2054H and 2055H.

Table 13: Results of Multi-Byte Binary Addition

Operands Contents of
Operand 1 Operand 2 2050H 2051H 2052H 2053H 2054H 2055H
F 52H 1E0H
A35H 124H
7C8H 295H
B42H 31DH
E8AH 196H
456H 2A3H

Observe and Infer

Answer the following questions based on the observations.

Q-1: How are the given multi-byte hexadecimal operands divided into lower-order and
higher-order bytes?

Q-2: Which memory location stores the lower-order byte of Operand 1?

Q-3: Which memory location stores the higher-order byte of Operand 1?

Q-4: Which instruction performs the addition of the lower-order bytes?

Q-5: What happens to the Carry flag when the addition of the lower-order bytes exceeds
F FH ?

Q-6: Which instruction includes the Carry generated during the lower-byte addition in
the higher-byte addition?

Q-7: Compare the results obtained for cases in which the lower-byte addition generates
a Carry with those in which no Carry is generated.

Q-8: Why would using ADD M instead of ADC M for the higher-order byte produce an
incorrect result when the lower-byte addition generates a Carry?

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Microprocessor Laboratory Experiment 2

6 Activity 5: Addition of BCD Numbers

Problem Statement
Binary-coded decimal (BCD) represents each decimal digit using a 4-bit binary code.
In packed BCD representation, two decimal digits are stored in a single 8-bit byte. Al-
though BCD numbers are stored in binary form, ordinary binary addition does not always
produce a valid BCD result.
In this activity, packed BCD numbers are added using the binary addition instructions
of the Intel 8085. The binary result of the addition is examined to determine whether it
represents a valid BCD number. The DAA instruction is then used to adjust the binary
result so that it represents the correct packed BCD value.

Concept Introduced
This activity introduces the following concepts:

• Binary-coded decimal (BCD) representation

• Packed BCD numbers

• Binary addition of BCD operands

• Invalid BCD result after ordinary binary addition

• Decimal adjustment using the DAA instruction

• Difference between binary and BCD interpretation of a byte

BCD Addition Using Binary Addition

Packed BCD numbers are stored in the same 8-bit format as a binary number, but each
hexadecimal digit is interpreted as a decimal digit. Therefore, the addition of two packed
BCD numbers can initially be performed using the ordinary binary addition instructions
of the Intel 8085.
For example, consider the packed BCD operands

25BCD and 37BCD .

The binary addition performed by the 8085 is

25BCD + 37BCD = 5CH .

Although 5CH is a valid 8-bit binary result, it is not a valid packed BCD number
because the lower 4-bit digit is CH , whereas a BCD digit can represent only the values
0H to 9H .
Thus, ordinary binary addition alone cannot always be used to obtain a valid BCD
result. A decimal adjustment is required when the binary result contains an invalid BCD
digit or when the addition generates a Carry from a BCD digit.

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 Microprocessor Laboratory Experiment 2

Decimal Adjustment Using DAA

The DAA instruction is used to adjust the contents of the Accumulator after the addition
of two packed BCD numbers. The instruction converts the binary result of the addition
into the corresponding valid packed BCD result.
For example, consider

25BCD + 37BCD .
The ordinary binary addition produces

25H + 37H = 5CH .

The result 5CH is not a valid packed BCD number because the lower BCD digit is
greater than 9H . Executing the DAA instruction adjusts the contents of the Accumulator:
DAA
5CH −−→ 62BCD .
The adjusted result therefore represents the correct decimal sum,

25 + 37 = 62.
The DAA instruction examines the result of the preceding addition and the relevant
condition flags to determine whether decimal adjustment is required. Thus, DAA is used
immediately after the binary addition of packed BCD operands when a valid BCD result
is required.

Assembly Language Program

The following assembly language program demonstrates the addition of two packed BCD
numbers and the subsequent decimal adjustment. The operands are stored at memory
locations 2050H and 2051H. The first operand is loaded into the Accumulator and the
second operand is added using the ADD instruction. The binary result is stored at memory
location 2052H. The DAA instruction is then executed to obtain the valid packed BCD
result, which is stored at memory location 2053H.
1 LDA 2050H ; Load the first BCD operand into A
2 MOV B,A ; Store the first operand in register B
3 LDA 2051H ; Load the second BCD operand into A
4 ADD B ; Add the first operand to the second operand
5 STA 2052H ; Store the unadjusted binary result
6 DAA ; Adjust the binary result to valid packed BCD
7 STA 2053H ; Store the adjusted BCD result
8 HLT ; Stop program execution

Machine Language Program

Using the Intel 8085 Instruction Set provided in the instruction set appendix, determine
the corresponding machine code for each assembly language instruction. Record the
answers in the table below before entering the program into the trainer kit.

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Microprocessor Laboratory Experiment 2

Table 14: Machine Language Program for BCD Addition and Decimal Adjustment

Memory Address Machine Code Assembly Instruction

2000H LDA 2050H
2001H
2002H
2003H MOV B,A
2004H LDA 2051H
2005H
2006H
2007H ADD B
2008H STA 2052H
2009H
2010H
2011H DAA
2012H STA 2053H
2013H
2014H
2015H HLT

Procedure
1. Press the RESET key to initialize the trainer kit.

2. Press the EXMEM key and enter the memory address 2050H.

3. Enter the first packed BCD operand 25BCD at memory location 2050H using the
DATA INS key.

4. Press the EXMEM key and enter the memory address 2051H.

5. Enter the second packed BCD operand 37BCD at memory location 2051H using the
DATA INS key.

6. Press the RESET key.

7. Press the EXMEM key and enter the starting memory address 2000H.

8. Using the machine code determined in the previous section, enter the complete
program into memory. Press the DATA INS key after entering each byte and use
the NEXT key to advance to the next memory location.

9. Press the RESET key.

10. Press the GO key and enter the starting address 2000H. The program performs the
BCD addition, stores the unadjusted binary result at memory location 2052H, and
stores the adjusted BCD result at memory location 2053H.

11. Press the EXMEM key and examine memory locations 2050H to 2053H. Record
the observed values in Table 15.

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Microprocessor Laboratory Experiment 2

Results
Repeat the BCD addition using the operand combinations given below. Store the two
packed BCD operands at memory locations 2050H and 2051H. Execute the program and
record the contents of memory locations 2052H and 2053H after program execution.

Table 15: Results of BCD Addition and Decimal Adjustment

Contents of
2050H 2051H 2052H 2053H
Operands Results
25BCD 37BCD
18BCD 21BCD
46BCD 38BCD
57BCD 26BCD
63BCD 19BCD
78BCD 15BCD

Observe and Infer

Answer the following questions based on the observations.

Q-1: Which memory location contains the first packed BCD operand?

Q-2: Which memory location contains the second packed BCD operand?

Q-3: Which memory location contains the result immediately after the ADD instruction?

Q-4: Which memory location contains the result after executing the DAA instruction?

Q-5: For which additions was the result obtained immediately after ADD not a valid
packed BCD number?

Q-6: Compare the contents of memory locations 2052H and 2053H. What change is
produced by the DAA instruction?

Q-7: Why is the DAA instruction required when adding packed BCD numbers?

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Microprocessor Laboratory Experiment 2

7 Summary of Instructions Learned

Table 16 summarizes the Intel 8085 instructions introduced in this experiment.

Table 16: Summary of Instructions Learned

Instruction Purpose
ADI Adds 8-bit immediate data to the contents of the Accumulator.
ADD r Adds the contents of the specified register to the Accumulator.
ADD M Adds the contents of the memory location addressed by the H-L register
pair to the Accumulator.
PUSH PSW Stores the contents of the Accumulator and Flag Register on the stack.
POP D Transfers two bytes from the stack to the D-E register pair.
ADC Adds the specified operand and the Carry flag to the contents of the
Accumulator.
DAA Adjusts the Accumulator contents to form a valid packed BCD result
after BCD addition.

8 Viva Questions
Answer the following questions based on the concepts and experiments performed in this
experiment.

1. What is the role of the Accumulator during an addition operation in the Intel 8085?
[BL1]

2. What is the difference between the ADI and ADD instructions? [BL2]

3. How does the ADD M instruction obtain its operand? [BL2]

4. Why is the H-L register pair used with the operand M? [BL2]

5. What happens when the result of an 8-bit addition exceeds F FH ? [BL2]

6. What is the purpose of the Carry flag in binary addition? [BL1]

7. Why was PUSH PSW used in Activity 3? [BL2]

8. What happens when POP D is executed after PUSH PSW? [BL2]

9. In which register does the Flag Register become available after executing POP D?
[BL1]

10. Why is ADC required for multi-byte binary addition? [BL2]

11. What is the difference between ADD and ADC? [BL2]

12. Why must the lower-order byte be added before the higher-order byte during multi-
byte addition? [BL2]

13. What is packed BCD representation? [BL1]

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Microprocessor Laboratory Experiment 2

14. Why can ordinary binary addition produce an invalid BCD result? [BL2]

15. What is the purpose of the DAA instruction? [BL2]

16. Explain why 25H +37H produces 5CH after ordinary binary addition but 62BCD
after DAA. [BL4]

End of Experiment 2

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