Complete CMOS LDO Design Procedure
Interview-oriented design guide: 1.2 V, 5 mA LDO in TSMC 28-nm CMOS
Important: The CV explicitly states TSMC 28-nm CMOS, a 5-mA LDO, and verification of DC/AC/transient behavior, line
regulation, load regulation, loop stability and compensation. The additional numerical targets in this document are selected
engineering targets for learning and interview preparation; they are not claimed as measured CV results.
1. Working Design Specification
Parameter Working target
Technology TSMC 28-nm CMOS
VIN 1.5–1.8 V
VOUT 1.2 V
VREF 0.6 V
Load current 0.1–5 mA
Dropout ≤100 mV @ 5 mA
COUT 1 µF
Line regulation ≤1 mV/V
Load regulation ≤1 mV/mA
DC loop gain ≥60 dB
Unity-gain frequency ≥1 MHz
Phase margin ≥60°
Gain margin ≥10 dB
PSRR ≥60 dB @ 1 kHz; ≥40 dB @ 100 kHz
Load transient 0.1 ↔ 5 mA
Transient deviation ≤50 mV
Settling time ≤10 µs
Quiescent current ≤50 µA
Temperature −40 to 125 °C
Output noise <100 µV RMS target
2. Choose the LDO Topology
Use a conventional PMOS-pass LDO with a two-stage error amplifier, resistive feedback divider, output capacitor, and
Miller compensation. Conceptually:
VIN → PMOS pass device → VOUT → feedback divider → error amplifier → PMOS gate
The error amplifier compares VFB with VREF. If VOUT falls, VFB falls, the amplifier changes the PMOS gate voltage
so that the PMOS conducts more current, and VOUT recovers.
3. Set the Output Voltage
For a resistor divider:
VFB = VOUT × R2/(R1 + R2)
At regulation, approximately VFB = VREF. Therefore:
VOUT = VREF × (1 + R1/R2)
For VOUT = 1.2 V and VREF = 0.6 V:
R1/R2 = 1 → R1 = R2
Design concept: resistor ratio sets the nominal output; absolute resistor value affects divider current, noise, area and
quiescent current.
4. Define Dropout and Pass-Device Requirement
Dropout is the minimum VIN−VOUT headroom required to maintain regulation at a specified load.
Approximate pass resistance target:
RON ≈ VDO / ILOAD
For 100 mV at 5 mA:
RON ≈ 0.1/0.005 = 20 Ω
For a PMOS pass transistor, increase W to reduce conduction resistance and support current. But increasing W also
increases gate capacitance, which can move poles and make compensation harder.
28-nm caution: Do not use the long-channel square-law equation as an exact final sizing method. Use it for intuition/initial
estimates, then size the device with PDK models and DC/PVT simulations.
5. Size the Error Amplifier
A practical two-stage OTA can be organized as: differential input pair → active load/current mirror → second gain
stage → PMOS gate.
Core MOS relations used for initial design:
VOV = VGS − VTH (NMOS); VOV = VSG − |VTH| (PMOS)
gm ≈ 2ID/VOV
ro ≈ 1/(λID)
Av ≈ gm × ro
gm/ID ≈ 2/VOV (long-channel intuition)
Design concept: choose operating currents and overdrive voltages to balance gain, power, headroom, matching and
speed. Final dimensions come from PDK simulation.
6. Establish Biasing
Generate stable bias currents using current mirrors. A simple mirror ideally gives IOUT/IREF ≈ (W/L)OUT/(W/L)REF.
Real mirrors have finite output resistance, compliance requirements, mismatch and PVT dependence.
Check every mirror transistor for the intended operating region across VIN, load and temperature.
7. Estimate DC Loop Gain
A useful first-order loop-gain model is:
T(s) ≈ AEA(s) × APASS(s) × β
β = R2/(R1 + R2)
Target: DC loop gain ≥60 dB, i.e. |T(0)| ≥1000.
Higher low-frequency loop gain improves output accuracy, line regulation and load regulation, but excessive amplifier
gain can make compensation more difficult.
8. Line Regulation
Definition:
Line regulation = ∆VOUT/∆VIN
Target ≤1 mV/V. For a 0.3-V input change, the allowed output change is approximately 0.3 mV.
Concept: input disturbances couple through the pass device and parasitics; feedback senses the output error and
corrects it. High low-frequency loop gain improves rejection.
9. Load Regulation
Definition:
Load regulation = ∆VOUT/∆ILOAD
Target ≤1 mV/mA. From 0.1 mA to 5 mA, ∆ILOAD = 4.9 mA, giving ≤4.9 mV output variation for this target.
Concept: load changes disturb VOUT; the feedback loop changes pass-device current until a new equilibrium is
reached.
10. Identify the Important Poles
Important dynamic nodes include the error-amplifier high-impedance node, PMOS gate, and output node.
A simplified pole estimate is:
fp ≈ 1/(2πRC)
The output pole is strongly dependent on the effective output resistance and COUT. Because the effective load
resistance changes with load current, pole locations can move with load.
11. Compensation and Miller Capacitor
Add a compensation capacitor CC around the high-gain stage to create a controlled dominant pole and separate
higher-frequency poles (pole splitting).
Conceptually: compensation lowers the dominant pole frequency while pushing another pole to a higher frequency.
The objective is to make the loop cross 0 dB before excessive phase lag accumulates.
Important: the exact CC value must be selected from the actual small-signal model and verified with AC analysis. Do not
assume a universal formula gives the final value for a 28-nm LDO.
12. Phase Margin and Gain Margin
At unity-gain frequency fu, where |T| = 1 (0 dB):
PM = 180° + phase(T) at fu
At the frequency where phase(T) = −180°:
GM = −20log10|T|
Targets: PM ≥60°, GM ≥10 dB.
Interpretation: PM indicates tolerance to additional phase lag; GM indicates tolerance to additional loop gain before
oscillation. Check both across load, VIN, temperature and process corners.
13. Unity-Gain Frequency and Bandwidth
Unity-gain frequency is where |T(jω)| = 1. Use AC analysis to find the 0-dB crossing.
Target fu ≥1 MHz. Do not maximize fu blindly: increasing bandwidth can reduce phase margin and increase sensitivity
to parasitics/noise.
14. Output Capacitor, ESR and Transient Response
The output capacitor supplies the initial current during a fast load step:
I = C dV/dt
The capacitor's ESR creates an approximately instantaneous step:
∆VESR ≈ ∆I × ESR
Test 0.1 ↔ 5 mA. Target |∆VOUT| ≤50 mV and settling time ≤10 µs. Simulate both load increase and load decrease.
15. PSRR
PSRR measures rejection of input ripple:
PSRR = 20log10(|VIN,ripple|/|VOUT,ripple|)
Targets: ≥60 dB at 1 kHz and ≥40 dB at 100 kHz.
At low frequency the loop has high gain and can actively correct input disturbances. At high frequency loop gain falls
and parasitic feedthrough becomes increasingly important.
16. Quiescent Current and Efficiency
Quiescent current is the LDO's internal current consumption excluding the load current. Target IQ ≤50 µA.
Efficiency:
η = VOUT IOUT/(VIN IIN)
At light load, IQ becomes significant. For an LDO, even with zero IQ, the basic voltage-conversion limit is
approximately η ≈ VOUT/VIN.
17. Startup
Apply VIN from zero or a defined initial condition and observe VOUT. Check startup time, monotonicity, overshoot,
inrush current and settling.
A large COUT stores more energy and can increase startup charging demand. Startup must be checked separately
from steady-state regulation.
18. Noise
Relevant noise sources include the reference, error amplifier, bias devices, MOS devices and feedback resistors.
Target output RMS noise: <100 µV over the specified measurement bandwidth. Use noise analysis and identify
dominant contributors rather than reporting only a final number.
19. PVT and Corner Verification
Sweep process corners (for example TT, SS, FF and relevant mixed corners), VIN, load current and temperature. For
this working specification use −40 to 125 °C.
At every relevant corner check: VOUT, dropout, line regulation, load regulation, IQ, loop gain, PM, GM, unity-gain
frequency, PSRR, transient response and startup.
Also sweep the specified COUT and ESR range if the intended application permits capacitor variation.
20. Recommended Cadence/Spectre Simulation Sequence
1. DC operating point — Confirm every transistor is biased correctly and the LDO regulates near 1.2 V.
2. VIN sweep — Extract line regulation and locate dropout.
3. Load sweep — Sweep 0.1–5 mA and extract load regulation.
4. AC loop analysis — Break/inject the loop correctly and plot gain/phase; extract DC loop gain, fu, PM and GM.
5. COUT/ESR sweep — Check stability and transient behavior across the allowed output-capacitor range.
6. PSRR — Inject small-signal VIN ripple and calculate VOUT/VIN versus frequency.
7. Load transient — Apply 0.1↔5 mA steps; measure undershoot, overshoot and settling.
8. Startup transient — Ramp VIN and/or release enable; measure startup behavior.
9. Noise — Run noise analysis and integrate output noise over the defined bandwidth.
10. PVT — Repeat critical tests across process, voltage, temperature and load.
21. How the Parameters Interact
Pass-device W ↑ → RON ↓ and current capability ↑, but gate capacitance ↑ →
compensation/stability may become harder.
COUT ↑ → generally less immediate capacitor droop for a load step, but pole locations,
startup and loop bandwidth change.
Loop gain ↑ → better DC regulation and disturbance rejection, but potentially harder
compensation.
UGF ↑ → potentially faster response, but PM can fall if higher-frequency poles are not
controlled.
IQ ↓ → better light-load efficiency, but available amplifier bandwidth/gain and transient
performance may become constrained.
22. Final Interview Answer: 'How Would You Design This LDO?'
A strong concise answer is: “I would start from the required 1.2-V output and 5-mA maximum load in TSMC 28-nm
CMOS. I would choose a PMOS-pass architecture and establish the feedback ratio from VOUT and VREF. Then I
would size the pass device for the required current and dropout using the PDK models, design the error amplifier and
bias network for sufficient DC gain and transconductance, identify the amplifier, gate and output poles, and choose
compensation to achieve the required unity-gain frequency with at least 60° phase margin. I would then verify DC
regulation, dropout, load and line regulation, AC loop stability, PSRR, load transients, startup and noise, followed by
full PVT, load and COUT/ESR sweeps. I would iterate sizing and compensation until all specifications are met with
margin.”
23. Key Equations to Memorize
VOUT = VREF(1 + R1/R2)
β = R2/(R1 + R2)
T(s) ≈ AEA(s) × APASS(s) × β
Line regulation = ∆VOUT/∆VIN
Load regulation = ∆VOUT/∆ILOAD
RON ≈ VDO/ILOAD
gm ≈ 2ID/VOV
ro ≈ 1/(λID)
Av ≈ gmro
fp ≈ 1/(2πRC)
PM = 180° + phase(T) at |T| = 1
GM = −20log10|T| at phase(T) = −180°
PSRR = 20log10(|VIN,ripple|/|VOUT,ripple|)
I = C dV/dt
∆VESR ≈ ∆I × ESR
η = VOUT IOUT/(VIN IIN)
24. Interview Caution
Do not present the selected numerical targets in this document as measured results from your actual project unless you confirm
them from your simulations. The CV supports the architecture/project scope and the categories of analysis, but not these
additional numerical performance values.