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Input Ordering Delay Effect:
The logical effort and parasitic delay of different gate inputs are different. Some logic
gates, like the AO121 are inherently asymmetric in that one input sees less capacitance
than another.
Other gates, like NANDs and NORs. are nominally symmetric but have slightly different
logical effort and parasitic delays for the different inputs.
Ex: 2-input NAND gate annotated with diffusion
capacitance.
2 2 Y 1
A 6C 0 1 1
1 1
B 2
1 0
Consider the falling output transition
the other rises from 0 to 1
occurring when one
input held a stable 1 value and
If input B rises last. node x will initially be at VDD - Ii VDD because it
through the nMOS transistor on input A. The Elmore delay=is was pulled
up
(R/2)(2C) R(6C) 7RC +
=
On the other hand. if
input A rises last, nodex will initially be at 0 V because it
discharged through the nMOS transistor on input B. was
No charge must be delivered to node x. so the Elmore delay is simply R(6C) =
6RC
the outer input to be the
input closer to the supply rail (e.g., B) and the inner input
the input closer to the to be
output (e.g.. A).
The parasitic delay is smallest when the inner
intermediate nodes have already been input switches last because the
discharged.
Therefore. if one signal is known to arrive
later than the others. the
that signal is connected to the inner gate is fastest when
input.
Asymmetric Gates: When one input is far less critical than another,
Ex: suppose input A of a NAND gate is most eritical
Use smaller transistor on A(less capacitanee)
Boost size of noneritical input
So total resistance is same
reset
gA=10/9
2
4/3 gB- 2
reset
4
gtotal =gA+gB-28/9
(b
Asymmetric gate approaches g=l on critical input but total logical effort goes up.
Skewed Gates: One input transition is more important than the other.
HI-skew gates to favor the rising output transition and
LO-skew gates to favor the falling output transition.
This favoring can be done by decreasing the size of the noncritical transistor.
The logical efforts for the rising (up) and falling (down) transitions are called gu and gd.
respectively.
Logical effort of a skewed gate for a particular transition is the ratio of the input
capacitance of that gate to the input capacitance of an unskewed inverter delivering
the same output current for the same transition.
Figure (a) shows howa HI-skew inverter is constructed by downsizing the nMOS
transistor.
HI-skew Unskewed Inverter Unskewed Inverter
Inverter (equal rise resistance) (equal fall resistance)
A
[2 A
2 Y A
[/2 1/2
(a) (b) (c)
Compare with unskewed inverter of the same rise/fall time.
Logical Effort for rising (up) output: gu=5/6
Logical Effort for falling (down) output: gd=5/3
Average Logical Effort: gavg= (gu+gd)/2=5/4
Catalogs Hi skew and LO-skew gates:
Inverter NAND2 NOR2
B- 4
2 A
Unskewed A Y
9u =1 B 9u 4/3 11 9u 5/3
9d1 94 4/3 9d 5/3
Savg1 Savg=4/3 Savg5/3
A
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A
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A
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