Module-2: Mrs.
SHILPA A P
Assistant Professor
Dept. of ECE,
Fabrication
nMOS Fabrication:
Semiconductor device fabrication is the process of creating integrated circuits in multiple-step
sequence of photolithographic and chemical processing during which electronic circuits are
gradually created on a wafer made of pure semiconducting material.
The following steps gives general aspect of nMOS fabrication process.
1. Processing is carried on thin wafer cut from single silicon crystal of high purity to which p-type
impurities are introduced as crystal is grown. Wafers are around 75 to 150 mm in diameter and 0.4
mm thick. They are doped with boron (p-type) impurity concentration of 1015/cm3 to 1016 /cm3.
2. On this a thick layer if silicon dioxide (SiO2) of 1μm. This protects the surface, act as barrier to
dopants and act as an insulating layer on which other layers can be deposited and patterned.
3. The surface is now covered with photoresist, and it is spun to achieve even distribution of
required thickness.
4. A mask is used and the photoresist layer on the wafer is exposed to UV light. Mask defines
those regions into which diffusion will take place and these regions remain unaffected after
exposing to UV light and other region gets hardened.
5. The UV exposed regions are etched away along with the silicon dioxide layer so that the wafer
surface is exposed in the window defined by the mask.
6. The remaining photoresist is removed and a thin layer of SiO2 is grown over entire surface and
then polysilicon is deposited on top of this to form gate structure.
7. The thin oxide is removed to expose areas into which n-type impurities are diffused to form
source and drain.
8. Thick oxide is grown all over again and then masked with photoresist and etched to expose
selected area of polysilicon gate and drain and the source areas where connections are to be made.
9. The whole chip is then has metal (Al) deposited over its surface to a thickness of 1μm. This
metal layer is then masked and etched to form the required interconnection pattern.
Fig below depicts the nMOS fabrication steps:
(1) Si with p-type impurities
(2) Thin layer of SiO2 on
substrate
(3) Photoresist on the layer of
SiO2
(4) Photoresist layer exposed to
UV light through mask
CMOS Fabrication:
There are several methods for CMOS fabrication, which includes p-well, n-well, twin tub and
silicon-on-insulator (SOI) processes. The p-well process is widely used and the n-well process as
it is a retrofit to existing nMOS technology.
The p-well Process:
Fig: CMOS p-well inverter showing VDD and VSS substrate connections
The p-well structure has an n-type substrate in which p-type devices can be formed with the help
of masking and diffusion. To accommodate n-type devices, deep p-well is diffused into the n-type
substrate. This is shown in Fig 1.
Masking, patterning, and diffusion process is same as that of nMOS fabrication. The summary of
processing steps is:
Mask1: defines the areas in which the deep p-well diffusion must take place.
Mask 2: defines the thin oxide region (where the thick oxide is to be removed or stripped and thin
oxide grown)
Mask 3: patterning the polysilicon layer which is deposited after thin oxide.
Mask 4: A p+ mask is used (to be in effect “AND” with mask 2) to define areas where p-diffusion
is to take place.
Mask 5: –ve form of mask 4 (p+ mask) is used which defines areas where n-diffusion is to take
place.
Mask 6: Contact cuts are defined using this mask.
Mask 7: The metal layer pattern is defined by this mask.
Mask 8: An overall passivation (over glass) is now applied, and it also defines openings for
accessing pads.
• In the process, the diffusion should be carried out with special care as p-well concentration and
depth will affect the threshold voltage and the breakdown voltage of the n-transistor.
• To achieve low threshold voltage either deep-well diffusion or high-well resistivity is required.
• But deep well require larger spacing between n- and p-type transistors and wires due to lateral
diffusion and therefore needs larger chip area.
• The p-well acts as substrate for n-devices within parent n-substrate and two areas are electrically
isolated
The n-well Process:
The p-well processes have been one of the most commonly available forms of CMOS. However,
an advantage of the n-well process is that it can be fabricated on the same process line as
conventional n MOS.
• n –well CMOS circuits are also superior to p-well because of the lower substrate bias
effects on transistor threshold voltage and inherently lower parasitic capacitances
associated with source and drain regions.
• Typically, n-well fabrication steps are like a p-well process, except that an n-well is used
which is illustrated in flow diagram
• The first masking step defines the n-well regions.
• The well depth is optimized to ensure against p-substrate to p+ diffusion breakdown
without compromising the n-well to n+ mask separation.
• The next steps are to define the devices and diffusion paths, grow field oxide, deposit, and
pattern the polysilicon, carry out the diffusions, make contact cuts and metallization.
• An n-well mask is used to define n-well regions, as opposed to a p-well mask in a p-well
process.
Fig. Depicts inverted circuit fabricated by n-well process.
The Twin-Tub process:
• Twin-tub CMOS technology provides the basis for separate optimization of the p-type and n-
type transistors, thus making it possible for threshold voltage, body effect, and the gain associated
with n- and p-devices to be independently optimized.
• Generally, the starting material is either an n+ or p+ substrate with a lightly doped epitaxial or
epi layer, which is used for protection against latch-up.
• The aim of epitaxial is to grow high purity silicon layers of controlled thickness with accurately
determined dopant concentrations distributed homogeneously throughout the layer. The electrical
properties for this layer are determined by the dopant and its concentration in the silicon.
MOS Circuit Design Processes:
The design process can be understood by means of stick diagrams and symbolic diagrams along
with set of design rules.
Design rules: is a communication link between designers specifying the requirements and the
fabricator.
MOS Layers:
MOS circuits are basically formed by 4 layers
▪ Metal ▪ Polysilicon ▪ N diffusion ▪ P diffusion
Here all the 4 layers are isolated from each other through thick or thin oxide layer (i.e., silicon
dioxide layer)The thin oxide (thinox) layer includes n-diffusion, p-diffusion and transistor channel.
Stick diagram:
• Stick diagrams are a means of capturing topography and layer information using simple diagrams.
• They convey layer information through color codes (or monochrome encoding).
• Acts as an interface between symbolic circuit and the actual layout.
• Stick diagrams do show all components/vias(contacts), relative placement of components and
helps in planning and routing. It goes one step closer to layout.
• However, they do not show exact placement of components, transistor sizes, length, and width
of wires also the boundaries. Thus, we can say that it does not give any low-level details.
• The color encodings chosen for different technologies is shown below.
Encodings for NMOS process:
Procedure to draw Stick Diagram:
Nmos Design Process:
1) Draw two metal lines/ power rails providing sufficient space to accommodate all transistors. i.e: Vdd
& Vss.
2) Draw common n+ diffusion layer for all the transistors.
3) Provide Vdd and Vss contacts.
4) Draw polysilicon to cross n+ diffusion layer to form transistors.
5) Create buried contact for depletion transistor.
6) Provide input and output connection.
CMOS Design Process:
• Two type of transistors are used i.e: Nmos and Pmos, thus in stick diagram demarcation line is
used to separate them.
• All Pmos transistors are placed above Demarcation line and Nmos transistors below demarcation
line.
• While drawing stick Diagram
1. Diffusion paths must not cross the demarcation line
2. N-diffusion and P-diffusion wires must not join.
3. Nmos and Pmos transistors are joined by Metal layer when it is required.
4. Cross must be placed on Vdd and Vss which represent substrate and P-well connection
respectively.
Procedure to draw Stick Diagram:
1) Draw two metal lines/ power rails providing sufficient space to accommodate all transistors. i.e: Vdd
& Vss.
2) Draw demarcation line in the middle of the two power lines.
3) Draw P+ diffusion above demarcation and N+ diffusion below demarcation
4) Draw polysilicon to represent Pmos and Nmos which represents gates of the transistor.
5) Connect source terminal of transistors to supply.
6) Drain terminals of transistor are connected using metal 1.
7) Place contact cuts wherever necessary.
8) Draw X which represents substrate and P-well contact on power lines.
Encodings for CMOS process:
Design rules: Are set of guidelines which specify minimum dimension and spacing allowed in
layout drawing. Design rules also acts a communication link between circuit designers and process
engineers during manufacturing phase.
Goal of design rule is to achieve optimum yield. Yield = (No. of good chips on wafer)/(Total no.
of chips on wafer).
Design rules are also called layout rules. If the circuit performance has to be increased, then rules
must be more aggressive. Else this leads to non-function of the circuit or yield reduction.
There are two rules.
1. Micron Rule - Absolute Dimension rule, here all sizes and spacing are specified in micron. Here
the circuit density is the important goal.
2. Lambda (λ) Based Rules - The Lambda based design rules are Proposed by Mead and Conway.
Scalable design rules, here this design rule normalizes all geometric design rule by parameter
lambda (λ) also called as scaling factor/feature size. In this all-mask patterns are expressed as
multiples of lambda.
Advantages of lambda-based design rules:
1. The mask layout can be scaled down proportionally if the feature size of the fabrication process
is reduced.
2. Design rules are conservative.
3. This rule enable technology changes and design reuse and reduced design cost.
Disadvantages:
1. Linear scaling cannot be extended and is limited over range of dimension (1-3 μm)
2. As rules are conservative, results in over dimension and density of design is less.
Transistor design rules:
▪ Minimum dimension of transistor is 2λ × 2λ – overlapping of diffusion and ploy
▪ Poly and diffusion both must extend beyond the boundary of transistor at least by 2λ.
▪ Implant for depletion mode transistor is 6λ × 6λ i.e., implant must extend boundary of transistor
by at least 2λ in all direction.
▪ From the boundary/ implant of one transistor, the next transistor should maintain min distance of
2λ.
▪ The distance from contact cut to transistor should be at least 2λ.
Metal contact – contact between metal 1 to polysilicon OR metal 1 to diffusion (active region)
is called metal contact. This is shown in fig. 3
▪ A 2λ × 2λ cut centered on 4λ × 4λ superimposed area is used to connect layers
▪ In case of multiple contacts, the distance between adjacent contacts should be 2λ
Via contact – the contact between metal 1 and metal 2 is called via contact as shown in fig. 4.
▪ A 2λ × 2λ cut centered on 4λ × 4λ superimposed area is used to connect layers
▪ To connect metal 2 with diffusion via and cut both are used