MOS Devices & Analog Design — Numerical Question Paper

MOS DEVICES AND ANALOG DESIGN FUNDAMENTALS

Numerical Class Test — Question Paper
Full Marks: 100 | 6 Modules × 5 Problems = 30 Problems | Time: 3 Hours

Instructions
1. Answer all questions. Each problem must be solved by writing the governing equation, substituting values with
correct units, and stating the final numerical answer.
2. Show all intermediate steps; unsupported final answers will receive partial credit only.
3. Use k = 1.38 × 10⁻²³ J/K and ε0 = 8.854 × 10⁻¹² F/m wherever required.
4. Marks for each problem are indicated alongside the question.

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 MOS Devices & Analog Design — Numerical Question Paper

SECTION — QUESTIONS
Module 1 — MOS Device Basics and DC Operation (5 questions)
Q1.1 Oxide Capacitance and Gate Capacitance (4 marks)
A MOS structure uses SiO2 with tox = 5.5 nm. Take εox = 3.9ε0 and ε0 = 8.854 × 10⁻¹² F/m. Calculate: (a) Cox in
F/m², (b) Cox in fF/µm², and (c) the ideal gate oxide capacitance for W = 18 µm and L = 0.6 µm.

Q1.2 Region of Operation and Drain Current (5 marks)

An NMOS has VTH = 0.42 V, µnCox = 260 µA/V², W/L = 12 and VGS = 0.92 V. Determine the operating region
and ID for (a) VDS = 0.10 V, (b) VDS = 0.35 V and (c) VDS = 1.0 V. Ignore channel-length modulation.

Q1.3 Sizing from Current and Overdrive (4 marks)

A designer requires ID = 0.8 mA at VOV = 0.20 V. If µnCox = 320 µA/V², calculate the required W/L. For L =
0.36 µm, find W. If VTH = 0.45 V, also obtain the required VGS.

Q1.4 Channel-Length Modulation (4 marks)

A transistor has ID0 = 0.50 mA when the channel-length modulation term is neglected and λ = 0.06 V ⁻¹. Calculate
ID at VDS = 0.5, 1.0, 1.5 and 2.0 V using ID = ID0(1 + λVDS). Determine the percentage current increase from
0.5 V to 2.0 V.

Q1.5 Body Effect (4 marks)

For an NMOS, VTH0 = 0.40 V, γ = 0.45 V^0.5 and 2φF = 0.70 V. Calculate VTH at VSB = 0, 0.4 and 1.0 V. If
VGS = 1.0 V, determine the corresponding overdrive voltage in each case.

Module 2 — Large-Signal to Small-Signal Models (5 questions)

Q2.1 gm, gds and ro (4 marks)
An NMOS is biased at ID = 0.60 mA with VOV = 0.24 V and λ = 0.04 V⁻¹. Calculate gm, gds, ro, and the intrinsic
gain magnitude gm·ro.

Q2.2 Common-Source Gain with Finite Output Resistance (4 marks)

A common-source stage has gm = 5.5 mS, ro = 70 kΩ, RD = 12 kΩ and RL = 50 kΩ. Calculate the midband gain
Av = −gm(RD∥ro∥RL). Recalculate if ro is neglected and find the percentage difference.

Q2.3 Source Degeneration (4 marks)

A common-source amplifier has gm = 7 mS, RD = 10 kΩ and an unbypassed source resistance RS = 350 Ω.
Neglect ro. Determine the gain with and without source degeneration. By what factor is the gain magnitude
reduced?

Q2.4 Body Transconductance (4 marks)

For an NMOS biased at gm = 6 mS, let γ = 0.50 V^0.5, 2φF = 0.65 V and VSB = 0.35 V. Calculate gmb from gmb
= gm·γ / (2√(2φF+VSB)). Find the ratio gmb/gm. If vgs = 10 mV and vbs = 5 mV, estimate the incremental drain
current neglecting ro.

Q2.5 Bias-to-Gain Design (5 marks)

An NMOS common-source stage must provide a low-frequency gain of approximately −20 V/V using RD = 8 kΩ.
Neglect ro. Find the required gm. If VOV = 0.25 V, determine ID. With VDD = 1.8 V, calculate the DC drop
across RD and the quiescent drain voltage. Comment on whether the assumed bias is physically reasonable for
saturation.

Module 3 — MOS Capacitances and Miller Effect (5 questions)

Q3.1 Intrinsic and Overlap Cgs (4 marks)
A long-channel NMOS in saturation has W = 30 µm, L = 0.5 µm and Cox = 7.0 fF/µm². The gate-source overlap
capacitance density is C'gso = 0.22 fF/µm. Calculate Cgs,int, Cgso and total Cgs.

Q3.2 Drain-Body Junction Capacitance (4 marks)

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 MOS Devices & Analog Design — Numerical Question Paper

A drain-body junction has Cj0 = 180 fF, φ0 = 0.75 V and grading coefficient m = 0.5. Calculate Cj for reverse
biases of 0, 0.5, 1.0 and 2.0 V. Determine the percentage reduction between 0 and 2.0 V.

Q3.3 Miller Multiplication (4 marks)

A common-source stage has Cgs = 120 fF, Cgd = 18 fF and Av = −16. Calculate (a) the Miller input capacitance
due to Cgd, (b) total effective input capacitance, and (c) the output-side equivalent contribution of Cgd using
Cgd(1 − 1/Av).

Q3.4 Gain Dependence of Input Capacitance (4 marks)

For Cgs = 150 fF and Cgd = 20 fF, calculate total effective input capacitance for Av = −5, −10, −20 and −40.
Determine the ratio Cin(−40)/Cin(−5).

Q3.5 Capacitance Budget of a Drain Node (5 marks)

A drain node has Cdb = 55 fF, wiring capacitance 40 fF, load capacitance 120 fF and Cgd = 15 fF. The stage gain
is Av = −12. Calculate the output-side equivalent of Cgd and the total capacitance loading the drain node. If the
equivalent resistance seen at the node is 9 kΩ, estimate its pole frequency.

Module 4 — Parasitics and Interconnects (5 questions)

Q4.1 Metal-Line Resistance (4 marks)
A metal line has resistivity ρ = 2.7 × 10⁻⁸ Ωm, length 1.2 mm, width 1.8 µm and thickness 0.45 µm. Calculate its
resistance. If the width is doubled with all other dimensions unchanged, find the new resistance.

Q4.2 Sheet-Resistance Method (4 marks)

A polysilicon resistor has sheet resistance R□ = 55 Ω/□, length 48 µm and width 2 µm. Calculate its resistance
from the number of squares. If two identical resistors are connected in parallel, calculate the effective resistance.

Q4.3 Lumped Node Time Constant (4 marks)

A high-impedance node sees Req = 18 kΩ and Ceq = 260 fF. Calculate the time constant, pole frequency and
approximate 10–90% rise time. Recalculate the pole if an additional probe capacitance of 140 fF is attached.

Q4.4 Distributed RC Interconnect (4 marks)

An interconnect has R' = 0.12 Ω/µm and C' = 0.20 fF/µm over a length of 2.5 mm. Calculate Rtot, Ctot and td ≈
0.38·Rtot·Ctot. If the length is reduced to 1.25 mm, determine the new delay and verify the approximate ℓ² scaling.

Q4.5 Parasitic Pole after Layout Extraction (4 marks)

Before layout, an amplifier output node was estimated to have C = 90 fF and Rout = 15 kΩ. Post-layout extraction
adds 65 fF of wiring capacitance and 45 fF of junction/fringing capacitance. Calculate the pre-layout and post-
layout pole frequencies. Find the percentage reduction in pole frequency.

Module 5 — Frequency Response (5 questions)

Q5.1 Single-Pole Response (4 marks)
An amplifier has A0 = −60 V/V and fp = 0.8 MHz. Calculate |A| and gain in dB at 0.08, 0.8, 8 and 80 MHz. State
the expected asymptotic slope beyond the pole.

Q5.2 Two-Pole Response (5 marks)

A voltage amplifier has A0 = 100 V/V, fp1 = 200 kHz and fp2 = 8 MHz. Calculate the exact magnitude (and dB) at
20 kHz, 200 kHz, 2 MHz, 8 MHz and 80 MHz. Identify the approximate slopes in the three frequency regions
separated by the poles.

Q5.3 Input Pole Due to Miller Effect (4 marks)

A common-source stage has Rsig = 25 kΩ, Cgs = 110 fF, Cgd = 22 fF and Av = −18. Determine the Miller input
capacitance, total input capacitance and input pole frequency. Repeat the pole calculation if the gain magnitude is
reduced to 9 while all physical capacitances remain unchanged.

Q5.4 Transition Frequency (4 marks)

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 MOS Devices & Analog Design — Numerical Question Paper

A MOSFET has gm = 9 mS, Cgs = 260 fF and Cgd = 35 fF. Estimate fT. Then calculate fT if gm rises to 13.5 mS
but total capacitance rises by 20% because a larger device is used. Compare the two cases.

Q5.5 Competing Input and Output Poles (5 marks)

A common-source amplifier has Av = −14, Rsig = 12 kΩ, Cgs = 140 fF and Cgd = 16 fF. At the output, Rout = 11
kΩ and Cdb + CL = 180 fF. Use Miller transformation to calculate both input and output poles. Identify the
dominant pole and estimate the overall upper cutoff frequency.

Module 6 — Noise (5 questions)

Q6.1 Resistor Thermal Noise (4 marks)
A 22 kΩ resistor operates at 300 K. Calculate its voltage-noise density in nV/√Hz and RMS noise voltage over
bandwidths of 10 kHz, 100 kHz and 2 MHz. Take k = 1.38 × 10⁻²³ J/K.

Q6.2 MOS Channel Thermal Noise (4 marks)

An NMOS operates at 300 K with gm = 5 mS and γ = 2/3. Calculate Sid (drain-current noise density, in pA/√Hz),
input-referred voltage-noise density (in nV/√Hz), and RMS input-referred thermal noise over a 5 MHz bandwidth.

Q6.3 Effect of gm on Input-Referred Noise (4 marks)

For T = 300 K and γ = 2/3, calculate input-referred MOS thermal-noise density for gm = 1, 2, 5 and 10 mS. Verify
numerically that the voltage-noise density varies as 1/√gm. By what factor must gm increase to halve the voltage-
noise density?

Q6.4 Flicker Noise and Corner Frequency (4 marks)

A MOS input device has a white input-referred noise density of 3 nV/√Hz. At 100 Hz, the flicker-noise voltage
density alone is 12 nV/√Hz and follows a 1/√f amplitude dependence. Determine the flicker-noise density at 1 kHz
and 10 kHz. Find the corner frequency at which the flicker-noise PSD equals the white-noise PSD.

Q6.5 Input-Referred Noise Budget (5 marks)

An amplifier input sees three uncorrelated noise sources: MOS thermal noise en1 = 2.8 nV/√Hz, resistor noise en2
= 5.0 nV/√Hz and a second device contribution en3 = 1.5 nV/√Hz. Calculate the total input-referred white-noise
density using root-sum-square addition. Estimate RMS noise in a 1 MHz ideal rectangular bandwidth. If the signal
is 1 mV RMS at the input, compute the resulting signal-to-noise ratio in dB.

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SECTION — ANSWER KEY (Numerical Solutions)

Final numerical results are given below; students should verify by re-deriving each step from the governing equations.

Module 1 — MOS Device Basics and DC Operation

A1.1 Oxide Capacitance and Gate Capacitance
Cox = εox/tox = (3.9 × 8.854×10⁻¹²) / 5.5×10⁻⁹ = 6.28 × 10⁻³ F/m²
Cox = 6.28 fF/µm²
Gate capacitance = Cox·W·L = 6.28 × 18 × 0.6 ≈ 67.8 fF

A1.2 Region of Operation and Drain Current

VOV = VGS − VTH = 0.92 − 0.42 = 0.50 V
(a) VDS = 0.10 V < VOV → Triode; ID = µnCox(W/L)[VOVVDS − VDS²/2] = 260µ×12×[0.5×0.1 − 0.005] =
140.4 µA
(b) VDS = 0.35 V < VOV → Triode; ID = 354.9 µA
(c) VDS = 1.0 V ≥ VOV → Saturation; ID = ½·µnCox(W/L)·VOV² = 390.0 µA

A1.3 Sizing from Current and Overdrive

W/L = 2ID/(µnCox·VOV²) = 2×0.8m / (320µ×0.04) = 125
For L = 0.36 µm → W = 125 × 0.36 = 45 µm
VGS = VTH + VOV = 0.45 + 0.20 = 0.65 V

A1.4 Channel-Length Modulation

ID = ID0(1+λVDS): VDS=0.5V → 0.5150 mA; 1.0V → 0.5300 mA; 1.5V → 0.5450 mA; 2.0V → 0.5600 mA
Percentage increase (0.5V→2.0V) = (0.560−0.515)/0.515 × 100 ≈ 8.74 %

A1.5 Body Effect

VTH = VTH0 + γ(√(2φF+VSB) − √2φF)
VSB=0: VTH=0.400 V, VOV(=1.0−VTH)=0.600 V
VSB=0.4: VTH=0.496 V, VOV=0.505 V
VSB=1.0: VTH=0.610 V, VOV=0.390 V

Module 2 — Large-Signal to Small-Signal Models

A2.1 gm, gds and ro
gm = 2ID/VOV = 2×0.60m/0.24 = 5.0 mS
gds = λID = 0.04×0.60m = 24 µS → ro = 1/gds = 41.7 kΩ
gm·ro = 5.0mS × 41.7kΩ ≈ 208.3 (intrinsic gain magnitude)

A2.2 Common-Source Gain with Finite Output Resistance

RD∥ro∥RL = 12k∥70k∥50k = 8.50 kΩ → Av = −5.5mS×8.50k = −46.76 V/V
Neglecting ro: RD∥RL = 12k∥50k = 9.68 kΩ → Av = −53.23 V/V
Percentage difference ≈ 13.8 % (neglecting ro overestimates gain)

A2.3 Source Degeneration

Without degeneration: Av = −gmRD = −70.0 V/V
With degeneration: Av = −gmRD/(1+gmRS) = −70/(1+7m×350) = −20.29 V/V

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Reduction factor = 1+gmRS = 3.45×

A2.4 Body Transconductance

gmb = gm·γ/(2√(2φF+VSB)) = 6m×0.50/(2×√1.00) = 1.5 mS
gmb/gm = 0.25
id = gm·vgs + gmb·vbs = 5m×10m + 1.5m×5m = 67.5 µA

A2.5 Bias-to-Gain Design

gm = |Av|/RD = 20/8k = 2.5 mS
ID = gm·VOV/2 = 2.5m×0.25/2 = 0.3125 mA
Vdrop across RD = ID·RD = 0.3125m×8k = 2.5 V
Quiescent VD = VDD − Vdrop = 1.8 − 2.5 = −0.7 V → NOT physically reasonable (negative drain voltage);
RD or ID must be reduced, or VDD increased, for saturation to hold.

Module 3 — MOS Capacitances and Miller Effect

A3.1 Intrinsic and Overlap Cgs
Cgs,int = (2/3)Cox·W·L = (2/3)×7.0×30×0.5 = 70.0 fF
Cgso = C'gso·W = 0.22×30 = 6.6 fF
Total Cgs = 70.0 + 6.6 = 76.6 fF

A3.2 Drain-Body Junction Capacitance

Cj(VR) = Cj0/(1+VR/φ0)^m: VR=0 → 180.0 fF; 0.5V → 139.4 fF; 1.0V → 117.8 fF; 2.0V → 94.0 fF
Percentage reduction (0→2.0V) ≈ 47.8 %

A3.3 Miller Multiplication

(a) CM,in = Cgd(1−Av) = 18×(1−(−16)) = 306 fF
(b) Total Cin = Cgs + CM,in = 120 + 306 = 426 fF
(c) CM,out = Cgd(1−1/Av) = 18×(1−1/(−16)) = 19.1 fF

A3.4 Gain Dependence of Input Capacitance

Cin = Cgs + Cgd(1−Av): Av=−5 → 270 fF; −10 → 370 fF; −20 → 570 fF; −40 → 970 fF
Ratio Cin(−40)/Cin(−5) = 970/270 ≈ 3.59

A3.5 Capacitance Budget of a Drain Node

CM,out = Cgd(1−1/Av) = 15×(1−1/(−12)) = 16.25 fF
Total drain-node capacitance = Cdb+Cwire+CL+CM,out = 55+40+120+16.25 = 231.25 fF
fp = 1/(2πReqCtot) = 1/(2π×9k×231.25f) ≈ 76.5 MHz

Module 4 — Parasitics and Interconnects

A4.1 Metal-Line Resistance
R = ρL/(Wt) = 2.7×10⁻⁸×1.2×10⁻³ / (1.8×10⁻⁶×0.45×10⁻⁶) = 40.0 Ω
Doubling width → R halves = 20.0 Ω

A4.2 Sheet-Resistance Method

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 MOS Devices & Analog Design — Numerical Question Paper

Number of squares = L/W = 48/2 = 24

R = R□ × squares = 55×24 = 1320 Ω
Two in parallel → Reff = 660 Ω

A4.3 Lumped Node Time Constant

τ = ReqCeq = 18k×260f = 4.68 ns → fp = 1/(2πτ) ≈ 34.0 MHz
t10–90% ≈ 2.2τ ≈ 10.30 ns
With +140 fF probe cap: Ceq = 400 fF → fp ≈ 22.1 MHz

A4.4 Distributed RC Interconnect

Rtot = R'ℓ = 0.12×2500 = 300 Ω; Ctot = C'ℓ = 0.20×2500 = 500 fF
td = 0.38×Rtot×Ctot = 0.38×300×500f ≈ 57.0 ps
At ℓ = 1.25 mm: Rtot=150Ω, Ctot=250 fF → td ≈ 14.25 ps = td(full)/4, confirming td ∝ ℓ²

A4.5 Parasitic Pole after Layout Extraction

Pre-layout: fp = 1/(2πRoutC) = 1/(2π×15k×90f) ≈ 117.9 MHz
Post-layout: Ctot = 90+65+45 = 200 fF → fp ≈ 53.1 MHz
Percentage reduction = (117.9−53.1)/117.9 × 100 = 55.0 %

Module 5 — Frequency Response

A5.1 Single-Pole Response
|A(f)| = |A0|/√(1+(f/fp)²): 0.08MHz → 59.70 (35.52 dB); 0.8MHz → 42.43 (32.55 dB, −3dB pt);
8MHz → 5.97 (15.52 dB); 80MHz → 0.60 (−4.44 dB)
Beyond fp, asymptotic roll-off is −20 dB/decade (single-pole slope)

A5.2 Two-Pole Response

20kHz → 99.50 (39.96 dB); 200kHz → 70.69 (36.99 dB, first −3dB pt);
2MHz → 9.65 (19.69 dB); 8MHz → 1.77 (4.95 dB, second pole); 80MHz → 0.025 (−32.08 dB)
Slope: ≈0 dB/decade below fp1, −20 dB/decade between fp1 and fp2, −40 dB/decade above fp2

A5.3 Input Pole Due to Miller Effect

CM,in = Cgd(1−Av) = 22×19 = 418 fF; Cin,total = 110+418 = 528 fF
fp,in = 1/(2πRsigCin) = 1/(2π×25k×528f) ≈ 12.06 MHz
With |Av|=9: CM,in=220 fF, Cin=330 fF → fp,in ≈ 19.29 MHz (bandwidth improves as gain drops)

A5.4 Transition Frequency

fT = gm/[2π(Cgs+Cgd)] = 9m/(2π×295f) ≈ 4.86 GHz
With gm=13.5mS and C×1.2 (=354f): fT ≈ 6.07 GHz — net improvement despite larger capacitance

A5.5 Competing Input and Output Poles

Input: CM,in=Cgd(1−Av)=16×15=240 fF, Cin=140+240=380 fF → fp,in=1/(2π×12k×380f)≈34.90 MHz
Output: CM,out=Cgd(1−1/Av)=16×(1+1/14)≈17.14 fF, Cout=180+17.14=197.14 fF →
fp,out=1/(2π×11k×197.14f)≈73.39 MHz
Input pole is dominant (lower frequency); overall upper cutoff ≈ fp,in ≈ 34.9 MHz (dominant-pole
approximation)

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Module 6 — Noise
A6.1 Resistor Thermal Noise
Sv = 4kTR = 4×1.38e-23×300×22k = 3.643×10⁻¹⁶ V²/Hz → density = 19.09 nV/√Hz
vn,rms = √(4kTRB): 10kHz → 1.91 µV; 100kHz → 6.04 µV; 2MHz → 26.99 µV

A6.2 MOS Channel Thermal Noise

Sid = 4kTγgm = 4×1.38e-23×300×(2/3)×5m = 5.52×10⁻²³ A²/Hz → in,d = 7.43 pA/√Hz
Sv,in = 4kTγ/gm = 2.208×10⁻¹⁸ V²/Hz → en = 1.486 nV/√Hz
vn,rms over 5 MHz = en√B ≈ 3.32 µV

A6.3 Effect of gm on Input-Referred Noise

en=√(4kTγ/gm): gm=1mS → 3.32 nV/√Hz; 2mS → 2.35 nV/√Hz; 5mS → 1.49 nV/√Hz; 10mS → 1.05 nV/√Hz
Ratios confirm en ∝ 1/√gm; to halve en, gm must increase by a factor of 4×

A6.4 Flicker Noise and Corner Frequency

en,1/f(f) = en,100×√(100/f): at 1 kHz → 3.79 nV/√Hz; at 10 kHz → 1.20 nV/√Hz
Corner frequency: fc = 100×(en,100/en,white)² = 100×(12/3)² = 1600 Hz

A6.5 Input-Referred Noise Budget

en,tot = √(2.8²+5.0²+1.5²) ≈ 5.92 nV/√Hz
vn,rms (1 MHz BW) = en,tot×√B ≈ 5.92 µV
SNR = 1mV/5.92µV ≈ 168.8 → SNR(dB) = 20log10(168.8) ≈ 44.5 dB