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COMPUTER SYSTEM
ARCHITECTURE UNIT - 2
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 COMPUTER SYSTEM ARCHITECTURE UNIT - 2
Digital Logic Circuits
The digital logic circuits are basic building blocks of the digital systems (digital computers).
These digital logic circuits can be classified into two categories such as combinational logic
circuits and sequential logic circuits. Before studying about the difference between
combinational and sequential logic circuits, primarily, we must know what is combinational
logic circuit and what are sequential logic circuits.
Digital Computers
A Digital computer can be considered as a digital system that performs various computational
tasks.
The first electronic digital computer was developed in the late 1940s and was used primarily
for numerical computations.
By convention, the digital computers use the binary number system, which has two digits: 0
and 1. A binary digit is called a bit.
A computer system is subdivided into two functional entities: Hardware and Software.
The hardware consists of all the electronic components and electromechanical devices that
comprise the physical entity of the device.
The software of the computer consists of the instructions and data that the computer
manipulates to perform various data-processing tasks.

o The Central Processing Unit (CPU) contains an arithmetic and logic unit for manipulating
data, a number of registers for storing data, and a control circuit for fetching and
executing instructions.
o The memory unit of a digital computer contains storage for instructions and data.
o The Random Access Memory (RAM) for real-time processing of the data.
o The Input-Output devices for generating inputs from the user and displaying the final
results to the user.

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o The Input-Output devices connected to the computer include the keyboard, mouse,
terminals, magnetic disk drives, and other communication devices.
Logic Gates
o The logic gates are the main structural part of a digital system.
o Logic Gates are a block of hardware that produces signals of binary 1 or 0 when input
logic requirements are satisfied.
o Each gate has a distinct graphic symbol, and its operation can be described by means of
algebraic expressions.
o The seven basic logic gates includes: AND, OR, XOR, NOT, NAND, NOR, and XNOR.
o The relationship between the input-output binary variables for each gate can be
represented in tabular form by a truth table.
o Each gate has one or two binary input variables designated by A and B and one binary
output variable designated by x.
AND GATE:
The AND gate is an electronic circuit which gives a high output only if all its inputs are high.
The AND operation is represented by a dot (.) sign.

OR GATE:
The OR gate is an electronic circuit which gives a high output if one or more of its inputs are
high. The operation performed by an OR gate is represented by a plus (+) sign.

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NOT GATE:
The NOT gate is an electronic circuit which produces an inverted version of the input at its
output. It is also known as an Inverter.
NAND GATE:
The NOT-AND (NAND) gate which is equal to an AND gate followed by a NOT gate. The NAND
gate gives a high output if any of the inputs are low. The NAND gate is represented by a AND
gate with a small circle on the output. The small circle represents inversion.

NOR GATE:
The NOT-OR (NOR) gate which is equal to an OR gate followed by a NOT gate. The NOR gate
gives a low output if any of the inputs are high. The NOR gate is represented by an OR gate
with a small circle on the output. The small circle represents inversion.

Exclusive-OR/ XOR GATE:

The 'Exclusive-OR' gate is a circuit which will give a high output if one of its inputs is high but
not both of them. The XOR operation is represented by an encircled plus sign.

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EXCLUSIVE-NOR/Equivalence GATE:
The 'Exclusive-NOR' gate is a circuit that does the inverse operation to the XOR gate. It will give
a low output if one of its inputs is high but not both of them. The small circle represents
inversion.

Boolean Algebra
Boolean algebra can be considered as an algebra that deals with binary variables and logic
operations. Boolean algebraic variables are designated by letters such as A, B, x, and y. The
basic operations performed are AND, OR, and complement.
The Boolean algebraic functions are mostly expressed with binary variables, logic operation
symbols, parentheses, and equal sign. For a given value of variables, the Boolean function can
be either 1 or 0. For instance, consider the Boolean function:
F = x + y'z
The logic diagram for the Boolean function F = x + y'z can be represented as:

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o The Boolean function F = x + y'z is transformed from an algebraic expression into a logic
diagram composed of AND, OR, and inverter gates.
o Inverter at input 'y' generates its complement y'.
o There is an AND gate for the term y'z, and an OR gate is used to combine the two terms
(x and y'z).
o The variables of the function are taken to be the inputs of the circuit, and the variable
symbol of the function is taken as the output of the circuit.
Note: A truth table can represent the relationship between a function and its binary variables.
To represent a function in a truth table, we need a list of the 2^n combinations of n binary
variables.
The truth table for the Boolean function F = x + y'z can be represented as:

Laws of Boolean algebra

The basic Laws of Boolean Algebra can be stated as follows:

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o Commutative Law states that the interchanging of the order of operands in a Boolean
equation does not change its result. For example:
1. OR operator → A + B = B + A
2. AND operator → A * B = B * A
o Associative Law of multiplication states that the AND operation are done on two or
more than two variables. For example:
A * (B * C) = (A * B) * C
o Distributive Law states that the multiplication of two variables and adding the result
with a variable will result in the same value as multiplication of addition of the variable
with individual variables. For example:
A + BC = (A + B) (A + C).
o Annulment law:
A.0 = 0
A+1=1
o Identity law:
A.1 = A
A+0=A
o Idempotent law:
A+A=A
A.A = A
o Complement law:
A + A' = 1
A.A'= 0
o Double negation law:
((A)')' = A
o Absorption law:
A.(A+B) = A
A + AB = A
De Morgan's Law is also known as De Morgan's theorem, works depending on the concept of
Duality. Duality states that interchanging the operators and variables in a function, such as
replacing 0 with 1 and 1 with 0, AND operator with OR operator and OR operator with AND
operator.
De Morgan stated 2 theorems, which will help us in solving the algebraic problems in digital
electronics. The De Morgan's statements are:
1. "The negation of a conjunction is the disjunction of the negations", which means that
the complement of the product of 2 variables is equal to the sum of the compliments of
individual variables. For example, (A.B)' = A' + B'.
2. "The negation of disjunction is the conjunction of the negations", which means that
compliment of the sum of two variables is equal to the product of the complement of
each variable. For example, (A + B)' = A'B'.
Map Simplification

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The Map method involves a simple, straightforward procedure for simplifying Boolean
expressions.
Map simplification may be regarded as a pictorial arrangement of the truth table which allows
an easy interpretation for choosing the minimum number of terms needed to express the
function algebraically. The map method is also known as Karnaugh map or K-map.
Each combination of the variables in a truth table is called a mid-term.
Note: When expressed in a truth table a function of n variables will have 2^n min-terms,
equivalent to the 2^n binary numbers obtained from n bits.
There are four min-terms in a two variable map. Therefore, the map consists of four squares,
one for each min-term. The 0's and 1's marked for each row, and each column designates the
values of variable x and y, respectively.
Two-variable map:

Representation of functions in the two-variable map:

Three variable map

There are eight min-terms in a three-variable map. Therefore, the map consists of eight
squares.
Three variable map:

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o The map was drawn in part (b) in the above image is marked with numbers in each row
and each column to show the relationship between the squares and the three variables.
o Any two adjacent squares in the map differ by only one variable, which is primed in one
square and unprimed in the other. For example, m5 and m7 lie in the two adjacent
squares. Variable y is primed in m5 and unprimed in m7, whereas the other two
variables are the same in both the squares.
o From the postulates of Boolean algebra, it follows that the sum of two min-terms in
adjacent squares can be simplified to a single AND term consisting of only two literals.
For example, consider the sum of two adjacent squares say m5 and m7:
m5+m7 = xy'z+xyz= xz(y'+y)= xz.
Logic circuits are classified into two types:
 Sequential logic circuits
 Combinational logic circuits.
Combinational Logic Circuits
The combinational logic circuits or time-independent logic circuits in digital circuit theory can
be defined as a type of digital logic circuit implemented using Boolean circuits, where the
output of logic circuit is a pure function of the present inputs only. The combinational logic
circuit operation is instantaneous and these circuits do not have the memory or feedback
loops.
This combinational logic is in contrast compared to the sequential logic circuit in which the
output depends on both present inputs and also on the previous inputs. Thus, we can say that
combinational logic does not have memory, whereas sequential logic stores previous input in
its memory. Hence, if the input of combinational logic circuit changes, then the output also
changes.
Combinational Logic Circuit Design

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Combinational Logic Circuit

These combinational logic circuits are designed to produce specific outputs from certain
inputs. The combinational logic design can be done using two methods such as a sum of
products and a product of sums. Combinational logic circuits are generally designed by
connecting together or combining the basic logic gates such as NAND, NOR, and NOT. Hence,
these logic gates are termed as building blocks. These logic circuits can be a very simple circuit
or a very complex circuit or huge combinational circuit can be designed using only universal
logic gates such as NAND and NOR gates.
The simple time independent logic circuits that are implemented using Boolean circuits whose
output logic value depends only on the input logic values can be called as combinational logic
circuits.

Combinational Logic Circuit

The figure shows all the three major components of the combinational logic circuit such as
logic diagram, truth table, and Boolean expression.
Functions of Combinational Logic Circuit
The function of combinational logic circuits can be specified in three main ways such as:
 Truth Table

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 Boolean Algebra
 Logic Diagram
Truth Table

Combinational Logic Function Truth Table

The logic gate function can be defined using its truth table which consists outputs for of all
possible combinations of inputs of the logic gate. An example combinational logic function
truth table is shown in the above figure.
Boolean Algebra

Combinational Logic Function Boolean Expression

The output of combinational logic function can be expressed in the form expression
using Boolean algebra and an example, Boolean expression for the above truth table is shown
in the above figure.
Logic Diagram

Combinational Logic Circuit using Logic Gates

The graphical representation of combinational logic functions using logic gates is called as logic
diagram. The logic diagram for above discussed logic function truth table and Boolean
expression can be realized as shown in the above figure.
The combinational logic circuits can be also be called as decision making circuits, as these are
designed using individual logic gates. The combinational logic is the process of combining logic
gates to process the given two or more inputs such that to generate at least one output signal
based on the logic function of each logic gate.
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Classification of Combinational Logic

Classificaiton of Combinational Logic

The combinational logic circuits can be classified into various types based on the purpose of
usage, such as arithmetic & logical functions, data transmission, and code converters. To solve
the arithmetic and logical functions we generally use adders, subtractors,
and comparators which are generally realized by combining various logic gates called as
combinational logic circuits. Similarly, for data transmission, we use multiplexers,
demultiplexers, encoders, and decoders which are also realized using combinational logic. The
code converters such as binary, BCD, and 7-segment are designed using various logic circuits.
In fact, combinational logic is most frequently used in multiplexer and demultiplexer type
circuits. If multiple inputs or outputs are connected to the common signal line, then the logic
gates are used for decoding an address in order to select single data input or output switch.
Sequential Logic Circuits
The combinational circuit does not use any memory. Hence the previous state of input does
not have any effect on the present state of the circuit. But sequential circuit has memory so
output can vary based on input. This type of circuits uses previous input, output, clock and a
memory element.
The simple logic circuits whose output logic value depends on the input logic values and also
on the stored information is called as sequential logic circuits.
Combinational circuit produces an output based on input variable only, but Sequential
circuit produces an output based on current input and previous input variables. That means
sequential circuits include memory elements which are capable of storing binary information.
That binary information defines the state of the sequential circuit at that time. A latch capable
of storing one bit of information.

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As shown in figure there are two types of input to the combinational logic :
1. External inputs which not controlled by the circuit.
2. Internal inputs which are a function of a previous output states.
Secondary inputs are state variables produced by the storage elements, where as secondary
outputs are excitations for the storage elements.
Types of Sequential Circuits – There are two types of sequential circuit :
1. Asynchronous sequential circuit – These circuit do not use a clock signal but uses the
pulses of the inputs. These circuits are faster than synchronous sequential circuits
because there is clock pulse and change their state immediately when there is a change
in the input signal. We use asynchronous sequential circuits when speed of operation is
important and independent of internal clock pulse.

But these circuits are more difficult to design and their output is uncertain.
2. Synchronous sequential circuit – These circuit uses clock signal and level inputs (or
pulsed) (with restrictions on pulse width and circuit propagation). The output pulse is
the same duration as the clock pulse for the clocked sequential circuits. Since they wait
for the next clock pulse to arrive to perform the next operation, so these circuits are
bit slower compared to asynchronous. Level output changes state at the start of an
input pulse and remains in that until the next input or clock pulse.

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We use synchronous sequential circuit in synchronous counters, flip flops, and in the design of
MOORE-MEALY state management machines.

Sequential Logic Circuit

The figure represents the block diagram of the sequential logic circuit.
Difference between Synchronous and Asynchronous Sequential Circuits
As the name suggests both Synchronous and Asynchronous Sequential Circuits are the type of
sequential circuits which uses feedback for the next output generation however on the basis
of the type of this feedback both circuits can be get differentiated.
Following are the important differences between Synchronous and Asynchronous Sequential
Circuits −
Sr. Key Synchronous Sequential Asynchronous Sequential Circuits
No. Circuits

1 Definition Synchronous sequential On other hand Asynchronous sequential

circuits are digital sequential circuits are digital sequential circuits in
circuits in which the which the feedback to the input for next
feedback to the input for output generation is not governed by clock
next output generation is signals.
governed by clock signals.

2 Memory In Synchronous sequential On other hand unclocked flip flop or time

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Sr. Key Synchronous Sequential Asynchronous Sequential Circuits

No. Circuits
Unit circuits, the memory unit delay is used as memory element in case
which is being get used for of Asynchronous sequential circuits.
governance is clocked flip
flop.

3 State The states of Synchronous On other hand there are chances for the
sequential circuits are always Asynchronous circuits to enter into a
predictable and thus reliable. wrong state because of the time
difference between the arrivals of inputs.
This is called as race condition.

4 Complexity It is easy to design However on other hand the presence of

Synchronous sequential feedback among logic gates causes
circuits instability issues making the design of
Asynchronous sequential circuits difficult.

5 Performance Due to the propagation delay Since there is no clock signal delay, these
of clock signal in reaching all are fast compared to the Synchronous
elements of the circuit the Sequential Circuits
Synchronous sequential
circuits are slower in its
operation speed

6 Example Synchronous circuits are On other hand Asynchronous circuits are

used in counters, shift used in low power and high speed
registers, memory units. operations such as simple
microprocessors, digital signal processing
units and in communication systems for
email applications, internet access and
networking.
Difference Between Combinational Logic Circuits and Sequential Logic Circuits
The difference between combinational logic circuits and sequential logic circuits can be easily
understood by knowing about each circuit in detail.
Combinational Logic Ciruits
 The digital logic circuits whose outputs can be determined using the logic function of
current state input are combinational logic circuits, hence, these are also called as
time independent logic circuits.
 Thus, these combinational digital logic circuits don’t have the capability to store a
state inside them.
 Hence, the combinational logic circuits do not contain any memory elements.

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 The arithmetic operations performed on the date stored data in the computers are
done using combinational logic circuits.
 The combinational digital logic circuits are fundamentally implemented using
different types of devices such as multiplexers, demultiplexers, encoders, decoders,
half adder, and full adders.
 The components of arithmetic and logic unit of the computers are generally
comprised of combinational digital logic circuits.
 The independent working states of the combinational logic circuits are represented
with Boolean algebra and after simplification by using NOR, NOT, and NAND gates
the circuit can be implemented.
 The combinational digital circuits don’t require any feedbacks.
 The combinational logic circuits are independent of the clock.
 As there are no clocks used in these digital logic circuits, they do not need any
triggering.
 The combinational logic circuit’s behavior can be defined by using the set of output
functions.
 In general, sum of products or products of sums method is used for the construction
of combinational logic.
Sequential Logic Circuits
 The digital logic circuits whose outputs can be determined using the logic function of
current state inputs and past state inputs are called as sequential logic circuits.
 These sequential digital logic circuits are capable to retain the earlier state of the
system based on the current inputs and earlier state.
 Hence, unlike the combinational logic circuits, these sequential digital logic circuits
are capable of storing the data in a digital circuit.
 The sequential logic circuits contain memory elements.
 The latch is considered as the simplest element used to retain the earlier memory or
state in the sequential digital logic.
 Latches can also be called as flip-flops, but, if we consider the true structural form,
then it can be considered as a combinational circuit with one or more than one
outputs fed back as inputs.
 These sequential digital logic circuits are used in maximum types of memory
elements and also in finite state machines, which are replica watches for sale digital
circuit models with finite possible states.
 The maximum number of sequential logic circuits uses a clock for triggering the flip
flops operation.
 If the flip flop in the digital logic circuit is triggered, then the circuit is called as
synchronous sequential circuit and the other circuits (which are simultaneously not
triggered) are called as asynchronous sequential circuits.
 The sequential digital logic circuits utilize the feedbacks from outputs to inputs.
 The sequential logic circuit’s behavior can be defined by using the set of output
functions and set of next state or memory functions.

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 In practical digital logic circuits, combinational digital logic circuits and sequential
digital logic circuits are used.
Different Types of Flip Flop Conversion
In electronics, flip flop is an electronic circuit and is also called as a latch. Flip flops consist of
two stable states which are used to store the data. These are basic building blocks of a digital
electronic system which are used in various systems like communications, computers, etc. A
basic flip flop can be used to construct a cross coupled inverting elements like invert gates,
FETs, BJTs, inverters, vacuum tubes. Conversion of one type of flip flop to another can be done
by using a combinational logic circuit. For instance, If a JK Flip Flop is necessary, the i/ps are
given to the combinational circuit & the o/p of the combinational circuit is given to the i/ps of
the actual flip-flop. Therefore, the o/p of the actual flip-flop is the o/p of the required flip-flop.

Flip Flop Conversion

Flip Flop Conversion
The main purpose of the flip flop conversion is to convert a flip flop into a desired type-B flip
flop using some conversion logic. The flip flop conversions are classified into different types
that are
 SR-FF to JK-FF Conversion
 JK-FF to SR-FF Conversion
 SR-FF to D-FF Conversion
 D-FF to SR-FF Conversion
 JK-FF to T-FF Conversion
 JK-FF to D-FF Conversion
 D-FF to JK-FF Conversion
SR-Flip Flop to JK-Flip Flop Conversion
In JK-flipflop, j and k are given as external i/ps to S and R in SR-flip flop. Here, both S & R are
o/ps of the combinational circuit. The truth tables of flip flop conversions are shown below.
The current state is denoted with Qp & Qp+1 is the next state to be found when the J &K i/ps
are applied.

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SR-FF to JK-FF Conversion

There are eight possible combinations for two i/ps J and K. For every combination of J, K & Qp,
the equivalent Qp+1 states are found. Qp+1 simply recommends the future values to be found
by the JK-flip flop after the importance of Qp. Then the table is finished by writing the values
of S & R compulsory to get each Qp+1 from the equivalent Qp. That is, the S and R values are
compulsory to change the state of the flip flop from Qp to Qp+1 are written
JK-Flip Flop to SR-Flip Flop Conversion
The conversion of the JK-FF to SR-FF is opposite to the SR-FF to JK-FF. Here S & R will be the
external i/ps to J & K, that is shown in the below logic diagram, J & K will be the o/ps of the
combinational circuit. So, the J and K values have to be acquired in terms of S, R & Qp. The
logic diagram is shown below. The conversion table for flip flop to be written in terms of S, R,
Qp, Qp+1, J & K. There are eight possible combinations for two i/ps S and R.

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JK-FF to SR-FF Conversion

For every combination, the equivalent Qp+1 o/p’s are found. The o/p’s for the combinations of
S=R=1 are not acceptable for an SR-FF. Therefore the o/p’s are considered as invalid and the J
& K values are taken as “don’t care”.
SR-Flip Flop to D-Flip Flop Conversion
As shown in the below figure, actual inputs of the flip flop are S & R where D is the external
i/p. The four combinations of the S & R in terms of D and Qp, conversion table, logic diagram
and the Karnaugh map are given below.

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SR-FF to D-FF Conversion

D-Flip Flop to SR-Flip Flop Conversion
In this type of conversion, D is the actual i/p of the flip flop where S & R are the external
i/[Link] are Eight possible combinations are obtained from the external i/ps S, R & Qp.
Nevertheless, since the combination of S=R=1 is unacceptable, the values of D and Qp+1 are
taken as “don’t care”. The logic diagram of D-FF to SR-FF is showing the conversion from D-FF
to SR-FF, and the Karnaugh map for D in terms of S, R & Qp are given below.

D-FF to SR-FF Conversion

JK-Flip Flop to T-Flip Flop Conversion
In this type of conversion, J & k are the actual i/ps of the flip flop where K is considered as the
external i/p. Four combinations are created by T, Qp, J & K that are expressed in terms of T &
Qp. The Karnaugh map, the logic diagram and conversion table, are given below.

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JK-FF to T-FF Conversion

JK-Flip Flop to D-Flip Flop Conversion
In this type of flip flop conversion, J&K are the actual inputs where D is the external input of
the flip flop. The four combinations of the flip flop will be done by using D & Qp, and in terms
of these two J&K are expressed. The conversion table with four combinations, JK-FF to D-FF
conversion logic diagram and Karnaugh map for J & K in terms of D & are shown below.

JK-FF to D-FF Conversion

D-Flip Flop to JK-Flip Flop Conversion
In this type of flip flop conversion, J & K are the external i/ps of the flip flop where D is the
actual input. The eight combinations can make by using J, K and Qp that is shown in the
conversion table below. D is stated in terms of J, K & Qp. The Karnaugh map D in terms of J, K
& Qp, conversion table and the logic diagram of the D-FF to JK-FF is shown below.

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D-FF to JK-FF Conversion

Thus, this is all about different types of flip flop conversions, that includes SR-FF to JK-FF , JK-FF
to SR-FF , SR-FF to D-FF , D-FF to SR-FF , JK-FF to T-FF , JK-FF to D-FF and D-FF to JK-FF . We
hope that you have got a better understanding of this concept. Furthermore, any doubts
regarding the applications of flip-flops or electronics projects, please give your feedback by
commenting in the comment section [Link] is a question for you, what are the
applications of flip flops?
Integrated Circuit
A microprocessor is digital is a digital circuit which is built using a combination logic functions.
The microprocessor package contains an integrated circuit.
An integrated circuit is electronic circuit or device that has electronic components on a small
semiconductor chip. It has functionality of logic AND or amplifying of a signal. These are mainly
two types of circuits: Digital or Analog. Analog ICs handle continuous signals such as audio
signals and Digital ICs handle discrete signals such as binary values.
An integrated circuit, or IC, is small chip that can function as an amplifier, oscillator,
timer, microprocessor, or even computer memory. An IC is a small wafer, usually made of
silicon, that can hold anywhere from hundreds to millions of transistors, resistors, and
capacitors. These extremely small electronics can perform calculations and store data using
either digital or analog technology.
Digital ICs use logic gates, which work only with values of ones and zeros. A low signal sent to
to a component on a digital IC will result in a value of 0, while a high signal creates a value of 1.
Digital ICs are the kind you will usually find in computers, networking equipment, and most
consumer electronics.
Analog, or linear ICs work with continuous values. This means a component on a linear IC can
take a value of any kind and output another value. The term "linear" is used since the output
value is a linear function of the input. For example, a component on a linear IC may multiple
an incoming value by a factor of 2.5 and output the result. Linear ICs are typically used in audio
and radio frequency amplification.
Types of Integrated Circuits

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There are different types of integrated circuits based various criteria. Based on intended
application, the Integrated Circuit (IC) can be classified as following:
 Digital Integrated Circuits handle discrete signals such as binary values (0 and 1). These
circuits use digital logic gates, multiplexers, flip flops [Link] circuits are easier to
design and economical.
 Analog Integrated Circuits handle contiguous signals. These are two types: linear
integrated circuits (Linear ICs) and Radio frequency integrated circuits (RF ICs).
 Mixed Integrated Circuits are obtained by the combination of analog and digital
integrated circuits. Therefore it have digital to analog (A/D) converter, digital to analog
(D/A) converter, and clock/timing integrated circuits.
General types of integrated circuits are as following: Comparators, Switching IC, Audio
amplifiers, Operational amplifiers, Timers ICs.
Digital Integrated Circuit
Functions of digital integrated circuits to handle discrete signals such as binary values in which
“true/false” logical operations are used. Basic Boolean functions such as AND, OR, and NOT
are essential in building functionality for modern digital systems. These Boolean functions are
implemented using transistors. For example, internal transistor structure of a NAND gate is
given in following figure.

There might ten billion or more transistors in modern digital circuit. So, we need Integrated
Circuits (ICs) that combine a small or large number of these transistors to achieve particular
functionality. These circuits provide benefiting students, very low cost and higher level of
reliability. Examples of integrated circuits are MOS, CMOS, TTL etc. CMOS ICs are fault
tolerant, reduce risk of chip failure, use of anti-static foam for storage and transport of ICs. TTL
technology requires regulated power supply of 5 volts.
Families of Integrated Circuits
A logic family is a group of electronic logic gates. A family has its own discrete logic level,
power supply, individual components, characteristic, advantages and disadvantages. Within
each family, there is a range of voltage which may be low level or high level.
These families are listed as following below:
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Diode Logic (DL)
Registers and diodes are used to implement logic. The purpose of diode is to perform OR and
AND operation, and logic switch. It is essential that diode is forward biased so that it can
conduct. Disadvantages: diodes can not perform NOT operation, diode cannot work for
multiple states, only one stage at a time, tend to degrade signals quickly.
Resistor-Transistor Logic (RTL)
Registers and transistors are used to implement logic. Transistors are used to combine signals
which are inverted and amplified inputs. These are economical and easy to design but slower
in speed. These require great amount of current from supply. RTL gates can be used as
interface between linear circuits and digital.
Diode Transistor Logic (DTL)
Registers and diodes are used to implement logic. It has advantages over DL and RTL. Diode
can perform AND and OR operation along with a transistor and output signal can be amplified.
It has logic inversion which is signal can be restored to full logic level, if we add a transistor at
output of logic gates. OR operation can be performed using diodes instead of resistors which
removes interaction between input signals. Since input resistor to transistor, switching speed
of transistor is limited. DTL was used in tube computers.
Transistor - Transistor Logic (TTL)
Transistors are used to implement logic and Bipolar transistors to contract integrated circuits.
There are standard TTL, high speed TTL, low power TTL, and schottky TTL. It is popular logic
family.
Emitter Coupled Logic (ECL)
ECL is a non-structured logic. Advantages of this logic are speed, and very low propagation
delay.
Complementary Metal Oxide Semiconductor Logic (CMOS)
It is known for high fan-out, low power consumption and most reliable logic family.
Decoders
Decoder is a combinational circuit that has ‘n’ input lines and maximum of 2 n output lines. One
of these outputs will be active High based on the combination of inputs present, when the
decoder is enabled. That means decoder detects a particular code. The outputs of the decoder
are nothing but the min terms of ‘n’ input variables lines, when it is enabled.
2 to 4 Decoder
Let 2 to 4 Decoder has two inputs A1 & A0 and four outputs Y3, Y2, Y1 & Y0. The block
diagram of 2 to 4 decoder is shown in the following figure.

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One of these four outputs will be ‘1’ for each combination of inputs when enable, E is ‘1’.
The Truth table of 2 to 4 decoder is shown below.
Enable Inputs Outputs

E A1 A0 Y3 Y2 Y1 Y0

0 x x 0 0 0 0

1 0 0 0 0 0 1

1 0 1 0 0 1 0

1 1 0 0 1 0 0

1 1 1 1 0 0 0
From Truth table, we can write the Boolean functions for each output as
Y3=E.A1.A0
Y2=E.A1.A0′
Y1=E.A1′.A0
Y0=E.A1′.A0′
Each output is having one product term. So, there are four product terms in total. We can
implement these four product terms by using four AND gates having three inputs each & two
inverters. The circuit diagram of 2 to 4 decoder is shown in the following figure.

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Therefore, the outputs of 2 to 4 decoder are nothing but the min terms of two input variables
A1 & A0, when enable, E is equal to one. If enable, E is zero, then all the outputs of decoder will
be equal to zero.
Similarly, 3 to 8 decoder produces eight min terms of three input variables A2, A1 & A0 and 4 to
16 decoder produces sixteen min terms of four input variables A 3, A2, A1 & A0.
Implementation of Higher-order Decoders
Now, let us implement the following two higher-order decoders using lower-order decoders.
 3 to 8 decoder
 4 to 16 decoder
3 to 8 Decoder
In this section, let us implement 3 to 8 decoder using 2 to 4 decoders. We know that 2 to 4
Decoder has two inputs, A1 & A0 and four outputs, Y3 to Y0. Whereas, 3 to 8 Decoder has three
inputs A2, A1 & A0 and eight outputs, Y7 to Y0.
We can find the number of lower order decoders required for implementing higher order
decoder using the following formula.
Required number of lower order decoders =m2/m1 Required number of lower order decoders
= m2/m1
Where,
m1/m1 is the number of outputs of lower order decoder.
m2/m2 is the number of outputs of higher order decoder.
Here, m1 = 4 and m2 = 8. Substitute, these two values in the above formula.
Required number of 2 to 4 decoders = 8/4 =2 Required number of 2 to 4 decoders=8/4=2
Therefore, we require two 2 to 4 decoders for implementing one 3 to 8 decoder. The block
diagram of 3 to 8 decoder using 2 to 4 decoders is shown in the following figure.

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The parallel inputs A1 & A0 are applied to each 2 to 4 decoder. The complement of input A2 is
connected to Enable, E of lower 2 to 4 decoder in order to get the outputs, Y 3 to Y0. These are
the lower four min terms. The input, A2 is directly connected to Enable, E of upper 2 to 4
decoder in order to get the outputs, Y7 to Y4. These are the higher four min terms.
4 to 16 Decoder
In this section, let us implement 4 to 16 decoder using 3 to 8 decoders. We know that 3 to 8
Decoder has three inputs A2, A1 & A0 and eight outputs, Y7 to Y0. Whereas, 4 to 16 Decoder has
four inputs A3, A2, A1 & A0 and sixteen outputs, Y15 to Y0
We know the following formula for finding the number of lower order decoders required.
Required number of lower order decoders = m2/m1 Required number of lower order decoders
= m2/m1
Substitute, m1 = 8 and m2 = 16 in the above formula.
Required number of 3 to 8 decoders = 16/8 = 2 Required number of 3 to 8 decoders = 16/8 =2
Therefore, we require two 3 to 8 decoders for implementing one 4 to 16 decoder. The block
diagram of 4 to 16 decoder using 3 to 8 decoders is shown in the following figure.

The parallel inputs A2, A1 & A0 are applied to each 3 to 8 decoder. The complement of input,
A3 is connected to Enable, E of lower 3 to 8 decoder in order to get the outputs, Y 7 to Y0. These
are the lower eight min terms. The input, A3 is directly connected to Enable, E of upper 3 to 8
decoder in order to get the outputs, Y15 to Y8. These are the higher eight min terms.
Multiplexers

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Multiplexer is a combinational circuit that has maximum of 2 n data inputs, ‘n’ selection lines
and single output line. One of these data inputs will be connected to the output based on the
values of selection lines.
Since there are ‘n’ selection lines, there will be 2n possible combinations of zeros and ones.
So, each combination will select only one data input. Multiplexer is also called as Mux.
4x1 Multiplexer
4x1 Multiplexer has four data inputs I 3, I2, I1 & I0, two selection lines s1 & s0 and one output Y.
The block diagram of 4x1 Multiplexer is shown in the following figure.

One of these 4 inputs will be connected to the output based on the combination of inputs
present at these two selection lines. Truth table of 4x1 Multiplexer is shown below.

Selection Lines Output

S1 S0 Y

0 0 I0

0 1 I1

1 0 I2

1 1 I3

From Truth table, we can directly write the Boolean function for output, Y as
Y=S1′S0′I0+S1′S0I1+S1S0′I2+S1S0I3
We can implement this Boolean function using Inverters, AND gates & OR gate. The circuit
diagram of 4x1 multiplexer is shown in the following figure.

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We can easily understand the operation of the above circuit. Similarly, you can implement
8x1 Multiplexer and 16x1 multiplexer by following the same procedure.
Implementation of Higher-order Multiplexers.
Now, implement the following two higher-order Multiplexers using lower-order Multiplexers.
 8x1 Multiplexer
 16x1 Multiplexer
8x1 Multiplexer
In this section, implement 8x1 Multiplexer using 4x1 Multiplexers and 2x1 Multiplexer. We
know that 4x1 Multiplexer has 4 data inputs, 2 selection lines and one output. Whereas, 8x1
Multiplexer has 8 data inputs, 3 selection lines and one output.
So, we require two 4x1 Multiplexers in first stage in order to get the 8 data inputs. Since,
each 4x1 Multiplexer produces one output, we require a 2x1 Multiplexer in second stage by
considering the outputs of first stage as inputs and to produce the final output.
Let the 8x1 Multiplexer has eight data inputs I 7 to I0, three selection lines s2, s1 & s0 and one
output Y. The Truth table of 8x1 Multiplexer is shown below.

Selection Inputs Output

S2 S1 S0 Y

0 0 0 I0

0 0 1 I1

0 1 0 I2

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0 1 1 I3

1 0 0 I4

1 0 1 I5

1 1 0 I6

1 1 1 I7

We can implement 8x1 Multiplexer using lower order Multiplexers easily by considering the
above Truth table. The block diagram of 8x1 Multiplexer is shown in the following figure.

The same selection lines, s1 & s0 are applied to both 4x1 Multiplexers. The data inputs of
upper 4x1 Multiplexer are I7 to I4 and the data inputs of lower 4x1 Multiplexer are I 3 to I0.
Therefore, each 4x1 Multiplexer produces an output based on the values of selection lines,
s1 & s0.
The outputs of first stage 4x1 Multiplexers are applied as inputs of 2x1 Multiplexer that is
present in second stage. The other selection line, s2 is applied to 2x1 Multiplexer.
 If s2 is zero, then the output of 2x1 Multiplexer will be one of the 4 inputs I 3 to I0 based
on the values of selection lines s1 & s0.
 If s2 is one, then the output of 2x1 Multiplexer will be one of the 4 inputs I 7 to I4 based
on the values of selection lines s1 & s0.

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Therefore, the overall combination of two 4x1 Multiplexers and one 2x1 Multiplexer performs
as one 8x1 Multiplexer.
16x1 Multiplexer
In this section, implement 16x1 Multiplexer using 8x1 Multiplexers and 2x1 Multiplexer. We
know that 8x1 Multiplexer has 8 data inputs, 3 selection lines and one output. Whereas, 16x1
Multiplexer has 16 data inputs, 4 selection lines and one output.
So, we require two 8x1 Multiplexers in first stage in order to get the 16 data inputs. Since,
each 8x1 Multiplexer produces one output, we require a 2x1 Multiplexer in second stage by
considering the outputs of first stage as inputs and to produce the final output.
Let the 16x1 Multiplexer has sixteen data inputs I 15 to I0, four selection lines s3 to s0 and one
output Y. The Truth table of 16x1 Multiplexer is shown below.

Selection Inputs Output

S3 S2 S1 S0 Y

0 0 0 0 I0

0 0 0 1 I1

0 0 1 0 I2

0 0 1 1 I3

0 1 0 0 I4

0 1 0 1 I5

0 1 1 0 I6

0 1 1 1 I7

1 0 0 0 I8

1 0 0 1 I9

1 0 1 0 I10

1 0 1 1 I11

1 1 0 0 I12

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1 1 0 1 I13

1 1 1 0 I14

1 1 1 1 I15

We can implement 16x1 Multiplexer using lower order Multiplexers easily by considering the
above Truth table. The block diagram of 16x1 Multiplexer is shown in the following figure.

The same selection lines, s2, s1 & s0 are applied to both 8x1 Multiplexers. The data inputs of
upper 8x1 Multiplexer are I15 to I8 and the data inputs of lower 8x1 Multiplexer are I 7 to I0.
Therefore, each 8x1 Multiplexer produces an output based on the values of selection lines, s 2,
s1 & s0.
The outputs of first stage 8x1 Multiplexers are applied as inputs of 2x1 Multiplexer that is
present in second stage. The other selection line, s3 is applied to 2x1 Multiplexer.
 If s3 is zero, then the output of 2x1 Multiplexer will be one of the 8 inputs Is 7 to I0 based
on the values of selection lines s2, s1 & s0.
 If s3 is one, then the output of 2x1 Multiplexer will be one of the 8 inputs I 15 to I8 based
on the values of selection lines s2, s1 & s0.
Therefore, the overall combination of two 8x1 Multiplexers and one 2x1 Multiplexer performs
as one 16x1 Multiplexer.
Digital Registers
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Flip-flop is a 1 bit memory cell which can be used for storing the digital data. To increase the
storage capacity in terms of number of bits, we have to use a group of flip-flop. Such a group
of flip-flop is known as a Register. The n-bit register will consist of n number of flip-flop and it
is capable of storing an n-bit word.
The binary data in a register can be moved within the register from one flip-flop to another.
The registers that allow such data transfers are called as shift registers. There are four mode
of operations of a shift register.
 Serial Input Serial Output
 Serial Input Parallel Output
 Parallel Input Serial Output
 Parallel Input Parallel Output
Serial Input Serial Output
Let all the flip-flop be initially in the reset condition i.e. Q3 = Q2 = Q1 = Q0 = 0. If an entry of a
four bit binary number 1 1 1 1 is made into the register, this number should be applied
to Din bit with the LSB bit applied first. The D input of FF-3 i.e. D3 is connected to serial data
input Din. Output of FF-3 i.e. Q3 is connected to the input of the next flip-flop i.e. D2 and so on.
Block Diagram

Operation
Before application of clock signal, let Q3 Q2 Q1 Q0 = 0000 and apply LSB bit of the number to be
entered to Din. So Din = D3 = 1. Apply the clock. On the first falling edge of clock, the FF-3 is set,
and stored word in the register is Q3 Q2 Q1 Q0 = 1000.

Apply the next bit to Din. So Din = 1. As soon as the next negative edge of the clock hits, FF-2
will set and the stored word change to Q3 Q2 Q1 Q0 = 1100.

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Apply the next bit to be stored i.e. 1 to Din. Apply the clock pulse. As soon as the third negative
clock edge hits, FF-1 will be set and output will be modified to Q3 Q2 Q1 Q0 = 1110.

Similarly with Din = 1 and with the fourth negative clock edge arriving, the stored word in the
register is Q3 Q2 Q1 Q0 = 1111.

Truth Table

Waveforms

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Serial Input Parallel Output

 In such types of operations, the data is entered serially and taken out in parallel fashion.
 Data is loaded bit by bit. The outputs are disabled as long as the data is loading.
 As soon as the data loading gets completed, all the flip-flops contain their required data,
the outputs are enabled so that all the loaded data is made available over all the output
lines at the same time.
 4 clock cycles are required to load a four bit word. Hence the speed of operation of SIPO
mode is same as that of SISO mode.
Block Diagram

Parallel Input Serial Output (PISO)

 Data bits are entered in parallel fashion.
 The circuit shown below is a four bit parallel input serial output register.

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 Output of previous Flip Flop is connected to the input of the next one via a
combinational circuit.
 The binary input word B0, B1, B2, B3 is applied though the same combinational circuit.
 There are two modes in which this circuit can work namely - shift mode or load mode.
Load mode
When the shift/load bar line is low (0), the AND gate 2, 4 and 6 become active they will pass
B1, B2, B3 bits to the corresponding flip-flops. On the low going edge of clock, the binary input
B0, B1, B2, B3 will get loaded into the corresponding flip-flops. Thus parallel loading takes place.
Shift mode
When the shift/load bar line is low (1), the AND gate 2, 4 and 6 become inactive. Hence the
parallel loading of the data becomes impossible. But the AND gate 1,3 and 5 become active.
Therefore the shifting of data from left to right bit by bit on application of clock pulses. Thus
the parallel in serial out operation takes place.
Block Diagram

Parallel Input Parallel Output (PIPO)

In this mode, the 4 bit binary input B 0, B1, B2, B3 is applied to the data inputs D0, D1, D2,
D3 respectively of the four flip-flops. As soon as a negative clock edge is applied, the input
binary bits will be loaded into the flip-flops simultaneously. The loaded bits will appear
simultaneously to the output side. Only clock pulse is essential to load all the bits.
Block Diagram

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Bidirectional Shift Register

 If a binary number is shifted left by one position then it is equivalent to multiplying the
original number by 2. Similarly if a binary number is shifted right by one position then it
is equivalent to dividing the original number by 2.
 Hence if we want to use the shift register to multiply and divide the given binary
number, then we should be able to move the data in either left or right direction.
 Such a register is called bi-directional register. A four bit bi-directional shift register is
shown in fig.
 There are two serial inputs namely the serial right shift data input DR, and the serial left
shift data input DL along with a mode select input (M).
Block Diagram

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Operation
S.N. Condition Operation

1 With M = 1 − Shift If M = 1, then the AND gates 1, 3, 5 and 7 are enabled whereas
right operation the remaining AND gates 2, 4, 6 and 8 will be disabled.
The data at DR is shifted to right bit by bit from FF-3 to FF-0 on
the application of clock pulses. Thus with M = 1 we get the serial
right shift operation.

2 With M = 0 − Shift When the mode control M is connected to 0 then the AND gates
left operation 2, 4, 6 and 8 are enabled while 1, 3, 5 and 7 are disabled.
The data at DL is shifted left bit by bit from FF-0 to FF-3 on the
application of clock pulses. Thus with M = 0 we get the serial
right shift operation.

Universal Shift Register

A shift register which can shift the data in only one direction is called a uni-directional shift
register. A shift register which can shift the data in both directions is called a bi-directional
shift register. Applying the same logic, a shift register which can shift the data in both
directions as well as load it parallely, is known as a universal shift register. The shift register is
capable of performing the following operation −
 Parallel loading
 Left Shifting
 Right shifting
The mode control input is connected to logic 1 for parallel loading operation whereas it is
connected to 0 for serial shifting. With mode control pin connected to ground, the universal
shift register acts as a bi-directional register. For serial left operation, the input is applied to
the serial input which goes to AND gate-1 shown in figure. Whereas for the shift right
operation, the serial input is applied to D input.
Block Diagram

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Counter
in digital logic and computing, a Counter is a device which stores (and sometimes displays) the
number of times a particular event or process has occurred, often in relationship to a clock
signal. Counters are used in digital electronics for counting purpose, they can count specific
event happening in the circuit. For example, in UP counter a counter increases count for every
rising edge of clock. Not only counting, a counter can follow the certain sequence based on
our design like any random sequence 0,1,3,2… .They can also be designed with the help of flip
flops.
Counter Classification
Counters are broadly divided into two categories
1. Asynchronous counter
2. Synchronous counter
1. Asynchronous Counter
In asynchronous counter we don’t use universal clock, only first flip flop is driven by main clock
and the clock input of rest of the following flip flop is driven by output of previous flip flops.
We can understand it by following diagram-

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It is evident from timing diagram that Q0 is changing as soon as the rising edge of clock pulse is
encountered, Q1 is changing when rising edge of Q0 is encountered(because Q0 is like clock
pulse for second flip flop) and so on. In this way ripples are generated through Q0, Q1, Q2, Q3
hence it is also called RIPPLE counter.
2. Synchronous Counter
Unlike the asynchronous counter, synchronous counter has one global clock which drives each
flip flop so output changes in parallel. The one advantage of synchronous counter over
asynchronous counter is, it can operate on higher frequency than asynchronous counter as it
does not have cumulative delay because of same clock is given to each flip flop.

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Synchronous counter circuit

Timing diagram synchronous counter

From circuit diagram we see that Q0 bit gives response to each falling edge of clock while Q1 is
dependent on Q0, Q2 is dependent on Q1 and Q0 , Q3 is dependent on Q2,Q1 and Q0.
Decade Counter
A decade counter counts ten different states and then reset to its initial states. A simple
decade counter will count from 0 to 9 but we can also make the decade counters which can go
through any ten states between 0 to 15 (for 4 bit counter).
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Clock pulse Q3 Q2 Q1 Q0

0 0 0 0 0

1 0 0 0 1

2 0 0 1 0

3 0 0 1 1

4 0 1 0 0

5 0 1 0 1

6 0 1 1 0

7 0 1 1 1

8 1 0 0 0

9 1 0 0 1

10 0 0 0 0
Truth table for simple decade counter

Decade counter circuit diagram

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We see from circuit diagram that we have used nand gate for Q3 and Q1 and feeding this to
clear input line because binary representation of 10 is—1010
And we see Q3 and Q1 are 1 here, if we give NAND of these two bits to clear input then
counter will be clear at 10 and again start from beginning.
Important point: Number of flip flops used in counter are always greater than equal to
(log2 n) where n=number of states in counter.
Representation of Data
 Data and instructions cannot be entered and processed directly into computers using
human language. Any type of data be it numbers, letters, special symbols, sound or
pictures must first be converted into machine-readable form i.e. binary form. Due to this
reason, it is important to understand how a computer together with its peripheral
devices handles data in its electronic circuits, on magnetic media and in optical devices.
Data representation in digital circuits
 Electronic components, such as microprocessor, are made up of millions of electronic
circuits. The availability of high voltage(on) in these circuits is interpreted as ‘1’ while a
low voltage (off) is interpreted as ‘0’.This concept can be compared to switching on and
off an electric circuit. When the switch is closed the high voltage in the circuit causes the
bulb to light (‘1’ state).on the other hand when the switch is open, the bulb goes off (‘0’
state). This forms a basis for describing data representation in digital computers using
the binary number system.
Data representation on magnetic media
 The laser beam reflected from the land is interpreted, as [Link] laser entering the pot is
not reflected. This is interpreted as [Link] reflected pattern of light from the rotating
disk falls on a receiving photoelectric detector that transforms the patterns into digital
[Link] presence of a magnetic field in one direction on magnetic media is interpreted
as 1; while the field in the opposite direction is interpreted as “0”.Magnetic technology
is mostly used on storage devices that are coated with special magnetic materials such
as iron oxide. Data is written on the media by arranging the magnetic dipoles of some
iron oxide particles to face in the same direction and some others in the opposite
direction
Data representation on optical media
In optical devices, the presence of light is interpreted as ‘1’ while its absence is interpreted as
‘0’.Optical devices use this technology to read or store data. Take example of a CD-ROM, if the
shiny surface is placed under a powerful microscope, the surface is observed to have very tiny
holes called pits. The areas that do not have pits are called land.
Computer does not understand human language. Any data, viz., letters, symbols, pictures,
audio, videos, etc., fed to computer should be converted to machine language first. Computers
represent data in the following three forms –
Number System
We are introduced to concept of numbers from a very early age. To a computer, everything is
a number, i.e., alphabets, pictures, sounds, etc., are numbers. Number system is categorized
into four types −
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 Binary number system consists of only two values, either 0 or 1
 Octal number system represents values in 8 digits.
 Decimal number system represents values in 10 digits.
 Hexadecimal number system represents values in 16 digits.
Number System

System Base Digits

Binary 2 01

Octal 8 01234567

Decimal 10 0123456789

Hexadecimal 16 0123456789ABCDEF
Bits and Bytes
Bits − A bit is a smallest possible unit of data that a computer can recognize or use. Computer
usually uses bits in groups.
Bytes − group of eight bits is called a byte. Half a byte is called a nibble.

The following table shows conversion of Bits and Bytes −

Byte Value Bit Value

1 Byte 8 Bits

1024 Bytes 1 Kilobyte

1024 Kilobytes 1 Megabyte

1024 Megabytes 1 Gigabyte

1024 Gigabytes 1 Terabyte

1024 Terabytes 1 Petabyte

1024 Petabytes 1 Exabyte

1024 Exabytes 1 Zettabyte

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1024 Zettabytes 1 Yottabyte

1024 Yottabytes 1 Brontobyte

1024 Brontobytes 1 Geopbytes

Text Code
Text code is format used commonly to represent alphabets, punctuation marks and other
symbols. Four most popular text code systems are −
 EBCDIC
 ASCII
 Extended ASCII
 Unicode
EBCDIC
Extended Binary Coded Decimal Interchange Code is an 8-bit code that defines 256 symbols.
Given below is the EBCDIC Tabular column

ASCII
American Standard Code for Information Interchange is an 8-bit code that specifies character
values from 0 to 127.
ASCII Tabular column
ASCII Code Decimal Value Character

0000 0000 0 Null prompt

0000 0001 1 Start of heading

0000 0010 2 Start of text

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0000 0011 3 End of text

0000 0100 4 End of transmit

0000 0101 5 Enquiry

0000 0110 6 Acknowledge

0000 0111 7 Audible bell

0000 1000 8 Backspace

0000 1001 9 Horizontal tab

0000 1010 10 Line Feed

Extended ASCII
Extended American Standard Code for Information Interchange is an 8-bit code that specifies
character values from 128 to 255.
Extended ASCII Tabular column

Unicode
Unicode Worldwide Character Standard uses 4 to 32 bits to represent letters, numbers and
symbol.
Unicode Tabular Column

Data Types
A very simple but very important concept available in almost all the programming languages
which is called data types. As its name indicates, a data type represents a type of the data

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which you can process using your computer program. It can be numeric, alphanumeric,
decimal, etc.
Keep Computer Programming aside for a while and take an easy example of adding two whole
numbers 10 & 20, which can be done simply as follows −
10 + 20
Another problem where we want to add two decimal numbers 10.50 & 20.50, which will be
written as follows −
10.50 + 20.50
The two examples are straightforward. Now another example where we want to record
student information in a notebook. Here we would like to record the following information −
Name:
Class:
Section:
Age:
Sex:
Now, put one student record as per the given requirement −
Name: Zara Ali
Class: 6th
Section: J
Age: 13
Sex: F
The first example dealt with whole numbers, the second example added two decimal
numbers, whereas the third example is dealing with a mix of different data. put it as follows −
 Student name "Zara Ali" is a sequence of characters which is also called a string.
 Student class "6th" has been represented by a mix of whole number and a string of
two characters. Such a mix is called alphanumeric.
 Student section has been represented by a single character which is 'J'.
 Student age has been represented by a whole number which is 13.
 Student sex has been represented by a single character which is 'F'.
This way, we realized that in our day-to-day life, we deal with different types of data such as
strings, characters, whole numbers (integers), and decimal numbers (floating point numbers).
Similarly, when we write a computer program to process different types of data, we need to
specify its type clearly; otherwise the computer does not understand how different operations
can be performed on that given data. Different programming languages use different
keywords to specify different data types. For example, C and Java programming languages
use int to specify integer data, whereas char specifies a character data type.
Subsequent chapters will show you how to use different data types in different situations. For
now, check the important data types available in C, Java, and Python and the keywords we will
use to specify those data types.
C and Java Data Types

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C and Java support almost the same set of data types, though Java supports additional data
types. For now, we are taking a few common data types supported by both the programming
languages −
Type Keyword Value range which can be represented by this data type

Character char -128 to 127 or 0 to 255

Number int -32,768 to 32,767 or -2,147,483,648 to 2,147,483,647

Small Number short -32,768 to 32,767

Long Number long -2,147,483,648 to 2,147,483,647

Decimal Number float 1.2E-38 to 3.4E+38 till 6 decimal places

These data types are called primitive data types and you can use these data types to build
more complex data types, which are called user-defined data type, for example a string will be
a sequence of characters.
Python Data Types
Python has five standard data types but this programming language does not make use of any
keyword to specify a particular data type, rather Python is intelligent enough to understand a
given data type automatically.
 Numbers
 String
 List
 Tuple
 Dictionary
Here, Number specifies all types of numbers including decimal numbers and string represents
a sequence of characters with a length of 1 or more characters. For now, proceed with these
two data types and skip List, Tuple, and Dictionary, which are advanced data types in Python.
Number System
The technique to represent and work with numbers is called number system. Decimal number
system is the most common number system. Other popular number systems include binary
number system, octal number system, hexadecimal number system, etc.
Decimal Number System
Decimal number system is a base 10 number system having 10 digits from 0 to 9. This means
that any numerical quantity can be represented using these 10 digits. Decimal number system
is also a positional value system. This means that the value of digits will depend on its
position. Let us take an example to understand this.
Say we have three numbers – 734, 971 and 207. The value of 7 in all three numbers is
different−
 In 734, value of 7 is 7 hundreds or 700 or 7 × 100 or 7 × 10 2
 In 971, value of 7 is 7 tens or 70 or 7 × 10 or 7 × 10 1

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 In 207, value 0f 7 is 7 units or 7 or 7 × 1 or 7 × 100
The weightage of each position can be represented as follows −

In digital systems, instructions are given through electric signals; variation is done by varying
the voltage of the signal. Having 10 different voltages to implement decimal number system in
digital equipment is difficult. So, many number systems that are easier to implement digitally
have been developed. Let’s look at them in detail.
Binary Number System
The easiest way to vary instructions through electric signals is two-state system – on and off.
On is represented as 1 and off as 0, though 0 is not actually no signal but signal at a lower
voltage. The number system having just these two digits – 0 and 1 – is called binary number
system.
Each binary digit is also called a bit. Binary number system is also positional value system,
where each digit has a value expressed in powers of 2, as displayed here.

In any binary number, the rightmost digit is called least significant bit (LSB) and leftmost digit
is called most significant bit (MSB).

And decimal equivalent of this number is sum of product of each digit with its positional value.
110102 = 1×24 + 1×23 + 0×22 + 1×21 + 0×20
= 16 + 8 + 0 + 2 + 0
= 2610
Computer memory is measured in terms of how many bits it can store. Here is a chart for
memory capacity conversion.
 1 byte (B) = 8 bits
 1 Kilobytes (KB) = 1024 bytes
 1 Megabyte (MB) = 1024 KB
 1 Gigabyte (GB) = 1024 MB
 1 Terabyte (TB) = 1024 GB
 1 Exabyte (EB) = 1024 PB
 1 Zettabyte = 1024 EB

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 1 Yottabyte (YB) = 1024 ZB
Octal Number System
Octal number system has eight digits – 0, 1, 2, 3, 4, 5, 6 and 7. Octal number system is also a
positional value system with where each digit has its value expressed in powers of 8, as shown
here −

Decimal equivalent of any octal number is sum of product of each digit with its positional
value.
7268 = 7×82 + 2×81 + 6×80
= 448 + 16 + 6
= 47010
Hexadecimal Number System
Octal number system has 16 symbols – 0 to 9 and A to F where A is equal to 10, B is equal to
11 and so on till F. Hexadecimal number system is also a positional value system with where
each digit has its value expressed in powers of 16, as shown here −

Decimal equivalent of any hexadecimal number is sum of product of each digit with its
positional value.
27FB16 = 2×163 + 7×162 + 15×161 + 10×160
= 8192 + 1792 + 240 +10
= 1023410
Number System Relationship
The following table depicts the relationship between decimal, binary, octal and hexadecimal
number systems.
HEXADECIMAL DECIMAL OCTAL BINARY

0 0 0 0000

1 1 1 0001

2 2 2 0010

3 3 3 0011

4 4 4 0100

5 5 5 0101

6 6 6 0110
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7 7 7 0111

8 8 10 1000

9 9 11 1001

A 10 12 1010

B 11 13 1011

C 12 14 1100

D 13 15 1101

E 14 16 1110

F 15 17 1111
ASCII
Besides numerical data, computer must be able to handle alphabets, punctuation marks,
mathematical operators, special symbols, etc. that form the complete character set of English
language. The complete set of characters or symbols are called alphanumeric codes. The
complete alphanumeric code typically includes −
 26 upper case letters
 26 lower case letters
 10 digits
 7 punctuation marks
 20 to 40 special characters
Now a computer understands only numeric values, whatever the number system used. So all
characters must have a numeric equivalent called the alphanumeric code. The most widely
used alphanumeric code is American Standard Code for Information Interchange (ASCII). ASCII
is a 7-bit code that has 128 (27) possible codes.

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ISCII
ISCII stands for Indian Script Code for Information Interchange. IISCII was developed to
support Indian languages on computer. Language supported by IISCI include Devanagari,
Tamil, Bangla, Gujarati, Gurmukhi, Tamil, Telugu, etc. IISCI is mostly used by government
departments and before it could catch on, a new universal encoding standard
called Unicode was introduced.
Unicode
Unicode is an international coding system designed to be used with different language scripts.
Each character or symbol is assigned a unique numeric value, largely within the framework of
ASCII. Earlier, each script had its own encoding system, which could conflict with each other.
In contrast, this is what Unicode officially aims to do − Unicode provides a unique number for
every character, no matter what the platform, no matter what the program, no matter what
the language.

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Number System Conversion
There are many methods or techniques which can be used to convert numbers from one base
to another. Here the following −
 Decimal to Other Base System
 Other Base System to Decimal
 Other Base System to Non-Decimal
 Shortcut method − Binary to Octal
 Shortcut method − Octal to Binary
 Shortcut method − Binary to Hexadecimal
 Shortcut method − Hexadecimal to Binary
Decimal to Other Base System
Steps
 Step 1 − Divide the decimal number to be converted by the value of the new base.
 Step 2 − Get the remainder from Step 1 as the rightmost digit (least significant digit) of
new base number.
 Step 3 − Divide the quotient of the previous divide by the new base.
 Step 4 − Record the remainder from Step 3 as the next digit (to the left) of the new base
number.
Repeat Steps 3 and 4, getting remainders from right to left, until the quotient becomes zero in
Step 3.
The last remainder thus obtained will be the Most Significant Digit (MSD) of the new base
number.
Example −
Decimal Number: 2910
Calculating Binary Equivalent −
Step Operation Result Remainder

Step 1 29 / 2 14 1

Step 2 14 / 2 7 0

Step 3 7/2 3 1

Step 4 3/2 1 1

Step 5 1/2 0 1

As mentioned in Steps 2 and 4, the remainders have to be arranged in the reverse order so
that the first remainder becomes the Least Significant Digit (LSD) and the last remainder
becomes the Most Significant Digit (MSD).

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Decimal Number − 2910 = Binary Number − 111012.
Other Base System to Decimal System
Steps
 Step 1 − Determine the column (positional) value of each digit (this depends on the
position of the digit and the base of the number system).
 Step 2 − Multiply the obtained column values (in Step 1) by the digits in the
corresponding columns.
 Step 3 − Sum the products calculated in Step 2. The total is the equivalent value in
decimal.
Example
Binary Number − 111012
Calculating Decimal Equivalent −
Step Binary Number Decimal Number

Step 1 111012 ((1 × 24) + (1 × 23) + (1 × 22) + (0 × 21) + (1 × 20))10

Step 2 111012 (16 + 8 + 4 + 0 + 1)10

Step 3 111012 2910

Binary Number − 111012 = Decimal Number − 2910

Other Base System to Non-Decimal System
Steps
 Step 1 − Convert the original number to a decimal number (base 10).
 Step 2 − Convert the decimal number so obtained to the new base number.
Example
Octal Number − 258
Calculating Binary Equivalent −
Step 1 − Convert to Decimal
Step Octal Number Decimal Number

Step 1 258 ((2 × 81) + (5 × 80))10

Step 2 258 (16 + 5 )10

Step 3 258 2110

Octal Number − 258 = Decimal Number − 2110

Step 2 − Convert Decimal to Binary

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Step Operation Result Remainder

Step 1 21 / 2 10 1

Step 2 10 / 2 5 0

Step 3 5/2 2 1

Step 4 2/2 1 0

Step 5 1/2 0 1

Decimal Number − 2110 = Binary Number − 101012

Octal Number − 258 = Binary Number − 101012
Shortcut method - Binary to Octal
Steps
 Step 1 − Divide the binary digits into groups of three (starting from the right).
 Step 2 − Convert each group of three binary digits to one octal digit.
Example
Binary Number − 101012
Calculating Octal Equivalent −
Step Binary Number Octal Number
Step 1 101012 010 101
Step 2 101012 28 58
Step 3 101012 258
Binary Number − 101012 = Octal Number − 258
Shortcut method - Octal to Binary
Steps
 Step 1 − Convert each octal digit to a 3 digit binary number (the octal digits may be
treated as decimal for this conversion).
 Step 2 − Combine all the resulting binary groups (of 3 digits each) into a single binary
number.
Example
Octal Number − 258
Calculating Binary Equivalent −
Step Octal Number Binary Number
Step 1 258 210 510
Step 2 258 0102 1012

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Step 3 258 0101012
Octal Number − 258 = Binary Number − 101012
Shortcut method - Binary to Hexadecimal
Steps
 Step 1 − Divide the binary digits into groups of four (starting from the right).
 Step 2 − Convert each group of four binary digits to one hexadecimal symbol.
Example
Binary Number − 101012
Calculating hexadecimal Equivalent −
Step Binary Number Hexadecimal Number
Step 1 101012 0001 0101
Step 2 101012 110 510
Step 3 101012 1516
Binary Number − 101012 = Hexadecimal Number − 1516
Shortcut method - Hexadecimal to Binary
Steps
 Step 1 − Convert each hexadecimal digit to a 4 digit binary number (the hexadecimal
digits may be treated as decimal for this conversion).
 Step 2 − Combine all the resulting binary groups (of 4 digits each) into a single binary
number.
Example
Hexadecimal Number − 1516
Calculating Binary Equivalent −
Step Hexadecimal Number Binary Number
Step 1 1516 110 510
Step 2 1516 00012 01012
Step 3 1516 000101012
Hexadecimal Number − 1516 = Binary Number − 101012
Complement Arithmetic
Complements are used in the digital computers in order to simplify the subtraction operation
and for the logical manipulations. For each radix-r system (radix r represents base of number
system) there are two types of complements.
S.N. Complement Description
1 Radix Complement The radix complement is referred to as the r's
complement
2 Diminished Radix The diminished radix complement is referred to as the
Complement (r-1)'s complement

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Binary system complements
As the binary system has base r = 2. So the two types of complements for the binary system
are 2's complement and 1's complement.
1's complement
The 1's complement of a number is found by changing all 1's to 0's and all 0's to 1's. This is
called as taking complement or 1's complement. Example of 1's Complement is as follows.

2's complement
The 2's complement of binary number is obtained by adding 1 to the Least Significant Bit (LSB)
of 1's complement of the number.
2's complement = 1's complement + 1
Example of 2's Complement is as follows.

Fixed Point and Floating Point Number Representations

Digital Computers use Binary number system to represent all types of information inside the
computers. Alphanumeric characters are represented using binary bits (i.e., 0 and 1). Digital
representations are easier to design, storage is easy, accuracy and precision are greater.
There are various types of number representation techniques for digital number
representation, for example: Binary number system, octal number system, decimal number
system, and hexadecimal number system etc. But Binary number system is most relevant and
popular for representing numbers in digital computer system.
Storing Real Number
These are structures as following below −

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There are two major approaches to store real numbers (i.e., numbers with fractional
component) in modern computing. These are (i) Fixed Point Notation and (ii) Floating Point
Notation. In fixed point notation, there are a fixed number of digits after the decimal point,
whereas floating point number allows for a varying number of digits after the decimal point.
Fixed-Point Representation −
This representation has fixed number of bits for integer part and for fractional part. For
example, if given fixed-point representation is [Link], then you can store minimum value is
0000.0001 and maximum value is 9999.9999. There are three parts of a fixed-point number
representation: the sign field, integer field, and fractional field.

We can represent these numbers using:

 Signed representation: range from -(2(k-1)-1) to (2(k-1)-1), for k bits.
 1’s complement representation: range from -(2(k-1)-1) to (2(k-1)-1), for k bits.
 2’s complementation representation: range from -(2(k-1)) to (2(k-1)-1), for k bits.
2’s complementation representation is preferred in computer system because of unambiguous
property and easier for arithmetic operations.
Example −Assume number is using 32-bit format which reserve 1 bit for the sign, 15 bits for
the integer part and 16 bits for the fractional part.
Then, -43.625 is represented as following:

Where, 0 is used to represent + and 1 is used to represent. 000000000101011 is 15 bit binary

value for decimal 43 and 1010000000000000 is 16 bit binary value for fractional 0.625.
The advantage of using a fixed-point representation is performance and disadvantage is
relatively limited range of values that they can represent. So, it is usually inadequate for

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numerical analysis as it does not allow enough numbers and accuracy. A number whose
representation exceeds 32 bits would have to be stored inexactly.

These are above smallest positive number and largest positive number which can be store in
32-bit representation as given above format. Therefore, the smallest positive number is 2 -16 ≈
0.000015 approximate and the largest positive number is (215-1)+(1-2-16)=215(1-2-16) =32768,
and gap between these numbers is 2-16.
We can move the radix point either left or right with the help of only integer field is 1.
Floating Point Representation
This representation does not reserve a specific number of bits for the integer part or the
fractional part. Instead it reserves a certain number of bits for the number (called the mantissa
or significand) and a certain number of bits to say where within that number the decimal place
sits (called the exponent).
The floating number representation of a number has two part: the first part represents a
signed fixed point number called mantissa. The second part of designates the position of the
decimal (or binary) point and is called the exponent. The fixed point mantissa may be fraction
or an integer. Floating -point is always interpreted to represent a number in the following
form: Mxre.
Only the mantissa m and the exponent e are physically represented in the register (including
their sign). A floating-point binary number is represented in a similar manner except that is
uses base 2 for the exponent. A floating-point number is said to be normalized if the most
significant digit of the mantissa is 1.

So, actual number is (-1)s(1+m)x2(e-Bias), where s is the sign bit, m is the mantissa, e is the
exponent value, and Bias is the bias number.
Note that signed integers and exponent are represented by either sign representation, or
one’s complement representation, or two’s complement representation.
The floating point representation is more flexible. Any non-zero number can be represented in
the normalized form of ±(1.b1b2b3 ...)2x2n This is normalized form of a number x.
The following description explains terminology and primary details of IEEE 754 binary floating
point representation. The discussion confines to single and double precision formats.
Usually, a real number in binary will be represented in the following format,
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ImIm-1…I2I1I0.F1F2…FnFn-1
Where Im and Fn will be either 0 or 1 of integer and fraction parts respectively.
A finite number can also represented by four integers components, a sign (s), a base (b), a
significand (m), and an exponent (e). Then the numerical value of the number is evaluated as
(-1)s x m x be ________ Where m < |b|
Depending on base and the number of bits used to encode various components, the IEEE
754 standard defines five basic formats. Among the five formats, the binary32 and the
binary64 formats are single precision and double precision formats respectively in which the
base is 2.
Table – 1 Precision Representation
Precision Base Sign Exponent Significand
Single precision 2 1 8 23+1
Double precision 2 1 11 52+1
Single Precision Format:
As mentioned in Table 1 the single precision format has 23 bits for significand (1 represents
implied bit, details below), 8 bits for exponent and 1 bit for sign.
For example, the rational number 9÷2 can be converted to single precision float format as
following,
9(10) ÷ 2(10) = 4.5(10) = 100.1(2)
The result said to be normalized, if it is represented with leading 1 bit, i.e. 1.001(2) x 22.
(Similarly when the number 0.000000001101(2) x 23 is normalized, it appears as 1.101(2) x 2-6).
Omitting this implied 1 on left extreme gives us the mantissa of float number. A normalized
number provides more accuracy than corresponding de-normalized number. The implied most
significant bit can be used to represent even more accurate significand (23 + 1 = 24 bits) which
is called subnormal representation. The floating point numbers are to be represented in
normalized form.
The subnormal numbers fall into the category of de-normalized numbers. The subnormal
representation slightly reduces the exponent range and can’t be normalized since that would
result in an exponent which doesn’t fit in the field. Subnormal numbers are less accurate, i.e.
they have less room for nonzero bits in the fraction field, than normalized numbers. Indeed,
the accuracy drops as the size of the subnormal number decreases. However, the subnormal
representation is useful in filing gaps of floating point scale near zero.
In other words, the above result can be written as (-1)0 x 1.001(2) x 22 which yields the integer
components as s = 0, b = 2, significand (m) = 1.001, mantissa = 001 and e = 2. The
corresponding single precision floating number can be represented in binary as shown below,

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Where the exponent field is supposed to be 2, yet encoded as 129 (127+2) called biased
exponent. The exponent field is in plain binary format which also represents negative
exponents with an encoding (like sign magnitude, 1’s complement, 2’s complement, etc.). The
biased exponent is used for the representation of negative exponents. The biased exponent
has advantages over other negative representations in performing bitwise comparing of two
floating point numbers for equality.
A bias of (2n-1 – 1), where n is # of bits used in exponent, is added to the exponent (e) to get
biased exponent (E). So, the biased exponent (E) of single precision number can be obtained as
E = e + 127
The range of exponent in single precision format is -128 to +127. Other values are used for
special symbols.
Note: When we unpack a floating point number the exponent obtained is the biased
exponent. Subtracting 127 from the biased exponent we can extract unbiased exponent.
Double Precision Format:
As mentioned in Table – 1 the double precision format has 52 bits for significand (1 represents
implied bit), 11 bits for exponent and 1 bit for sign. All other definitions are same for double
precision format, except for the size of various components.
Precision:
The smallest change that can be represented in floating point representation is called as
precision. The fractional part of a single precision normalized number has exactly 23 bits of
resolution, (24 bits with the implied bit). This corresponds to log (10) (223) = 6.924 = 7 (the
characteristic of logarithm) decimal digits of accuracy. Similarly, in case of double precision
numbers the precision is log(10) (252) = 15.654 = 16 decimal digits.
Accuracy:
Accuracy in floating point representation is governed by number of significand bits, whereas
range is limited by exponent. Not all real numbers can exactly be represented in floating point
format. For any numberwhich is not floating point number, there are two options for floating
point approximation, say, the closest floating point number less than x as x_ and the closest
floating point number greater than x as x+. A rounding operation is performed on number of
significant bits in the mantissa field based on the selected mode. The round down mode
causes x set to x_, the round up mode causes x set to x+, the round towards zero mode causes
x is either x_ or x+ whichever is between zero and. The round to nearest mode sets x to x_ or
x+ whichever is nearest to x. Usually round to nearest is most used mode. The closeness of
floating point representation to the actual value is called as accuracy.
Special Bit Patterns:

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The standard defines few special floating point bit patterns. Zero can’t have most significant 1
bit, hence can’t be normalized. The hidden bit representation requires a special technique for
storing zero. We will have two different bit patterns +0 and -0 for the same numerical value
zero. For single precision floating point representation, these patterns are given below,
0 00000000 00000000000000000000000 = +0
1 00000000 00000000000000000000000 = -0
Similarly, the standard represents two different bit patters for +INF and -INF. The same are
given below,
0 11111111 00000000000000000000000 = +INF
1 11111111 00000000000000000000000 = -INF
All of these special numbers, as well as other special numbers (below) are subnormal
numbers, represented through the use of a special bit pattern in the exponent field. This
slightly reduces the exponent range, but this is quite acceptable since the range is so large.
An attempt to compute expressions like 0 x INF, 0 ÷ INF, etc. make no mathematical sense. The
standard calls the result of such expressions as Not a Number (NaN). Any subsequent
expression with NaN yields NaN. The representation of NaN has non-zero significand and all 1s
in the exponent field. These are shown below for single precision format (x is don’t care bits),
x 11111111 1m0000000000000000000000
Where m can be 0 or 1. This gives us two different representations of NaN.
0 11111111 110000000000000000000000 _____________ Signaling NaN (SNaN)
0 11111111 100000000000000000000000 _____________Quiet NaN (QNaN)
Usually QNaN and SNaN are used for error handling. QNaN do not raise any exceptions as they
propagate through most operations. Whereas SNaN are which when consumed by most
operations will raise an invalid exception.
Overflow and Underflow:
Overflow is said to occur when the true result of an arithmetic operation is finite but larger in
magnitude than the largest floating point number which can be stored using the given
precision. Underflow is said to occur when the true result of an arithmetic operation is smaller
in magnitude (infinitesimal) than the smallest normalized floating point number which can be
stored. Overflow can’t be ignored in calculations whereas underflow can effectively be
replaced by zero.
Endianness:
The IEEE 754 standard defines a binary floating point format. The architecture details are left
to the hardware manufacturers. The storage order of individual bytes in binary floating point
numbers varies from architecture to architecture.
Error Detection Codes
The binary information is transferred from one location to another location through some
communication medium. The external noise can change bits from 1 to 0 or 0 to [Link] changes
in values are called errors. For efficient data transfer, there should be an error detection and
correction codes. An error detection code is a binary code that detects digital errors during
transmission. A famous error detection code is a Parity Bit method.

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Parity Bit Method :
A parity bit is an extra bit included in binary message to make total number of 1’s either odd or
even. Parity word denotes number of 1’s in a binary string. There are two parity system-even
and odd. In even parity system 1 is appended to binary string it there is an odd number of 1’s
in string otherwise 0 is appended to make total even number of 1’s.

In odd parity system, 1 is appended to binary string if there is even a number of 1’s to make an
odd number of 1’s. The receiver knows that whether sender is an odd parity generator or even
parity generator. Suppose if sender is an odd parity generator then there must be an odd
number of 1’s in received binary string. If an error occurs to a single bit that is either bit is
changed to 1 to 0 or O to 1, received binary bit will have an even number of 1’s which will
indicate an error.

The limitation of this method is that only error in a single bit would be identified.

MESSAGE (XYZ) P(ODD) P(EVEN)

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000 1 0

001 0 1

010 0 1

011 1 0

100 0 1

101 1 0

110 1 0

111 0 1

Figure – Error Detection with Odd Parity Bit

Points to Remember :
 In 1’s complement of signed number +0 and -0 has two different representation.
 The range of signed magnitude representation of an 8-bit number in which 1-bit is used
as a signed bit as follows -27 to +27.

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 Floating point number is said to be normalized if most significant digit of mantissa is
one. For example, 6-bit binary number 001101 is normalized because of two leading 0’s.
 Booth algorithm that uses two n bit numbers for multiplication gives results in 2n bits.
 The booth algorithm uses 2’s complement representation of numbers and work for both
positive and negative numbers.
 If k-bits are used to represent exponent then bits number = (2 k-1) and range of exponent
= – (2k-1 -1) to (2k-1).
Features of Error detection codes
These are the following features of error detection codes:
 These codes are used when we use message backward error correction techniques
for reliable data transmission. A feedback message is sent by the receiver to inform
the sender whether the message is received without any error or not at the receiver
side. If the message contains errors, the sender retransmits the message.
 In error detection codes, in fixed-size blocks of bits, the message is contained. In this,
the redundant bits are added for correcting and detecting errors.
 These codes involve checking of the error. No matter how many error bits are there
and the type of error.
 Parity check, Checksum, and CRC are the error detection technique.
Computer Arithmetic
Computer arithmetic is a field of computer science that investigates how computers should
represent numbers and perform operations on them. It includes integer arithmetic, fixed-point
arithmetic, and the arithmetic this book focuses on: floating-point (FP) arithmetic, which will
be more thoroughly described in Chapter 1. For now, let us say that it is the common way
computers approximate real numbers and that it is described in the IEEE-754 standard [IEE
08]. As in scientific notations, numbers are represented using an exponent and a significand,
except that this significand has to fit on a certain amount of bits. As this number of bits (called
precision) is limited, each operation may be inexact due to the rounding. This makes computer
arithmetic sometimes inaccurate: the result of a long computation may be far from the
mathematical result that would have been obtained if all the computations were correct. This
also makes computer arithmetic unintuitive: for instance, the FP addition is not always
associative.
Register Transfer Language
A digital computer system exhibits an interconnection of digital modules such as registers,
decoders, arithmetic elements, and Control logic.
These digital modules are interconnected with some common data and control paths to form a
complete digital system.
Moreover, digital modules are best defined by the registers and the operations that are
performed on the data stored in them.
The operations performed on the data stored in registers are called Micro-operations.
The internal hardware organization of a digital system is best defined by specifying:
o The set of registers and the flow of data between them.

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o The sequence of micro-operations performed on the data which are stored in the
registers.
o The control paths that initiates the sequence of micro-operation
The Register Transfer Language is the symbolic representation of notations used to specify the
sequence of micro-operations.
In a computer system, data transfer takes place between processor registers and memory and
between processor registers and input-output systems. These data transfer can be
represented by standard notations given below:
o Notations R0, R1, R2..., and so on represent processor registers.
o The addresses of memory locations are represented by names such as LOC, PLACE,
MEM, etc.
o Input-output registers are represented by names such as DATA IN, DATA OUT and so on.
o The content of register or memory location is denoted by placing square brackets
around the name of the register or memory location.
Register Transfer
The term Register Transfer refers to the availability of hardware logic circuits that can perform
a given micro-operation and transfer the result of the operation to the same or another
register.
Most of the standard notations used for specifying operations on various registers are stated
below.
 The memory address register is designated by MAR.
 Program Counter PC holds the next instruction's address.
 Instruction Register IR holds the instruction being executed.
 R1 (Processor Register).
 We can also indicate individual bits by placing them in parenthesis. For instance, PC
(8-15), R2 (5), etc.
 Data Transfer from one register to another register is represented in symbolic form
by means of replacement operator. For instance, the following statement denotes a
transfer of the data of register R1 into register R2.
1. R2 ← R1
o Typically, most of the users want the transfer to occur only in a predetermined control
condition. This can be shown by following if-then statement:
If (P=1) then (R2 ← R1); Here P is a control signal generated in the control section.
o It is more convenient to specify a control function (P) by separating the control variables
from the register transfer operation. For instance, the following statement defines the
data transfer operation under a specific control function (P).
1. P: R2 ← R1
The following image shows the block diagram that depicts the transfer of data from R1 to R2.

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Here, the letter 'n' indicates the number of bits for the register. The 'n' outputs of the register
R1 are connected to the 'n' inputs of register R2.
A load input is activated by the control variable 'P' which is transferred to the register R2.
Bus and Memory Transfers
A digital system composed of many registers, and paths must be provided to transfer
information from one register to another. The number of wires connecting all of the registers
will be excessive if separate lines are used between each register and all other registers in the
system.
A bus structure, on the other hand, is more efficient for transferring information between
registers in a multi-register configuration system.
A bus consists of a set of common lines, one for each bit of register, through which binary
information is transferred one at a time. Control signals determine which register is selected
by the bus during a particular register transfer.
The following block diagram shows a Bus system for four registers. It is constructed with the
help of four 4 * 1 Multiplexers each having four data inputs (0 through 3) and two selection
inputs (S1 and S2).
We have used labels to make it more convenient for you to understand the input-output
configuration of a Bus system for four registers. For instance, output 1 of register A is
connected to input 0 of MUX1.

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The two selection lines S1 and S2 are connected to the selection inputs of all four multiplexers.
The selection lines choose the four bits of one register and transfer them into the four-line
common bus.
When both of the select lines are at low logic, i.e. S1S0 = 00, the 0 data inputs of all four
multiplexers are selected and applied to the outputs that forms the bus. This, in turn, causes
the bus lines to receive the content of register A since the outputs of this register are
connected to the 0 data inputs of the multiplexers.
Similarly, when S1S0 = 01, register B is selected, and the bus lines will receive the content
provided by register B.
The following function table shows the register that is selected by the bus for each of the four
possible binary values of the Selection lines.

Note: The number of multiplexers needed to construct the bus is equal to the number of bits
in each register. The size of each multiplexer must be 'k * 1' since it multiplexes 'k' data lines.
For instance, a common bus for eight registers of 16 bits each requires 16 multiplexers, one for
each line in the bus. Each multiplexer must have eight data input lines and three selection lines
to multiplex one significant bit in the eight registers.
A bus system can also be constructed using three-state gates instead of multiplexers.

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The three state gates can be considered as a digital circuit that has three gates, two of which
are signals equivalent to logic 1 and 0 as in a conventional gate. However, the third gate
exhibits a high-impedance state.
The most commonly used three state gates in case of the bus system is a buffer gate.
The graphical symbol of a three-state buffer gate can be represented as:

The following diagram demonstrates the construction of a bus system with three-state buffers.

 The outputs generated by the four buffers are connected to form a single bus line.
 Only one buffer can be in active state at a given point of time.
 The control inputs to the buffers determine which of the four normal inputs will
communicate with the bus line.
 A 2 * 4 decoder ensures that no more than one control input is active at any given
point of time.
Memory Transfer
Most of the standard notations used for specifying operations on memory transfer are stated
below.

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o The transfer of information from a memory unit to the user end is called
a Read operation.
o The transfer of new information to be stored in the memory is called a Write operation.
o A memory word is designated by the letter M.
o We must specify the address of memory word while writing the memory transfer
operations.
o The address register is designated by AR and the data register by DR.
o Thus, a read operation can be stated as:

1. Read: DR ← M [AR]
o The Read statement causes a transfer of information into the data register (DR) from
the memory word (M) selected by the address register (AR).
o And the corresponding write operation can be stated as:

1. Write: M [AR] ← R1
o The Write statement causes a transfer of information from register R1 into the memory
word (M) selected by address register (AR).

Micro-Operations
The operations executed on data stored in registers are called micro-operations. A micro-
operation is an elementary operation performed on the information stored in one or more
registers.
Example: Shift, count, clear and load.
Types of Micro-Operations
The micro-operations in digital computers are of 4 types:
1. Register transfer micro-operations transfer binary information from one register to
another.
2. Arithmetic micro-operations perform arithmetic operations on numeric data stored
in registers.
3. Logic micro-operations perform bit manipulation operation on non-numeric data
stored in registers.
4. Shift micro-operations perform shift micro-operations performed on data.
Arithmetic Micro-operations
In general, the Arithmetic Micro-operations deals with the operations performed on numeric
data stored in the registers.
The basic Arithmetic Micro-operations are classified in the following categories:
1. Addition
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2. Subtraction
3. Increment
4. Decrement
5. Shift
Some additional Arithmetic Micro-operations are classified as:
1. Add with carry
2. Subtract with borrow
3. Transfer/Load, etc.
The following table shows the symbolic representation of various Arithmetic Micro-operations.

Symbolic Representation Description

R3 ← R1 + R2 The contents of R1 plus R2 are transferred to R3.

R3 ← R1 - R2 The contents of R1 minus R2 are transferred to R3.

R2 ← R2' Complement the contents of R2 (1's complement)

R2 ← R2' + 1 2's complement the contents of R2 (negate)

R3 ← R1 + R2' + 1 R1 plus the 2's complement of R2 (subtraction)

R1 ← R1 + 1 Increment the contents of R1 by one

R1 ← R1 - 1 Decrement the contents of R1 by one

Note: The increment and decrement micro-operations are symbolized by '+ 1' and '? 1'
respectively. Arithmetic operations like multiply and divide are not included in the basic set of
micro-operations.
Logic Micro-Operations
These are binary micro-operations performed on the bits stored in the registers. These
operations consider each bit separately and treat them as binary variables.
Let us consider the X-OR micro-operation with the contents of two registers R1 and R2.
P: R1 ← R1 X-OR R2
In the above statement we have also included a Control Function.
Assume that each register has 3 bits. Let the content of R1 be 010 and R2 be 100. The X-OR
micro-operation will be:

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Shift Micro-Operations
These are used for serial transfer of data. That means we can shift the contents of the register
to the left or right. In the shift left operation the serial input transfers a bit to the right most
position and in shift right operation the serial input transfers a bit to the left most position.
There are three types of shifts as follows:
a) Logical Shift
It transfers 0 through the serial input. The symbol "shl" is used for logical shift left and "shr" is
used for logical shift right.
R1 ← she R1
R1 ← she R1
The register symbol must be same on both sides of arrows.
b) Circular Shift
This circulates or rotates the bits of register around the two ends without any loss of data or
contents. In this, the serial output of the shift register is connected to its serial
input. "cil" and "cir" is used for circular shift left and right respectively.
c) Arithmetic Shift
This shifts a signed binary number to left or right. An arithmetic shift left multiplies a signed
binary number by 2 and shift left divides the number by 2. Arithmetic shift micro-operation
leaves the sign bit unchanged because the signed number remains same when it is multiplied
or divided by 2.
Arithmetic Logical Unit
Instead of having individual registers performing the micro-operations, computer system
provides a number of registers connected to a common unit called as Arithmetic Logical Unit
(ALU). ALU is the main and one of the most important unit inisde CPU of computer. All the
logical and mathematical operations of computer are performed here. The contents of specific
register is placed in the in the input of ALU. ALU performs the given operation and then
transfer it to the destination register.

Registers

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Register is a very fast computer memory, used to store data/instruction in-execution.
A Register is a group of flip-flops with each flip-flop capable of storing one bit of information.
An n-bit register has a group of n flip-flops and is capable of storing binary information of n-
bits.
A register consists of a group of flip-flops and gates. The flip-flops hold the binary information
and gates control when and how new information is transferred into a register. Various types
of registers are available commercially. The simplest register is one that consists of only flip-
flops with no external gates.
These days registers are also implemented as a register file.
Loading the Registers
The transfer of new information into a register is referred to as loading the register. If all the
bits of register are loaded simultaneously with a common clock pulse than the loading is said
to be done in parallel.
Instruction Codes
While a Program, as we all know, is, A set of instructions that specify the operations,
operands, and the sequence by which processing has to occur. An instruction code is a group
of bits that tells the computer to perform a specific operation part.
Instruction Code: Operation Code
The operation code of an instruction is a group of bits that define operations such as add,
subtract, multiply, shift and compliment. The number of bits required for the operation code
depends upon the total number of operations available on the computer. The operation code
must consist of at least n bits for a given 2^n operations. The operation part of an instruction
code specifies the operation to be performed.
Instruction Code: Register Part
The operation must be performed on the data stored in registers. An instruction code
therefore specifies not only operations to be performed but also the registers where the
operands(data) will be found as well as the registers where the result has to be stored.
Stored Program Organisation
The simplest way to organize a computer is to have Processor Register and instruction code
with two parts. The first part specifies the operation to be performed and second specifies an
address. The memory address tells where the operand in memory will be found.
Instructions are stored in one section of memory and data in another.

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Computers with a single processor register is known as Accumulator (AC). The operation is
performed with the memory operand and the content of AC.
Common Bus System
The basic computer has 8 registers, a memory unit and a control unit. Paths must be provided
to transfer data from one register to another. An efficient method for transferring data in a
system is to use a Common Bus System. The output of registers and memory are connected to
the common bus.
Load(LD)
The lines from the common bus are connected to the inputs of each register and data inputs of
memory. The particular register whose LD input is enabled receives the data from the bus
during the next clock pulse transition.
Before studying about instruction formats lets first study about the operand address parts.
When the 2nd part of an instruction code specifies the operand, the instruction is said to
have immediate operand. And when the 2nd part of the instruction code specifies the address
of an operand, the instruction is said to have a direct address. And in indirect address, the 2nd
part of instruction code, specifies the address of a memory word in which the address of the
operand is found.
Computer Instructions
The basic computer has three instruction code formats. The Operation code (opcode) part of
the instruction contains 3 bits and remaining 13 bits depends upon the operation code
encountered.
There are three types of formats:
1. Memory Reference Instruction
It uses 12 bits to specify the address and 1 bit to specify the addressing mode (I). I is equal
to 0 for direct address and 1 for indirect address.
2. Register Reference Instruction

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These instructions are recognized by the opcode 111 with a 0 in the left most bit of instruction.
The other 12 bits specify the operation to be executed.
3. Input-Output Instruction
These instructions are recognized by the operation code 111 with a 1 in the left most bit of
instruction. The remaining 12 bits are used to specify the input-output operation.
Format of Instruction
The format of an instruction is depicted in a rectangular box symbolizing the bits of an
instruction. Basic fields of an instruction format are given below:
1. An operation code field that specifies the operation to be performed.
2. An address field that designates the memory address or register.
3. A mode field that specifies the way the operand of effective address is determined.
Computers may have instructions of different lengths containing varying number of addresses.
The number of address field in the instruction format depends upon the internal organization
of its registers.
Adressing Modes and Instruction Cycle
The operation field of an instruction specifies the operation to be performed. This operation
will be executed on some data which is stored in computer registers or the main memory. The
way any operand is selected during the program execution is dependent on the addressing
mode of the instruction. The purpose of using addressing modes is as follows:
1. To give the programming versatility to the user.
2. To reduce the number of bits in addressing field of instruction.
Types of Addressing Modes
Below we have discussed different types of addressing modes one by one:
Immediate Mode
In this mode, the operand is specified in the instruction itself. An immediate mode instruction
has an operand field rather than the address field.
For example: ADD 7, which says Add 7 to contents of accumulator. 7 is the operand here.
Register Mode
In this mode the operand is stored in the register and this register is present in CPU. The
instruction has the address of the Register where the operand is stored.

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Advantages
 Shorter instructions and faster instruction fetch.
 Faster memory access to the operand(s)
Disadvantages
 Very limited address space
 Using multiple registers helps performance but it complicates the instructions.
Register Indirect Mode
In this mode, the instruction specifies the register whose contents give us the address of
operand which is in memory. Thus, the register contains the address of operand rather than
the operand itself.

Auto Increment/Decrement Mode

In this the register is incremented or decremented after or before its value is used.
Direct Addressing Mode
In this mode, effective address of operand is present in instruction itself.
 Single memory reference to access data.
 No additional calculations to find the effective address of the operand.

For Example: ADD R1, 4000 - In this the 4000 is effective address of operand.
NOTE: Effective Address is the location where operand is present.
Indirect Addressing Mode

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In this, the address field of instruction gives the address where the effective address is stored
in memory. This slows down the execution, as this includes multiple memory lookups to find
the operand.

Displacement Addressing Mode

In this the contents of the indexed register is added to the Address part of the instruction, to
obtain the effective address of operand.
EA = A + (R), In this the address field holds two values, A(which is the base value) and R(that
holds the displacement), or vice versa.

Relative Addressing Mode

It is a version of Displacement addressing mode.
In this the contents of PC(Program Counter) is added to address part of instruction to obtain
the effective address.
EA = A + (PC), where EA is effective address and PC is program counter.
The operand is A cells away from the current cell(the one pointed to by PC)
Base Register Addressing Mode
It is again a version of Displacement addressing mode. This can be defined as EA = A + (R),
where A is displacement and R holds pointer to base address.
Stack Addressing Mode

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In this mode, operand is at the top of the stack. For example: ADD, this instruction will POP top
two items from the stack, add them, and will then PUSH the result to the top of the stack.
Instruction Cycle
An instruction cycle, also known as fetch-decode-execute cycle is the basic operational
process of a computer. This process is repeated continuously by CPU from boot up to shut
down of computer.
Following are the steps that occur during an instruction cycle:
1. Fetch the Instruction
The instruction is fetched from memory address that is stored in PC(Program Counter) and
stored in the instruction register IR. At the end of the fetch operation, PC is incremented by 1
and it then points to the next instruction to be executed.
2. Decode the Instruction
The instruction in the IR is executed by the decoder.
3. Read the Effective Address
If the instruction has an indirect address, the effective address is read from the memory.
Otherwise operands are directly read in case of immediate operand instruction.
4. Execute the Instruction
The Control Unit passes the information in the form of control signals to the functional unit of
CPU. The result generated is stored in main memory or sent to an output device.
The cycle is then repeated by fetching the next instruction. Thus in this way the instruction
cycle is repeated continuously.

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Memory-Reference Instructions
The basic computer has 16-bit instruction register (IR) which can denote either memory
reference or register reference or input-output instruction.
1. Memory Reference – These instructions refer to memory address as an operand. The
other operand is always accumulator. Specifies 12-bit address, 3-bit opcode (other than
111) and 1-bit addressing mode for direct and indirect addressing.

Example –
IR register contains = 0001XXXXXXXXXXXX, i.e. ADD after fetching and decoding of instruction
we find out that it is a memory reference instruction for ADD operation.
Hence, DR ← M[AR]
AC ← AC + DR, SC ← 0
Input-Output instructions
Input/Output – These instructions are for communication between computer and outside
environment. The IR(14 – 12) is 111 (differentiates it from memory reference) and IR(15) is 1
(differentiates it from register reference instructions). The rest 12 bits specify I/O operation.

Example –
IR register contains = 1111100000000000, i.e. INP after fetch and decode cycle we find out
that it is an input/output instruction for inputing character. Hence, INPUT character from
peripheral device.
The set of instructions incorporated in16 bit IR register are:
1. Arithmetic, logical and shift instructions (and, add, complement, circulate left, right,
etc)
2. To move information to and from memory (store the accumulator, load the
accumulator)
3. Program control instructions with status conditions (branch, skip)
4. Input output instructions (input character, output character)
Machine Language
Machine language, or machine code, is a low-level language comprised of binary digits (ones
and zeros). High-level languages, such as Swift and C++ must be compiled into machine
language before the code is run on a computer.
Since computers are digital devices, they only recognize binary data. Every program, video,
image, and character of text is represented in binary. This binary data, or machine code, is
processed as input by the CPU. The resulting output is sent to the operating system or

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an application, which displays the data visually. For example, the ASCII value for the letter "A"
is 01000001 in machine code, but this data is displayed as "A" on the screen. An image may
have thousands or even millions of binary values that determine the color of each pixel.
While machine code is comprised of 1s and 0s, different processor architectures use different
machine code. For example, a PowerPC processor, which has a RISC architecture, requires
different code than an Intel x86 processor, which has a CISC architecture. A compiler must
compile high-level source cod for the correct processor architecture in order for a program to
run correctly.
The exact machine language for a program or action can differ by operating system. The
specific operating system dictates how a compiler writes a program or action into machine
language.
Computer programs are written in one or more programming languages, like C++, Java,
or Visual Basic. A computer cannot directly understand the programming languages used to
create computer programs, so the program code must be compiled. Once a program's code is
compiled, the computer can understand it because the program's code is turned into machine
language.
Machine language example
Below is an example of machine language (binary) for the text "Hello World."
01001000 01100101 01101100 01101100 01101111 00100000 01010111 01101111 01110010
01101100 01100100
Below is another example of machine language (non-binary), which prints the letter "A" 1000
times to the computer screen.
169 1 160 0 153 0 128 153 0 129 153 130 153 0 131 200 208 241 96
Assembly language
Sometimes referred to as assembly or ASM, an assembly language is a low-level programming
language.
Programs written in assembly languages are compiled by an assembler. Every assembler has
its own assembly language, which is designed for one specific computer architecture.
Why is ASM useful?
Machine language is a series of numbers, which is not easy for humans to read. Using ASM,
programmers can write human-readable programs that correspond almost exactly to machine
language.
The disadvantage is that everything the computer does must be described explicitly, in precise
detail. The advantage is that the programmer has maximum control over what the computer is
doing.
Why is ASM a "low-level" language?
Assembly is called a low-level programming language because there's (nearly) a one-to-one
relationship between what it tells the computer to do, and what the computer does. In
general, one line of an assembly program contains a maximum of one instruction for the
computer.
How is ASM different from a "high-level" language?

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High-level languages provide abstractions of low-level operations which allow the programmer
to focus more on describing what they want to do, and less on how it should be done.
Programming this way is more convenient and makes programs easier to read at the sacrifice
of low-level control.
Programs written in high-level languages never match the raw speed and efficiency of
programs written in assembly. Examples of high-level languages
include Python, Java, JavaScript, Clojure, and Lisp.
What is a "mid-level" language?
Mid-level languages or lower-level languages provide some high-level abstractions to make
the programmer's life easier, while still providing access to low-level operations. They are
often used to write operating systems, so they are sometimes called system programming
languages.
Programs written in mid-level languages can perform as well, or nearly as well, as programs
written in assembly language. Examples of mid-level programming languages
include C, C++, Ada, Nim, and Rust.
Is ASM portable?
No. Because assembly languages are tied to one specific computer architecture, they are
not portable. A program written in one assembly language would need to be completely
rewritten for it to run on another type of machine.
Portability is one of the main advantages of higher-level languages. The C programming
language is often called "portable assembly" because C compilers exist for nearly every
modern system architecture. A program written in C may require some changes before it will
compile on another computer, but the core language is portable.
Generally speaking, the higher-level a language is, the fewer changes need to be made for it to
run on another architecture. The lowest-level languages — machine language and assembly
language — are not portable.
Machine Language vs Assembly Language
Machine language and assembly language are both low-level languages, but machine code is
below assembly in the hierarchy of computer languages. Assembly language includes human-
readable commands, such as mov, add, and sub, while machine language does not contain any
words or even letters. Some developers manually write assembly language to optimize a
program, but they do not write machine code. Only developers who write software compilers
need to worry about machine language.
NOTE: While machine code is technically comprised of binary data, it may also be represented
in hexadecimal values. For example, the letter "Z," which is 01011010 in binary, may be
displayed as 5A in hexadecimal code.
Assembler
Program used to convert or translate programs written in assembly code to machine code.
Some users may also refer to assembly language or assembler language as assembler.
An assembler is a program that converts assembly language into machine code. It takes the
basic commands and operations from assembly code and converts them into binary code that
can be recognized by a specific type of processor.
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Assemblers are similar to compilers in that they produce executable code. However,
assemblers are more simplistic since they only convert low-level code (assembly language) to
machine code. Since each assembly language is designed for a specific processor, assembling a
program is performed using a simple one-to-one mapping from assembly code to machine
code. Compilers, on the other hand, must convert generic high-level source code into machine
code for a specific processor.
Most programs are written in high-level programming languages and are compiled directly to
machine code using a compiler. However, in some cases, assembly code may be used to
customize functions and ensure they perform in a specific way. Therefore, IDEs often include
assemblers so they can build programs from both high and low-level languages.
How it works:
 Most computers come with a specified set of very basic instructions that correspond to
the basic machine operations that the computer can perform. For example, a "Load"
instruction causes the processor to move a string of bits from a location in the
processor's memory to a special holding place called a register. Assuming the processor
has at least eight registers, each numbered, the following instruction would move the
value (string of bits of a certain length) at memory location 3000 into the holding place
called register 8:
L 8,3000
 The programmer can write a program using a sequence of these assembler instructions.
 This sequence of assembler instructions, known as the source code or source program,
is then specified to the assembler program when that program is started.
 The assembler program takes each program statement in the source program and
generates a corresponding bit stream or pattern (a series of 0's and 1's of a given
length).
 The output of the assembler program is called the object code or object program
relative to the input source program. The sequence of 0's and 1's that constitute the
object program is sometimes called machine code.
 The object program can then be run (or executed) whenever desired.
In the earliest computers, programmers actually wrote programs in machine code, but
assembler languages or instruction sets were soon developed to speed up programming.
Today, assembler programming is used only where very efficient control over processor
operations is needed. It requires knowledge of a particular computer's instruction set,
however. Historically, most programs have been written in "higher-level" languages such as
COBOL, FORTRAN, PL/I, and C. These languages are easier to learn and faster to write
programs with than assembler language. The program that processes the source code written
in these languages is called a compiler. Like the assembler, a compiler takes higher-level
language statements and reduces them to machine code.
Program Loops
Loops are among the most basic and powerful of programming concepts. A loop in a computer
program is an instruction that repeats until a specified condition is reached. In a loop
structure, the loop asks a question. If the answer requires action, it is executed. The same
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question is asked again and again until no further action is required. Each time the question is
asked is called an iteration.
A computer programmer who needs to use the same lines of code many times in a program
can use a loop to save time.
Just about every programming language includes the concept of a loop. High-level programs
accommodate several types of loops. C, C++, and C# are all high-level computer programs and
have the capacity to use several types of loops.
Types of Loops
 A for loop is a loop that runs for a preset number of times.
 A while loop is a loop that is repeated as long as an expression is true. An expression is a
statement that has a value.
 A do while loop or repeat until loop repeats until an expression becomes false.
 An infinite or endless loop is a loop that repeats indefinitely because it has no
terminating condition, the exit condition is never met or the loop is instructed to start
over from the beginning. Although it is possible for a programmer to intentionally use
an infinite loop, they are often mistakes made by new programmers.
 A nested loop appears inside any other for, while or do while loop.
A goto statement can create a loop by jumping backward to a label, although this is generally
discouraged as a bad programming practice. For some complex code, it allows a jump to a
common exit point that simplifies the code.
Loop Control Statements
A statement that alters the execution of a loop from its designated sequence is a loop control
statement. C#, for example, provides two loop control statements.
 A break statement inside a loop terminates the loop immediately.
 A continue statement jumps to the next iteration of the loop, skipping any code in
between.
Basic Structures of Computer Programming
Loop, selection, and sequence are the three basic structures of computer programming. These
three logic structures are used in combination to form algorithms for solving any logic
problem. This process is called structured programming.
Subroutine
A set of Instructions which are used repeatedly in a program can be referred to as Subroutine.
Only one copy of this Instruction is stored in the memory. When a Subroutine is required it can
be called many times during the Execution of a Particular program. A call Subroutine
Instruction calls the Subroutine. Care Should be taken while returning a Subroutine as
Subroutine can be called from a different place from the memory.
The content of the PC must be Saved by the call Subroutine Instruction to make a correct
return to the calling program.

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Figure – Process of subroutine in a program

Subroutine linkage method is a way in which computer call and return the Subroutine. The
simplest way of Subroutine linkage is saving the return address in a specific location, such as
register which can be called as link register call Subroutine.
2. Subroutine Nesting –
Subroutine nesting is a common Programming practice In which one Subroutine call another
Subroutine.

Figure – Subroutine calling another subroutine

From the above figure, assume that when Subroutine 1 calls Subroutine 2 the return address
of Subroutine 2 should be saved somewhere. So if link register stores return address of
Subroutine 1 this will be (destroyed/overwritten) by return address of Subroutine 2. As the last
Subroutine called is the first one to be returned ( Last in first out format). So stack data
structure is the most efficient way to store the return addresses of the Subroutines.

Figure – Return address of subroutine is stored in stack memory

3. Stack memory –
Stack is a basic data structure which can be implemented anywhere in the memory. It can be
used to store variables which may be required afterwards in the program Execution. In a stack,
the first data put will be last to get out of a stack. So the last data added will be the First one to
come out of the stack (last in first out).
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Figure – Stack memory having data A, B & C

So from the diagram above first A is added then B & C. While removing first C is Removed then
B & A.
Design of Control Unit
The Control Unit is classified into two major categories:
1. Hardwired Control
2. Microprogrammed Control
Hardwired Control Unit:
When the control signals are generated by hardware using conventional logic design
techniques, the control unit is said to be hardwired.
The Hardwired Control organization involves the control logic to be implemented with gates,
flip-flops, decoders, and other digital circuits.
The following image shows the block diagram of a Hardwired Control organization.

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 A Hard-wired Control consists of two decoders, a sequence counter, and a number of

logic gates.
 An instruction fetched from the memory unit is placed in the instruction register (IR).
 The component of an instruction register includes; I bit, the operation code, and bits
0 through 11.
 The operation code in bits 12 through 14 are coded with a 3 x 8 decoder.
 The outputs of the decoder are designated by the symbols D0 through D7.
 The operation code at bit 15 is transferred to a flip-flop designated by the symbol I.
 The operation codes from Bits 0 through 11 are applied to the control logic gates.
 The Sequence counter (SC) can count in binary from 0 through 15.
Micro-programmed Control
The Microprogrammed Control organization is implemented by using the programming
approach.

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In Microprogrammed Control, the micro-operations are performed by executing a program
consisting of micro-instructions.
The following image shows the block diagram of a Microprogrammed Control organization.

 The Control memory address register specifies the address of the micro-instruction.
 The Control memory is assumed to be a ROM, within which all control information is
permanently stored.
 The control register holds the microinstruction fetched from the memory.
 The micro-instruction contains a control word that specifies one or more micro-
operations for the data processor.
 While the micro-operations are being executed, the next address is computed in the
next address generator circuit and then transferred into the control address register
to read the next microinstruction.
 The next address generator is often referred to as a micro-program sequencer, as it
determines the address sequence that is read from control memory.
Difference between Hardwired Control and Microprogrammed Control
Hardwired Control Microprogrammed Control
Technology is circuit based. Technology is software based.
It is implemented through flip-flops, Microinstructions generate signals to control the
gates, decoders etc. execution of instructions.
Variable instruction format (16-64 bits per
Fixed instruction format.
instruction).
Instructions are register based. Instructions are not register based.
ROM is not used. ROM is used.
It is used in RISC. It is used in CISC.
Faster decoding. Slower decoding.
Difficult to modify. Easily modified.
Chip area is less. Chip area is large.
Dynamic microprogramming:
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A more advanced development known as dynamic microprogramming permits a
microprogram to be loaded initially from an auxiliary memory such as a magnetic disk. Control
units that use dynamic microprogramming employ a writable control memory. This type of
memory can be used for writing.
Control Memory:
Control Memory is the storage in the microprogrammed control unit to store the
microprogram.
Writeable Control Memory:
Control Storage whose contents can be modified, allow the change in microprogram and
Instruction set can be changed or modified is referred as Writeable Control Memory.
Control Word:
The control variables at any given time can be represented by a control word string of 1 's and
0's called a control word.
Microoperation, Microinstruction, Micro program, Microcode.
Microoperations:
In computer central processing units, micro-operations (also known as a micro-ops or μops)
are detailed low-level instructions used in some designs to implement complex machine
instructions (sometimes termed macro-instructions in this context).
Micro instruction:
 A symbolic microprogram can be translated into its binary equivalent by means of an
assembler.
 Each line of the assembly language microprogram defines a symbolic microinstruction.
 Each symbolic microinstruction is divided into five fields: label, microoperations, CD, BR,
and AD.
Micro program:
 A sequence of microinstructions constitutes a microprogram.
 Since alterations of the microprogram are not needed once the control unit
is in operation, the control memory can be a read-only memory (ROM).
 ROM words are made permanent during the hardware production of the
unit.
 The use of a micro program involves placing all control variables in words of
ROM for use by the control unit through successive read operations.
 The content of the word in ROM at a given address specifies a
microinstruction.
Microcode:
 Microinstructions can be saved by employing subroutines that use common
sections of microcode.
 For example, the sequence of micro operations needed to generate the
effective address of the operand for an instruction is common to all
memory reference instructions.
 This sequence could be a subroutine that is called from within many other
routines to execute the effective address computation.
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Organization of micro programmed control unit
 The general configuration of a micro-programmed control unit is demonstrated in the
block diagram of Figure 4.1.
 The control memory is assumed to be a ROM, within which all control information is
permanently stored.

figure: Micro-programmed control organization

 The control memory address register specifies the address of the microinstruction, and
the control data register holds the microinstruction read from memory.
 The microinstruction contains a control word that specifies one or more
microoperations for the data processor. Once these operations are executed, the
control must determine the next address.
 The location of the next microinstruction may be the one next in sequence, or it may be
located somewhere else in the control memory.
 While the microoperations are being executed, the next address is computed in the next
address generator circuit and then transferred into the control address register to read
the next microinstruction.
 Thus a microinstruction contains bits for initiating microoperations in the data processor
part and bits that determine the address sequence for the control memory.
 The next address generator is sometimes called a micro-program sequencer, as it
determines the address sequence that is read from control memory.
 Typical functions of a micro-program sequencer are incrementing the control address
register by one, loading into the control address register an address from control
memory, transferring an external address, or loading an initial address to start the
control operations.
 The control data register holds the present microinstruction while the next address is
computed and read from memory.
 The data register is sometimes called a pipeline register.
 It allows the execution of the microoperations specified by the control word
simultaneously with the generation of the next microinstruction.
 This configuration requires a two-phase clock, with one clock applied to the address
register and the other to the data register.

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 The main advantage of the micro programmed control is the fact that once the
hardware configuration is established; there should be no need for further hardware or
wiring changes.
 If we want to establish a different control sequence for the system, all we need to do is
specify a different set of microinstructions for control memory.
Address Sequencing
Microinstructions are stored in control memory in groups, with each group specifying a
routine.
To appreciate the address sequencing in a micro-program control unit, specify the steps that
the control must undergo during the execution of a single computer instruction.
Step-1:
 An initial address is loaded into the control address register when power is turned on in
the computer.
 This address is usually the address of the first microinstruction that activates the
instruction fetch routine.
 The fetch routine may be sequenced by incrementing the control address register
through the rest of its microinstructions.
 At the end of the fetch routine, the instruction is in the instruction register of the
computer.
Step-2:
 The control memory next must go through the routine that determines the effective
address of the operand.
 A machine instruction may have bits that specify various addressing modes, such as
indirect address and index registers.
 The effective address computation routine in control memory can be reached through a
branch microinstruction, which is conditioned on the status of the mode bits of the
instruction.
 When the effective address computation routine is completed, the address of the
operand is available in the memory address register.
Step-3:
 The next step is to generate the microoperations that execute the instruction fetched
from memory.
 The microoperation steps to be generated in processor registers depend on the
operation code part of the instruction.
 Each instruction has its own micro-program routine stored in a given location of control
memory.
 The transformation from the instruction code bits to an address in control memory
where the routine is located is referred to as a mapping process.
 A mapping procedure is a rule that transforms the instruction code into a control
memory address.
Step-4:

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 Once the required routine is reached, the microinstructions that execute
the instruction may be sequenced by incrementing the control address
register.
 Micro-programs that employ subroutines will require an external register
for storing the return address.
 Return addresses cannot be stored in ROM because the unit has no writing
capability.
 When the execution of the instruction is completed, control must return to
the fetch routine.
 This is accomplished by executing an unconditional branch microinstruction
to the first address of the fetch routine.

In summary, the address sequencing capabilities required in a control memory are:

1. Incrementing of the control address register.
2. Unconditional branch or conditional branch, depending on status bit
conditions.
3. A mapping process from the bits of the instruction to an address for control
memory.
4. A facility for subroutine call and return.
Selection of address for control memory

Figure 4.2: Selection of address for control memory

 Above figure 4.2 shows a block diagram of a control memory and the associated
hardware needed for selecting the next microinstruction address.

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 The microinstruction in control memory contains a set of bits to initiate microoperations
in computer registers and other bits to specify the method by which the next address is
obtained.
 The diagram shows four different paths from which the control address register (CAR)
receives the address.
 The incrementer increments the content of the control address register by one, to select
the next microinstruction in sequence.
 Branching is achieved by specifying the branch address in one of the fields of the
microinstruction.
 Conditional branching is obtained by using part of the microinstruction to select a
specific status bit in order to determine its condition.
 An external address is transferred into control memory via a mapping logic circuit.
 The return address for a subroutine is stored in a special register whose value is then
used when the micro-program wishes to return from the subroutine.
Central Processing Unit (CPU)
The central processing unit (CPU) or processor, is the unit which performs most of the
processing inside a computer. It processes all instructions received by software running on the
PC and by other hardware components, and acts as a powerful calculator.
The CPU is placed into a specific square-shaped socket found on all motherboards by inserting
its metallic connectors or pins found on the underside. Each socket is built with a specific pin
layout to support only a specific type of processor.
Since modern CPUs produce a lot of heat and are prone to overheating, they must be kept
cool with appropriate fans or ventilation systems, and covered with heat sinks and thermal
paste.
To control instructions and data flow to and from other parts of the computer, the CPU relies
heavily on a chipset, which is a group of microchips located on the motherboard.
This term is also known as a central processor, microprocessor or chip
The central processing unit (CPU) has three components:

Control Unit
The control unit extracts instructions from memory and decodes and executes them.
The control unit acts as an intermediary that decodes the instructions sent to the processor,
tells the other units such as the Arithmetic Logic Unit (below) what to do by providing control
signals, and then sends back the processed data back to memory.
Arithmetic Logic Unit (ALU)
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An arithmetic logic unit (ALU) is a digital circuit inside the processor that handles arithmetic
and logical operations by loading data from input registers.
After the control unit provides the ALU with the instruction on the operations that must be
performed, the ALU completes them by connecting multiple transistors, and then stores the
results in an output register.
The control unit will then move this data to memory.
To function properly, the CPU relies on the system clock, memory, secondary storage, and
data and address buses.
Smaller devices like mobile phones, calculators, held gaming systems, and tablets use smaller-
sized processors known as ARM CPUs to accommodate their reduced size and space.
The CPU is the heart and brain of a computer. It receives data input, executes instructions, and
processes information. It communicates with input/output (I/O) devices, which send and
receive data to and from the CPU.
Additionally, the microprocessor has an internal bus for communication with the internal
cache memory, called the backside bus. The main bus for data transfer to and from the CPU,
memory, chipset, and AGP socket is called the front-side bus.
The CPU contains internal memory units, which are called registers. These registers contain
data, instructions, counters and addresses used in the ALU's information processing.
Some computers utilize two or more processors. These consist of separate physical
microprocessors located side by side on the same board or on separate boards. Each CPU has
an independent interface, separate cache, and individual paths to the system front-side bus.
Multiple processors are ideal for intensive parallel tasks requiring multitasking. Multicore CPUs
are also common, in which a single chip contains multiple CPUs.
Since the first microprocessor was released by Intel in November 1971, CPUs have increased
their computing power severalfold.
The oldest Intel 4004 processor only performed 60,000 operations per second, while a modern
Intel Pentium processor can perform about 188,000,000 instructions per second.
Memory or Storage Unit/ Registers
It is called Random access memory (RAM). It temporarily stores data, programs, and
intermediate and final results of processing. So, it acts as a temporary storage area that holds
the data temporarily, which is used to run the computer.
CPU Clock Speed
The clock speed of a CPU or a processor refers to the number of instructions it can process in a
second. It is measured in gigahertz. For example, a CPU with a clock speed of 4.0 GHz means it
can process 4 billion instructions in a second.
Types of CPU:
CPUs are mostly manufactured by Intel and AMD, each of which manufactures its own types of
CPUs. In modern times, there are lots of CPU types in the market. Some of the basic types of
CPUs are described below:
Single Core CPU: Single Core is the oldest type of computer CPU, which was used in the 1970s.
It has only one core to process different operations. It can start only one operation at a time;

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the CPU switches back and forth between different sets of data streams when more than one
program runs. So, it is not suitable for multitasking as the performance will be reduced if more
than one application runs. The performance of these CPUs is mainly dependent on the clock
speed. It is still used in various devices, such as smartphones.
Dual Core CPU: As the name suggests, Dual Core CPU contains two cores in a single Integrated
Circuit (IC). Although each core has its own controller and cache, they are linked together to
work as a single unit and thus can perform faster than the single-core processors and can
handle multitasking more efficiently than Single Core processors.
Quad Core CPU: This type of CPU comes with two dual-core processors in one integrated
circuit (IC) or chip. So, a quad-core processor is a chip that contains four independent units
called cores. These cores read and execute instructions of CPU. The cores can run multiple
instructions simultaneously, thereby increases the overall speed for programs that are
compatible with parallel processing.
Quad Core CPU uses a technology that allows four independent processing units (cores) to run
in parallel on a single chip. Thus by integrating multiple cores in a single CPU, higher
performance can be generated without boosting the clock speed. However, the performance
increases only when the computer's software supports multiprocessing. The software which
supports multiprocessing divides the processing load between multiple processors instead of
using one processor at a time.
History of CPU:
Some of the important events in the development of CPU since its invention till date are as
follows:
 In 1823, Baron Jons Jackob Berzelius discovered silicon that is the main component
of CPU till date.
 In 1903, Nikola Tesla got gates or switches patented, which are electrical logic
circuits.
 In December 1947, John Bardeen, William Shockley, and Walter Brattain invented
the first transistor at the Bell Laboratories and got it patented in 1948.
 In 1958, the first working integrated circuit was developed by Robert Noyce and Jack
Kilby.
 In 1960, IBM established the first mass-production facility for transistors in New
York.
 In 1968, Robert Noyce and Gordon Moore founded Intel Corporation.
 AMD (Advanced Micro Devices) was founded in May 1969.
 In 1971, Intel introduced the first microprocessor, the Intel 4004, with the help of
Ted Hoff.
 In 1972, Intel introduced the 8008 processor; in 1976, Intel 8086 was introduced, and
in June 1979, Intel 8088 was released.
 In 1979, a 16/32-bit processor, the Motorola 68000, was released. Later, it was used
as a processor for the Apple Macintosh and Amiga computers.
 In 1987, Sun introduced the SPARC processor.
 In March 1991, AMD introduced the AM386 microprocessor family.

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 In March 1993, Intel released the Pentium processor. In 1995, Cyrix introduced the
Cx5x86 processor to give competition to Intel Pentium processors.
 In January 1999, Intel introduced the Celeron 366 MHz and 400 MHz processors.
 In April 2005, AMD introduced its first dual-core processor.
 In 2006, Intel introduced the Core 2 Duo processor.
 In 2007, Intel introduced different types of Core 2 Quad processors.
 In April 2008, Intel introduced the first series of Intel Atom processors, the Z5xx
series. They were single-core processors with a 200 MHz GPU.
 In September 2009, Intel released the first Core i5 desktop processor with four cores.
 In January 2010, Intel released many processors such as Core 2 Quad processor
Q9500, first Core i3 and i5 mobile processors, first Core i3 and i5 desktop processors.
In the same year in July, it released the first Core i7 desktop processor with six cores.
 In June 2017, Intel introduced the first Core i9 desktop processor.
 In April 2018, Intel released the first Core i9 mobile processor.
General Register based CPU Organization
When we are using multiple general purpose registers, instead of single accumulator register,
in the CPU Organization then this type of organization is known as General register based CPU
Organization. In this type of organization, computer uses two or three address fields in their
instruction format. Each address field may specify a general register or a memory [Link]
many CPU registers are available for heavily used variables and intermediate results, we can
avoid memory references much of the time, thus vastly increasing program execution speed,
and reducing program size.
For example:
MULT R1, R2, R3
This is an instruction of an arithmatic multiplication written in assembly language. It uses three
address fields R1, R2 and R3. The meaning of this instruction is:
R1 <-- R2 * R3
This instruction also can be written using only two address fields as:
MULT R1, R2
In this instruction, the destination register is the same as one of the source registers. This
means the operation
R1 <-- R1 * R2
The use of large number of registers results in short program with limited instructions.
Some examples of General register based CPU Organization are IBM 360 and PDP- 11.
The advantages of General register based CPU organization –
 Efficiency of CPU increases as there are large number of registers are used in this
organization.
 Less memory space is used to store the program since the instructions are written in
compact way.
The disadvantages of General register based CPU organization –
 Care should be taken to avoid unnecessary usage of registers. Thus, compilers need
to be more intelligent in this aspect.
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 Since large number of registers are used, thus extra cost is required in this
organization.
General register CPU organisation of two type:
1. Register-memory reference architecture (CPU with less register)– In this organisation
Source 1 is always required in register, source 2 can be present either in register or in
[Link] two address instruction format is the compatible instruction format.
2. Register-register reference architecture(CPU with more register)– In this organisation
ALU operations are performed only on a register data. So operands are required in
the register. After manipulation result is also placed in [Link] three address
instruction format is the compatible instruction format.
Stack based CPU Organization
The computers which use Stack-based CPU Organization are based on a data structure
called stack. The stack is a list of data words. It uses Last In First Out (LIFO) access method
which is the most popular access method in most of the CPU. A register is used to store the
address of the topmost element of the stack which is known as Stack pointer (SP). In this
organisation, ALU operations are performed on stack data. It means both the operands are
always required on the stack. After manipulation, the result is placed in the stack.
The main two operations that are performed on the operators of the stack are Push and Pop.
These two operations are performed from one end only.
1. Push –
This operation results in inserting one operand at the top of the stack and it decrease
the stack pointer register. The format of the PUSH instruction is:
PUSH
It inserts the data word at specified address to the top of the stack. It can be implemented as:
//decrement SP by 1
SP <-- SP - 1
//store the content of specified memory address
//into SP; i.e, at top of stack
SP <-- (memory address)
2. Pop –
This operation results in deleting one operand from the top of the stack and it increase
the stack pointer register. The format of the POP instruction is:
POP
It deletes the data word at the top of the stack to the specified address. It can be implemented
as:
//transfer the content of SP (i.e, at top most data)
//into specified memory location
(memory address) <-- SP
//increment SP by 1
SP <-- SP + 1

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Operation type instruction does not need the address field in this CPU organization. This is
because the operation is performed on the two operands that are on the top of the stack. For
example:
SUB
This instruction contains the opcode only with no address field. It pops the two top data from
the stack, subtracting the data, and pushing the result into the stack at the top.
PDP-11, Intel’s 8085 and HP 3000 are some of the examples of the stack organized computers.
The advantages of Stack based CPU organization –
 Efficient computation of complex arithmetic expressions.
 Execution of instructions is fast because operand data are stored in consecutive
memory locations.
 Length of instruction is short as they do not have address field.
The disadvantages of Stack based CPU organization –
 The size of the program increases.
Note:Stack based CPU organisation uses zero address instruction.
Computer Instructions
The basic computer has three instruction code formats. The Operation code (opcode) part of
the instruction contains 3 bits and remaining 13 bits depends upon the operation code
encountered.
There are three types of formats:
1. Memory Reference Instruction
It uses 12 bits to specify the address and 1 bit to specify the addressing mode (I). I is equal
to 0 for direct address and 1 for indirect address.
2. Register Reference Instruction
These instructions are recognized by the opcode 111 with a 0 in the left most bit of instruction.
The other 12 bits specify the operation to be executed.
3. Input-Output Instruction
These instructions are recognized by the operation code 111 with a 1 in the left most bit of
instruction. The remaining 12 bits are used to specify the input-output operation.
Format of Instruction
The format of an instruction is depicted in a rectangular box symbolizing the bits of an
instruction. Basic fields of an instruction format are given below:
4. An operation code field that specifies the operation to be performed.
5. An address field that designates the memory address or register.
6. A mode field that specifies the way the operand of effective address is determined.
Computers may have instructions of different lengths containing varying number of addresses.
The number of address field in the instruction format depends upon the internal organization
of its registers.
Adressing Modes

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The operation field of an instruction specifies the operation to be performed. This operation
will be executed on some data which is stored in computer registers or the main memory. The
way any operand is selected during the program execution is dependent on the addressing
mode of the instruction. The purpose of using addressing modes is as follows:
3. To give the programming versatility to the user.
4. To reduce the number of bits in addressing field of instruction.
Types of Addressing Modes
Below we have discussed different types of addressing modes one by one:
Immediate Mode
In this mode, the operand is specified in the instruction itself. An immediate mode instruction
has an operand field rather than the address field.
For example: ADD 7, which says Add 7 to contents of accumulator. 7 is the operand here.
Register Mode
In this mode the operand is stored in the register and this register is present in CPU. The
instruction has the address of the Register where the operand is stored.

Advantages
 Shorter instructions and faster instruction fetch.
 Faster memory access to the operand(s)
Disadvantages
 Very limited address space
 Using multiple registers helps performance but it complicates the instructions.
Register Indirect Mode
In this mode, the instruction specifies the register whose contents give us the address of
operand which is in memory. Thus, the register contains the address of operand rather than
the operand itself.

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Auto Increment/Decrement Mode

In this the register is incremented or decremented after or before its value is used.
Direct Addressing Mode
In this mode, effective address of operand is present in instruction itself.
 Single memory reference to access data.
 No additional calculations to find the effective address of the operand.

For Example: ADD R1, 4000 - In this the 4000 is effective address of operand.
NOTE: Effective Address is the location where operand is present.
Indirect Addressing Mode
In this, the address field of instruction gives the address where the effective address is stored
in memory. This slows down the execution, as this includes multiple memory lookups to find
the operand.

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Displacement Addressing Mode

In this the contents of the indexed register is added to the Address part of the instruction, to
obtain the effective address of operand.
EA = A + (R), In this the address field holds two values, A(which is the base value) and R(that
holds the displacement), or vice versa.

Relative Addressing Mode

It is a version of Displacement addressing mode.
In this the contents of PC(Program Counter) is added to address part of instruction to obtain
the effective address.
EA = A + (PC), where EA is effective address and PC is program counter.
The operand is A cells away from the current cell(the one pointed to by PC)
Base Register Addressing Mode
It is again a version of Displacement addressing mode. This can be defined as EA = A + (R),
where A is displacement and R holds pointer to base address.
Stack Addressing Mode
In this mode, operand is at the top of the stack. For example: ADD, this instruction will POP top
two items from the stack, add them, and will then PUSH the result to the top of the stack.
RISC Processor
It is known as Reduced Instruction Set Computer. It is a type of microprocessor that has a
limited number of instructions. They can execute their instructions very fast because
instructions are very small and simple.

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RISC chips require fewer transistors which make them cheaper to design and produce. In RISC,
the instruction set contains simple and basic instructions from which more complex instruction
can be produced. Most instructions complete in one cycle, which allows the processor to
handle many instructions at same time.
In this instructions are register based and data transfer takes place from register to register.
CISC Processor
 It is known as Complex Instruction Set Computer.
 It was first developed by Intel.
 It contains large number of complex instructions.
 In this instructions are not register based.
 Instructions cannot be completed in one machine cycle.
 Data transfer is from memory to memory.
 Micro programmed control unit is found in CISC.
 Also they have variable instruction formats.
SIMD Array Processors
SIMD is the organization of a single computer containing multiple processors operating in
parallel. The processing units are made to operate under the control of a common control
unit, thus providing a single instruction stream and multiple data streams.
A general block diagram of an array processor is shown below. It contains a set of identical
processing elements (PE's), each of which is having a local memory M. Each processor element
includes an ALU and registers. The master control unit controls all the operations of the
processor elements. It also decodes the instructions and determines how the instruction is to
be executed.
The main memory is used for storing the program. The control unit is responsible for fetching
the instructions. Vector instructions are send to all PE's simultaneously and results are
returned to the memory.
The best known SIMD array processor is the ILLIAC IV computer developed by the Burroughs
corps. SIMD processors are highly specialized computers. They are only suitable for numerical
problems that can be expressed in vector or matrix form and they are not suitable for other
types of computations.

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Why use the Array Processor

 Array processors increases the overall instruction processing speed.
 As most of the Array processors operates asynchronously from the host CPU, hence
it improves the overall capacity of the system.
 Array Processors has its own local memory, hence providing extra memory for
systems with low memory.
Input/Output Organisation
Input/Output Subsystem
The I/O subsystem of a computer provides an efficient mode of communication between the
central system and the outside environment. It handles all the input-output operations of the
computer system.
Peripheral Devices
Input or output devices that are connected to computer are called peripheral devices. These
devices are designed to read information into or out of the memory unit upon command from
the CPU and are considered to be the part of computer system. These devices are also
called peripherals.
For example: Keyboards, display units and printers are common peripheral devices.
There are three types of peripherals:
1. Input peripherals : Allows user input, from the outside world to the computer. Example:
Keyboard, Mouse etc.
2. Output peripherals: Allows information output, from the computer to the outside
world. Example: Printer, Monitor etc
3. Input-Output peripherals: Allows both input(from outised world to computer) as well
as, output(from computer to the outside world). Example: Touch screen etc.
Interfaces

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Interface is a shared boundary btween two separate components of the computer system
which can be used to attach two or more components to the system for communication
purposes.
There are two types of interface:
1. CPU Inteface
2. I/O Interface
Input-Output Interface
Peripherals connected to a computer need special communication links for interfacing with
CPU. In computer system, there are special hardware components between the CPU and
peripherals to control or manage the input-output transfers. These components are
called input-output interface units because they provide communication links between
processor bus and peripherals. They provide a method for transferring information between
internal system and input-output devices.
Modes of I/O Data Transfer
Data transfer between the central unit and I/O devices can be handled in generally three types
of modes which are given below:
1. Programmed I/O
2. Interrupt Initiated I/O
3. Direct Memory Access
Programmed I/O
Programmed I/O instructions are the result of I/O instructions written in computer program.
Each data item transfer is initiated by the instruction in the program.
Usually the program controls data transfer to and from CPU and peripheral. Transferring data
under programmed I/O requires constant monitoring of the peripherals by the CPU.
Interrupt Initiated I/O
In the programmed I/O method the CPU stays in the program loop until the I/O unit indicates
that it is ready for data transfer. This is time consuming process because it keeps the processor
busy needlessly.
This problem can be overcome by using interrupt initiated I/O. In this when the interface
determines that the peripheral is ready for data transfer, it generates an interrupt. After
receiving the interrupt signal, the CPU stops the task which it is processing and service the I/O
transfer and then returns back to its previous processing task.
Direct Memory Access
Removing the CPU from the path and letting the peripheral device manage the memory buses
directly would improve the speed of transfer. This technique is known as DMA.
In this, the interface transfer data to and from the memory through memory bus. A DMA
controller manages to transfer data between peripherals and memory unit.
Many hardware systems use DMA such as disk drive controllers, graphic cards, network cards
and sound cards etc. It is also used for intra chip data transfer in multicore processors. In DMA,
CPU would initiate the transfer, do other operations while the transfer is in progress and
receive an interrupt from the DMA controller when the transfer has been completed.

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Above figure shows block diagram of DMA

Input/Output Processor
An input-output processor (IOP) is a processor with direct memory access capability. In this,
the computer system is divided into a memory unit and number of processors.
Each IOP controls and manage the input-output tasks. The IOP is similar to CPU except that it
handles only the details of I/O processing. The IOP can fetch and execute its own instructions.
These IOP instructions are designed to manage I/O transfers only.
Block Diagram Of I/O Processor
Below is a block diagram of a computer along with various I/O Processors. The memory unit
occupies the central position and can communicate with each processor.
The CPU processes the data required for solving the computational tasks. The IOP provides a
path for transfer of data between peripherals and memory. The CPU assigns the task of
initiating the I/O program.
The IOP operates independent from CPU and transfer data between peripherals and memory.

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The communication between the IOP and the devices is similar to the program control method
of transfer. And the communication with the memory is similar to the direct memory access
method.
In large scale computers, each processor is independent of other processors and any processor
can initiate the operation.
The CPU can act as master and the IOP act as slave processor. The CPU assigns the task of
initiating operations but it is the IOP, who executes the instructions, and not the CPU. CPU
instructions provide operations to start an I/O transfer. The IOP asks for CPU through
interrupt.
Instructions that are read from memory by an IOP are also called commands to distinguish
them from instructions that are read by CPU. Commands are prepared by programmers and
are stored in memory. Command words make the program for IOP. CPU informs the IOP
where to find the commands in memory.
Memory Mapping and Concept of Virtual Memory
The transformation of data from main memory to cache memory is called mapping. There are
3 main types of mapping:
 Associative Mapping
 Direct Mapping
 Set Associative Mapping
Associative Mapping
The associative memory stores both address and data. The address value of 15 bits is 5 digit
octal numbers and data is of 12 bits word in 4 digit octal number. A CPU address of 15 bits is
placed in argument register and the associative memory is searched for matching address.

Direct Mapping
The CPU address of 15 bits is divided into 2 fields. In this the 9 least significant bits constitute
the index field and the remaining 6 bits constitute the tag field. The number of bits in index
field is equal to the number of address bits required to access cache memory.

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Set Associative Mapping

The disadvantage of direct mapping is that two words with same index address can't reside in
cache memory at the same time. This problem can be overcome by set associative mapping.
In this we can store two or more words of memory under the same index address. Each data
word is stored together with its tag and this forms a set.

Replacement Algorithms
Data is continuously replaced with new data in the cache memory using replacement
algorithms. Following are the 2 replacement algorithms used:
 FIFO - First in First out. Oldest item is replaced with the latest item.
 LRU - Least Recently Used. Item which is least recently used by CPU is removed.
Virtual Memory
Virtual memory is the separation of logical memory from physical memory. This separation
provides large virtual memory for programmers when only small physical memory is available.
Virtual memory is used to give programmers the illusion that they have a very large memory
even though the computer has a small main memory. It makes the task of programming easier
because the programmer no longer needs to worry about the amount of physical memory
available.

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Memory Management Unit (MMU)
A computer’s memory management unit (MMU) is the physical hardware that handles its
virtual memory and caching operations. The MMU is usually located within the computer’s
central processing unit (CPU), but sometimes operates in a separate integrated chip (IC). All
data request inputs are sent to the MMU, which in turn determines whether the data needs to
be retrieved from RAM or ROM storage.
A memory management unit is also known as a paged memory management unit.
The memory management unit performs three major functions:
 Hardware memory management
 Operating system (OS) memory management
 Application memory management
Hardware memory management deals with a system's RAM and cache memory, OS memory
management regulates resources among objects and data structures, and application memory
management allocates and optimizes memory among programs.
The MMU also includes a section of memory that holds a table that matches virtual addresses
to physical addresses, called the translation lookaside buffer (TLB).
Multiprocessor
A Multiprocessor is a computer system with two or more central processing units (CPUs) share
full access to a common RAM. The main objective of using a multiprocessor is to boost the
system’s execution speed, with other objectives being fault tolerance and application
matching.
There are two types of multiprocessors, one is called shared memory multiprocessor and
another is distributed memory multiprocessor. In shared memory multiprocessors, all the
CPUs shares the common memory but in a distributed memory multiprocessor, every CPU has
its own private memory.

Applications of Multiprocessor –
1. As a uniprocessor, such as single instruction, single data stream (SISD).
2. As a multiprocessor, such as single instruction, multiple data stream (SIMD), which is
usually used for vector processing.
3. Multiple series of instructions in a single perspective, such as multiple instruction,
single data stream (MISD), which is used for describing hyper-threading or pipelined
processors.
4. Inside a single system for executing multiple, individual series of instructions in
multiple perspectives, such as multiple instruction, multiple data stream (MIMD).
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Benefits of using a Multiprocessor –
 Enhanced performance.
 Multiple applications.
 Multi-tasking inside an application.
 High throughput and responsiveness.
 Hardware sharing among CPUs.
Characteristics of multiprocessor
A multiprocessor system has two or more CPUs. It is an interconnection of two or more CPUs
with memory and input-output equipment. The term “processor” in multiprocessor can mean
either a central processing unit (CPU) or an input-output processor (IOP). However, a system
with a single CPU and one or more lOPs is usually not included in the definition of a
multiprocessor system unless the IOP has computational facilities comparable to a CPU. As it is
most commonly defined, a multiprocessor system implies the existence of multiple CPUs,
although usually there will be one or more lOPs as well. As mentioned earlier multiprocessors
are classified as multiple instruction stream, multiple data stream (MIMD) systems.
There are some similarities between multiprocessor and multicomputer systems since both
support concurrent operations. However, there exists an important distinction between a
system with multiple computers and a system with multiple processors. Computers are
interconnected with each other by means of communication lines to form a computer
network. The network consists of several autonomous computers that may or may not
communicate with each other. A multiprocessor system is controlled by one operating system
that provides interaction between processors and all the components of the system cooperate
in the solution of a problem.
Multiprocessing improves the reliability of the system so that a failure or error in one part has
a limited effect on the rest of the system. If a fault cause one processor to fail, a second
processor can be assigned to perform the functions of the disabled processor. The system as a
whole can continue to function correctly with perhaps some loss in efficiency.
The benefit derived from a multiprocessor organization is an improved system performance.
The system derives its high performance from the fact that computations can proceed in
parallel in one of two ways.
1. Multiple independent jobs can be made to operate in parallel.
2. A single job can be partitioned into multiple parallel tasks.
An overall function can be partitioned into a number of tasks that each processor can handle
individually. System tasks may be allocated to special purpose processors whose design is
optimized to perform certain types of processing efficiently. An example is a computer system
where one processor performs the computations for an industrial process control while other
monitor and control the various parameters, such as temperature and flow rate.
Multiprocessors are classified by the way their memory is organized. A multiprocessor system
with common shared memory is classified as a shared-memory or tightly coupled
multiprocessor. This does not preclude each processor from having its own local memory. In
fact, most commercial tightly coupled multiprocessors provide a cache memory with each

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CPU. In addition, there is a global common memory that all CPUs can access. Information can
therefore be shared among the CPUs by placing it in the common global memory.
An alternative model of microprocessor is the distributed-memory or loosely coupled system.
Each processor element in a loosely coupled system has its own private local memory. The
processors are tied together by a switching scheme designed to route information from one
processor to another through a message-passing scheme. The processors relay program and
data to other processors in packets. A packet consists of an address, the data content, and
some error detection code. The packets are addressed to a specific processor or taken by the
first available processor, depending on the communication system used. Loosely coupled
systems are most efficient when the interaction between tasks is minimal, whereas tightly
coupled systems can tolerate a higher degree of interaction between tasks.
Interconnection Structures
CPUs, TOPs connect’ to input-output device, and a memory unit form a multiprocessor system,
they may be partitioned into a number of separate modules. The interconnection between the
components can have different physical configurations, depending on the number of transfer
paths that are available between the processors and memory in a shared memory system or
among the processing elements in a loosely coupled system. There are several physical forms
available for establishing an interconnection network. Some of these schemes are presented in
this section:
1. Time-shared common bus
2. Multiport memory
3. Crossbar switch
4. Multistage switching network
5. Hypercube system
Time Shared Common bus
A common-bus multiprocessor system consists of a number of processors connected through a
common path to a memory unit. A time-shared common bus for five processors is shown in
figure below. Only one processor can communicate with the memory or another processor at
any given time. Transfer operations are conducted by the processor that is in control of the
bus at the time. Any other processor wishing to initiate a transfer must first determine the
availability status of the bus, and only after the bus becomes available can the processor
address the destination unit to initiate the transfer. A command is issued to inform the
destination unit what operation is to be performed. The receiving unit recognizes its address in
the bus and responds to the control signals from the sender, after which the transfer is
initiated. The system may exhibit transfer conflicts since one common bus is shared by all
processors. These conflicts must be resolved by incorporating a bus controller that establishes
priorities among the requesting units.
A single common-bus system is restricted to one transfer at a time. This means that when one
processor is communicating with the memory, all other processors are either busy with
internal operations or must be idle waiting for the bus. As a consequence, the total overall
transfer rate within the system is limited by the speed of the single path. The processors in the
system can be kept busy more often through the implementation of two or more independent

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buses to permit multiple simultaneous bus transfers. However, this increases the system cost
and complexity.
Multiport Memory
A multiport memory system employs separate buses between each memory module and each
CPU. This is shown in figure below for four CPUs and four memory modules (MMs). Each
processor bus is connected to each memory module. A processor bus consists of the address,
data, and control lines required to communicate with memory. The memory module is said to
have four ports and each port accommodates one of the buses. The module must have
internal control logic to determine which port will have access to memory at any given time.
Memory access conflicts are resolved by assigning fixed priorities to each memory port. The
priority for memory access associated with each processor may be established by the physical
port position that its bus occupies in each module. Thus CPU1 will have priority over CPU2,
CPU2 will have priority over CPU3, and CPU4 will have the lowest priority. The advantage of
the multiport memory organization is the high transfer rate that can be achieved because of
the multiple paths between processors and memory. The disadvantage is that it requires
expensive memory control logic and a large number of cables and connectors. As a
consequence, this interconnection structure is usually appropriate for systems with a small
number of processors.
Crossbar Switch
The crossbar switch organization consists of a number of crosspoints that are placed at
intersections between processor buses and memory module paths. Figure below shows a
crossbar switch interconnection between four CPUs and four memory modules. The small
square in each crosspoint is a switch that determines the path from a processor to a memory
module. Each switch point has control logic to set up the transfer path between a processor
and memory. It examines the address that is placed in the bus to determine whether its
particular module is being addressed. It also resolves multiple requests for access to the same
memory module on a predetermined priority basis.
Multistage Switching network
The basic component of a multistage network is a two-input, two-output interchange switch.
There are control signals (not shown) associated with the switch that establish the
interconnection between the input and output terminals. The switch has the capability of
connecting input A to either of the outputs. Terminal B of the switch behaves in a similar
fashion. The switch also has the capability to arbitrate between conflicting requests. If inputs A
and B both request the same output terminal, only one of them will be connected; the other
will be blocked.
Hypercube Interconnection
The hypercube or binary n-cube multiprocessor structure is a loosely coupled system
composed of N = 2n processors interconnected in an n-dimensional binary cube. Each
processor forms a node of the cube. Although it is customary to refer to each node as having a
processor, in effect it contains not only a CPU but also local memory and I/O interface. Each
processor has direct communication paths to n other neighbor processors. These paths
correspond to the edges of the cube. There are 2n distinct n-bit binary addresses that can be

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assigned to the processors. Each processor address differs from that of each of its n neighbors
by exactly one bit position.
Interconnection Structures

System bus
The processor uses a multidrop, shared system bus to provide four-way glueless
multiprocessor system support. No additional bridges are needed for building up to a four-way
system. Systems with eight or more processors are designed through clusters of these nodes
using high-speed interconnects. Note that multidrop buses are a cost-effective way to build
high-performance four-way systems for commercial transaction processing and e-business
workloads. These workloads often have highly shared writeable data and demand high
throughput and low latency on transfers of modified data between caches of multiple

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processors. In a four-processor system, the transactionbased bus protocol allows up to 56
pending bus transactions (including 32 read transactions) on the bus at any given time. An
advanced MESI coherence protocol helps in reducing bus invalidation transactions and in
providing faster access to writeable data. The cache-to-cache transfer latency is further
improved by an enhanced defer mechanism, which permits efficient out-of-order data
transfers and out-of-order transaction completion on the bus. A deferred transaction on the
bus can be completed without reusing the address bus. This reduces data return latency for
deferred transactions and efficiently uses the address bus. This feature is critical for scalability
beyond four-processor systems. The 64-bit system bus uses a source-synchronous data
transfer to achieve 266-Mtransfers/ s, which enables a bandwidth of 2.1 Gbytes/s. The
combination of these features makes the Itanium processor system a scalable building block
for large multiprocessor systems.
Source Synchronous Mode
In source synchronous mode, the clock to data phase relationship at the input pins is
maintained at the clock and data ports of the IOE input register. This mode is recommended
for source synchronous data transfers. Data and clock signals at the IOE experience similar
buffer delays as long as the same I/O standard is used.
Interprocessor Arbitration
Computer systems contain a number of buses at various levels to facilitate the transfer of
information between components. The CPU contains a number of internal buses for
transferring information between processor registers and ALU. A memory bus consists of lines
for transferring data, address, and read/write information. An I/O bus is used to transfer
information to and from input and output devices. A bus that connects major components in a
multi-processor system, such as CPUs, lOPs, and memory, is called a system bus. The physical
circuits of a system bus are contained in a number of identical printed circuit boards. Each
board in the system belongs to a particular module. The board consists of circuits connected in
parallel through connectors. Each pin of each circuit connector is connected by a wire to the
corresponding pin of all other connectors in other boards. Thus any board can be plugged into
a slot in the back-pane that forms the system bus.
The processors in a shared memory multiprocessor system request access to common
memory or other common resources through the system bus. If n other processor is currently
utilizing the bus, the requesting processor may be granted access immediately. However, the
requesting processor must wait if another processor is currently utilizing the system bus.
Furthermore, other processors may request the system bus at the same time. Arbitration must
then be performed to resolve this multiple contention for the shared resources. The
arbitration logic would be part of the system bus controller placed between the local bus and
the system bus.
System Bus
A typical system bus consists of approximately 100 signal lines. These lines are divided into
three functional groups: data, address, and control. In addition, there are power distribution
lines that supply power to the components. For example, the IEEE standard 796 multibus
system has 16 data lines, 24 address lines, 26 control lines, and 20 power lines, for a total of 86
lines.
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The data lines provide a path for the transfer of data between processors and common
memory. The number of data lines is usually a multiple of 8, with 16 and 32 being most
common. The address lines are used to identify a memory address or any other source or
destination, such as input or output ports. The number of address lines determines the
maximum possible memory capacity in the system. For example, an address of 24 lines can
access up to 2″ (16 mega) words of memory. The data and address lines are terminated with
three-state buffers. The address buffers are unidirectional from processor to memory. The
data lines are bi- directional, allowing the transfer of data in either direction.
Data transfers over the system bus may be synchronous or asynchronous. In a synchronous
bus, each data item is transferred during a time slice known in advance to both source and
destination units; synchronization is achieved by driving both units from a common clock
source. An alternative procedure is to have separate clocks of approximately the same
frequency in each unit. Synchronization signals are transmitted periodically in order to keep all
clocks asynchronous bus in the system in step with each other. In an asynchronous bus, each
data item being transferred is accompanied by handshaking control signals to indicate when
the data are transferred from the source and received by the destination.
The control lines provide signals for controlling the information transfer between units. Timing
signals indicate the validity of data and address information. Command signals specify
operations to be performed. Typical control lines include transfer signals such as memory read
and write, acknowledge of a transfer, interrupt requests, bus control signals such as bus
request and bus grant, and signals for arbitration procedures.
Serial Arbitration Procedure
Arbitration procedures service all processor requests on the basis of established priorities. A
hardware bus priority resolving technique can be established by means of a serial or parallel
connection of the units requesting control the system bus. The serial priority resolving
technique is obtained from daisy-chain connection of bus arbitration circuits similar to the
priority interrupt logic.
The processors connected to the system bus are assigned priority according to their position
along the priority control line. The device closest to the priority line is assigned the highest
priority. When multiple devices concurrently request the use of the bus, the device with the
highest priority is granted access to it.
Parallel Arbitration Logic
The parallel bus arbitration technique uses an external priority encoder and decoder as shown
in figure below. Each bus arbiter in the parallel scheme has a bus request output line and a bus
acknowledge input line. Each arbiter enables the request line when its processor is requesting
access to the system bus. The processor takes control of the bus if its acknowledge input line is
enabled. The bus busy line provides an orderly transfer of control, as in the daisy-chaining
case.
Dynamic Arbitration Algorithms
The two bus arbitration procedures just described use a static priority algorithm since the
priority of each device is fixed by the way it is connected to the bus. In contrast, a dynamic
priority algorithm gives the system the capability for changing the priority of the devices while

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the system is in operation. We now discuss a few arbitration procedures that use dynamic
priority algorithms.
The time slice algorithm allocates a fixed-length time slice of bus time that is offered
sequentially to each processor, in round-robin fashion. The service given to each system
component with this scheme is independent of its location along the bus. No preference is
given to any particular device since each is allotted the same amount of time to communicate
with the bus.
In a bus system that uses polling, the bus-grant signal is replaced by a set of lines called poll
lines, which are connected to all units. These lines are used by the bus controller to define an
address for each device connected to the bus. The bus controller sequences through the
addresses in a prescribed manner. When a processor that requires access recognizes its
address, it activates the bus busy-line and then accesses the bus. After a number of bus cycles,
the polling process continues by choosing a different processor. The polling sequence is
normally programmable, and as a result, the selection priority can be altered under program
control.
The least recently used (LRU) algorithm gives the highest priority to the requesting device that
has not used the bus for the longest interval. The priorities are adjusted after a number of bus
cycles according to the LRU algorithm. With this procedure, no processor is favored over any
other since the priorities are dynamically changed to give every device an opportunity to
access the bus.
In the first-come, first-serve scheme, requests are served in the order received. To implement
this algorithm, the bus controller establishes a queue arranged according to the time that the
bus requests arrive. Each processor must wait for its turn to use the bus on a first-in, first-out
(FIFO) basis. The rotating daisy-chain procedure is a dynamic extension of the daisy-chain
algorithm. In this scheme there is no central bus controller, and the priority line is connected
from the priority-out of the last device back to the priority-in of the first device in a closed
loop. This is similar to the connections shown in figure for serial arbitration except that the PO
output of arbiter 4 is connected to the PI input of arbiter 1. Whichever device has access to the
bus serves as a bus controller for the following arbitration. Each arbiter priority for a given bus
cycle is determined by its position along the bus priority line from the arbiter whose processor
is currently controlling the bus. Once an arbiter releases the bus, it has the lowest priority.
Interprocessor Communication & Synchronization
The various processors in a multiprocessor system must be provided with a facility for
communicating with each other. A communication path can be established through common
input-output channels. In a shared memory multiprocessor system, the most common
procedure is to set aside a portion of memory that is accessible to all processors. The primary
use of the common memory is to act as a message center similar to a mailbox, where each
processor can leave messages for other processors and pick up messages intended for it.
The sending processor structures a request, a message, or a procedure, and places it in the
memory mailbox. Status bits residing in common memory are generally used to indicate the
condition of the mailbox, whether it has meaningful information, and for which processor it is
intended. The receiving processor can check the mailbox periodically to determine if there are
valid messages for it. The response time of this procedure can be time consuming since a
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processor will recognize a request only when polling messages. A more efficient procedure is
for the sending processor to alert the receiving processor directly by means of an interrupt
signal. This can be accomplished through a software-initiated interprocessor interrupt by
means of an instruction in the program of one processor which when executed produces an
external interrupt condition in a second processor. This alerts the interrupted processor of the
fact that a new message has been inserted by the interrupting processor. In addition to shared
memory, a multiprocessor system may have other shared resources. For example, a magnetic
disk storage unit connected to an IOP may be available to all CPUs. This provides a facility for
sharing of system programs stored in the disk.
To prevent conflicting use of shared resources by several processors there must be a provision
for assigning resources to processors. This task is given to the operating system. There are
three organizations that have been used in the design of operating system for multiprocessors:
master-slave configuration, separate operating system, and distributed operating system. In a
master-slave mode, one processor, designated the master, always executes the operating
system functions. The remaining processors, denoted as slaves, do not perform operating
system functions. If a slave processor needs an operating system service, it must request it by
interrupting the master and waiting until the current program can be interrupted. In the
separate operating system organization, each processor can execute the operating system
routines it needs. This organization is more suitable for loosely coupled systems where every
processor may have its own copy of the entire operating system. In the distributed operating
system organization, the operating system routines are distributed among the available
processors. However, each particular operating system function is assigned to only one
processor at a time. This type of organization is also referred to as a floating operating system
since the routines float from one processor to another and the execution of the routines may
be assigned to different processors at different times.
Inter Process Communication
Inter Process Communication (IPC) is a mechanism that involves communication of one
process with another process. This usually occurs only in one system.
Communication can be of two types −
 Between related processes initiating from only one process, such as parent and child
processes.
 Between unrelated processes, or two or more different processes.
Following are some important terms that we need to know before proceeding further on this
topic.
Pipes − Communication between two related processes. The mechanism is half duplex
meaning the first process communicates with the second process. To achieve a full duplex i.e.,
for the second process to communicate with the first process another pipe is required.
FIFO − Communication between two unrelated processes. FIFO is a full duplex, meaning the
first process can communicate with the second process and vice versa at the same time.
Message Queues − Communication between two or more processes with full duplex capacity.
The processes will communicate with each other by posting a message and retrieving it out of
the queue. Once retrieved, the message is no longer available in the queue.

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Shared Memory − Communication between two or more processes is achieved through a
shared piece of memory among all processes. The shared memory needs to be protected from
each other by synchronizing access to all the processes.
Semaphores − Semaphores are meant for synchronizing access to multiple processes. When
one process wants to access the memory (for reading or writing), it needs to be locked (or
protected) and released when the access is removed. This needs to be repeated by all the
processes to secure data.
Signals − Signal is a mechanism to communication between multiple processes by way of
signaling. This means a source process will send a signal (recognized by number) and the
destination process will handle it accordingly.
Note − Almost all the programs in this tutorial are based on system calls under Linux Operating
System (executed in Ubuntu).
Interprocessor Synchronization
The instruction set of a multiprocessor contains basic instructions that are used to implement
communication and synchronization between cooperating processes. Communication refers to
the exchange of data between different processes. For example, parameters passed to a
procedure in a different processor constitute interprocessor communication. Synchronization
refers to the special case where the data used to communicate between processors is control
information. Synchronization is needed to enforce the correct sequence of processes and to
ensure mutually exclusive access to shared writable data.
Multiprocessor systems usually include various mechanisms to deal with the synchronization
of resources. Low-level primitives are implemented directly by the hardware. These primitives
are the basic mechanisms that enforce mutual exclusion for more complex mechanisms
implemented in software. A number of hardware mechanisms for mutual exclusion have been
developed. One of the most popular methods is through the use of a binary semaphore.
Mutual Exclusion with a Semaphore
A binary variable called a semaphore is often used to indicate whether or not a processor is
executing a critical section. A semaphore is a software-controlled flag that is stored in a
memory location that all processors can access. When the semaphore is equal to 1, it means
that a processor is executing a critical program, so that the shared memory is not available to
other processors. When the semaphore is equal to 0, the shared memory is available to any
requesting processor. Processors that share the same memory segment agree by convention
not to use the memory segment unless the semaphore is equal to 0, indicating that memory is
available. They also agree to set the semaphore to 1 when they are executing a critical section
and to clear it to 0 when they are finished.
A semaphore can be initialized by means of a test and set instruction in conjunction with a
hardware lock mechanism. A hardware lock is a processor- generated signal that serves to
prevent other processors from using the system bus as long as the signal is active. The test-
and-set instruction tests and sets a semaphore and activates the lock mechanism during the
time that the instruction is being executed. This prevents other processors from changing the
semaphore between the time that the processor is testing it and the time that it is setting it.
Assume that the semaphore is a bit in the least significant position of a memory word whose

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address is symbolized by SEM. Let the mnemonic TSL designate the “test and set while locked”
operation. The instruction
TSL SEM
will be executed in two memory cycles (the first to read and the second to write) without
interference as follows:
R ← M[SEM] Test semaphore
M [SEM] ← 1 Set semaphore
The semaphore is tested by transferring its value to a processor register R and then it is set to
1. The value in R determines what to do next. If the processor finds that R = 1, it knows that
the semaphore was originally set (the fact that it is set again does not change the semaphore
value). That means another processor is executing a critical section, so the processor that
checked the semaphore does not access the shared memory. R = 0 means that the common
memory (or the shared resource that the semaphore represents) is available. The semaphore
is set to 1 to prevent other processors from accessing memory. The processor can now
execute the critical section. The last instruction in the program must clear location SEM to zero
to release the share resource to other processors.
Cache Coherence
We know that the primary advantage of cache is its ability to reduce the average access time
in uniprocessor systems. When the processor finds a word in cache during a read operation,
the main memory is not involved in the transfer. If the operation is to write, there are two
commonly used procedures to update memory. In the write-through policy, both cache and
main memory are updated with every write operation. In the write-back policy, only the cache
is updated and the location is marked so that it can be copied later into main memory. In a
shared memory multiprocessor system, all the processors share a common memory. In
addition, each processor may have a local memory, part or all of which may be a cache. The
compelling reason for having separate caches for each processor is to reduce the average
access time in each processor .The same information may reside in a number of copies in
some caches and main memory. To ensure the ability of the system to execute memory
operations correctly, the multiple copies must be kept identical. This requirement imposes a
cache coherence problem. A memory scheme is coherent if the value returned on a load
instruction is always the value given by the latest store instruction with the same address.
Without a proper solution to the cache coherence problem, caching cannot be used in bus-
oriented multiprocessor with two or more processors.
Conditions for Incoherence
Cache-coherence problems occur in multiprocessors with private caches because of the need
to share writable data. Read-only data can safely be replicated without cache coherence
enforcement mechanism to illustrate the problem, consider the three-processor configuration
with private caches
Solution to the Cache Coherence System
There are various schemes to solve the cache coherence problem in shared memory
multiprocessors.

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A simple scheme is to disallow private caches for each processor and have a shared cache
memory associated with main memory. Every data access is made to the shared cache. This
method violates the principle of closeness of CPU to cache and increases the average memory
access time. In effect, this scheme solves the problem by avoiding it.
For performance considerations it is desirable to attach a private cache to each processor. One
scheme that has been used allows only non-shared and read-only to be stored in caches. Such
items are called cacheable. Shared writable data are non-cachable. The compiler must tag data
as either cachable or non-cachable, and the system hardware makes sure that only cachable
data are stored in caches. The non-cachable data remain in main memory. This method
restricts the type of data stored in caches and introduces an extra software overhead that may
degrade performance.
A scheme that allows writable data to exist in at least one cache is a method that employs a
centralized global table in its compiler. The status of memory blocks is stored in the central
global table. Each block is identified as read-only (RO) or read-write (RW). All caches can have
copies of blocks identified as RO.
Only one cache can have a copy of an RW block. Thus if the data are updated in the cache with
an RW block, the other caches are not affected because they do not have a copy of this block.
The cache coherence problem can be solved by means of a combination of software and
hardware or by means of hardware-only schemes. The two methods mentioned previously use
software-based procedures that require the ability to tag information in order to disable
caching of shared writable data. Hardware-only solutions are handled by the hardware
automatically and have the advantage of higher speed and program transparency. In the
hardware solution, the cache controller is speedily designed to allow it to monitor all bus
requests from CPUs and IOPs. All caches attached to the bus constantly monitor the network
for possible write operations. Depending on the method used, they must then either update
or invalidate their own cache copies when a match is detected. The bus controller that
monitors this action is referred to snoopy cache as a snoopy cache controller. This is basically a
hardware unit designed to maintain a bus-watching mechanism over all the caches attached to
the bus.
Various schemes have been proposed to solve the cache coherence problem by means of
snoopy cache protocol. The simplest method is to adopt a write-through policy and use the
following procedure. All the snoopy controllers watch the bus for memory store operations.
When a word in a cache is updated by writing into it, the corresponding location in main
memory is also updated. The local snoopy controllers in all other caches check their memory
to determine if they have a copy of the word that has been overwritten. If a copy exists in a
remote cache, that location is marked invalid. Because all caches snoop on all bus writes,
whenever a word is written, the net effect is to update it in the original cache and main
memory and remove it from all other caches. If at some future time a processor accesses the
invalid item from its cache, the response is equivalent to a cache miss, and the updated item is
transferred from main memory. In this way, inconsistent versions are prevented
The Cache Coherence Problem

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In a multiprocessor system, data inconsistency may occur among adjacent levels or within the
same level of the memory hierarchy. For example, the cache and the main memory may have
inconsistent copies of the same object.
As multiple processors operate in parallel, and independently multiple caches may possess
different copies of the same memory block, this creates cache coherence problem. Cache
coherence schemes help to avoid this problem by maintaining a uniform state for each cached
block of data.

Let X be an element of shared data which has been referenced by two processors, P1 and P2.
In the beginning, three copies of X are consistent. If the processor P1 writes a new data X1 into
the cache, by using write-through policy, the same copy will be written immediately into the
shared memory. In this case, inconsistency occurs between cache memory and the main
memory. When a write-back policy is used, the main memory will be updated when the
modified data in the cache is replaced or invalidated.
In general, there are three sources of inconsistency problem −
 Sharing of writable data
 Process migration
 I/O activity
Snoopy Bus Protocols
Snoopy protocols achieve data consistency between the cache memory and the shared
memory through a bus-based memory system. Write-invalidate and write-update policies are
used for maintaining cache consistency.

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In this case, we have three processors P1, P2, and P3 having a consistent copy of data element
‘X’ in their local cache memory and in the shared memory (Figure-a). Processor P1 writes X1 in
its cache memory using write-invalidate protocol. So, all other copies are invalidated via the
bus. It is denoted by ‘I’ (Figure-b). Invalidated blocks are also known as dirty, i.e. they should

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not be used. The write-update protocol updates all the cache copies via the bus. By
using write back cache, the memory copy is also updated (Figure-c).

Cache Events and Actions

Following events and actions occur on the execution of memory-access and invalidation
commands −
 Read-miss − When a processor wants to read a block and it is not in the cache, a read-
miss occurs. This initiates a bus-read operation. If no dirty copy exists, then the main
memory that has a consistent copy, supplies a copy to the requesting cache memory. If
a dirty copy exists in a remote cache memory, that cache will restrain the main memory
and send a copy to the requesting cache memory. In both the cases, the cache copy will
enter the valid state after a read miss.
 Write-hit − If the copy is in dirty or reserved state, write is done locally and the new
state is dirty. If the new state is valid, write-invalidate command is broadcasted to all the
caches, invalidating their copies. When the shared memory is written through, the
resulting state is reserved after this first write.
 Write-miss − If a processor fails to write in the local cache memory, the copy must come
either from the main memory or from a remote cache memory with a dirty block. This is
done by sending a read-invalidate command, which will invalidate all cache copies.
Then the local copy is updated with dirty state.
 Read-hit − Read-hit is always performed in local cache memory without causing a
transition of state or using the snoopy bus for invalidation.

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 Block replacement − When a copy is dirty, it is to be written back to the main memory
by block replacement method. However, when the copy is either in valid or reserved or
invalid state, no replacement will take place.
Directory-Based Protocols
By using a multistage network for building a large multiprocessor with hundreds of processors,
the snoopy cache protocols need to be modified to suit the network capabilities. Broadcasting
being very expensive to perform in a multistage network, the consistency commands is sent
only to those caches that keep a copy of the block. This is the reason for development of
directory-based protocols for network-connected multiprocessors.
In a directory-based protocols system, data to be shared are placed in a common directory
that maintains the coherence among the caches. Here, the directory acts as a filter where the
processors ask permission to load an entry from the primary memory to its cache memory. If
an entry is changed the directory either updates it or invalidates the other caches with that
entry.
Hardware Synchronization Mechanisms
Synchronization is a special form of communication where instead of data control, information
is exchanged between communicating processes residing in the same or different processors.
Multiprocessor systems use hardware mechanisms to implement low-level synchronization
operations. Most multiprocessors have hardware mechanisms to impose atomic operations
such as memory read, write or read-modify-write operations to implement some
synchronization primitives. Other than atomic memory operations, some inter-processor
interrupts are also used for synchronization purposes.
Cache Coherency in Shared Memory Machines
Maintaining cache coherency is a problem in multiprocessor system when the processors
contain local cache memory. Data inconsistency between different caches easily occurs in this
system.
The major concern areas are −
 Sharing of writable data
 Process migration
 I/O activity
Sharing of writable data
When two processors (P1 and P2) have same data element (X) in their local caches and one
process (P1) writes to the data element (X), as the caches are write-through local cache of P1,
the main memory is also updated. Now when P2 tries to read data element (X), it does not find
X because the data element in the cache of P2 has become outdated.

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Process migration
In the first stage, cache of P1 has data element X, whereas P2 does not have anything. A
process on P2 first writes on X and then migrates to P1. Now, the process starts reading data
element X, but as the processor P1 has outdated data the process cannot read it. So, a process
on P1 writes to the data element X and then migrates to P2. After migration, a process on P2
starts reading the data element X but it finds an outdated version of X in the main memory.

I/O activity
As illustrated in the figure, an I/O device is added to the bus in a two-processor multiprocessor
architecture. In the beginning, both the caches contain the data element X. When the I/O
device receives a new element X, it stores the new element directly in the main memory. Now,
when either P1 or P2 (assume P1) tries to read element X it gets an outdated copy. So, P1
writes to element X. Now, if I/O device tries to transmit X it gets an outdated copy.

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Uniform Memory Access (UMA)

Uniform Memory Access (UMA) architecture means the shared memory is the same for all
processors in the system. Popular classes of UMA machines, which are commonly used for
(file-) servers, are the so-called Symmetric Multiprocessors (SMPs). In an SMP, all system
resources like memory, disks, other I/O devices, etc. are accessible by the processors in a
uniform manner.
Non-Uniform Memory Access (NUMA)
In NUMA architecture, there are multiple SMP clusters having an internal indirect/shared
network, which are connected in scalable message-passing network. So, NUMA architecture is
logically shared physically distributed memory architecture.
In a NUMA machine, the cache-controller of a processor determines whether a memory
reference is local to the SMP’s memory or it is remote. To reduce the number of remote
memory accesses, NUMA architectures usually apply caching processors that can cache the
remote data. But when caches are involved, cache coherency needs to be maintained. So
these systems are also known as CC-NUMA (Cache Coherent NUMA).
Cache Only Memory Architecture (COMA)
COMA machines are similar to NUMA machines, with the only difference that the main
memories of COMA machines act as direct-mapped or set-associative caches. The data blocks
are hashed to a location in the DRAM cache according to their addresses. Data that is fetched
remotely is actually stored in the local main memory. Moreover, data blocks do not have a
fixed home location, they can freely move throughout the system.
COMA architectures mostly have a hierarchical message-passing network. A switch in such a
tree contains a directory with data elements as its sub-tree. Since data has no home location,
it must be explicitly searched for. This means that a remote access requires a traversal along
the switches in the tree to search their directories for the required data. So, if a switch in the
network receives multiple requests from its subtree for the same data, it combines them into
a single request which is sent to the parent of the switch. When the requested data returns,
the switch sends multiple copies of it down its subtree.
COMA versus CC-NUMA

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Following are the differences between COMA and CC-NUMA.
 COMA tends to be more flexible than CC-NUMA because COMA transparently
supports the migration and replication of data without the need of the OS.
 COMA machines are expensive and complex to build because they need non-
standard memory management hardware and the coherency protocol is harder to
implement.
 Remote accesses in COMA are often slower than those in CC-NUMA since the tree
network needs to be traversed to find the data.
Multicore processor
A multicore processor is a single computing component comprised of two or
more CPUs that read and execute the actual program instructions. The individual cores can
execute multiple instructions in parallel, increasing the performance of software which is
written to take advantage of the unique architecture.
The first multicore processors were produced by Intel and AMD in the early 2000s. Today,
processors are created with two cores ("dual core"), four cores ("quad core"), six cores ("hexa
core"), and eight cores ("octo core"). Processors are made with as many as 100 physical cores,
as well as 1000 effective independent cores by using FPGAs (Field Programmable Gate Arrays).
A multicore processor is a single integrated circuit (a.k.a., chip multiprocessor or CMP) that
contains multiple core processing units, more commonly known as cores. There are many
different multicore processor architectures, which vary in terms of
 Number of cores. Different multicore processors often have different numbers of cores.
For example, a quad-core processor has four cores. The number of cores is usually a
power of two.
 Number of core types.
o Homogeneous (symmetric) cores. All of the cores in a homogeneous multicore
processor are of the same type; typically the core processing units are general-
purpose central processing units that run a single multicore operating system.
o Heterogeneous (asymmetric) cores. Heterogeneous multicore processors have a
mix of core types that often run different operating systems and include graphics
processing units.
 Number and level of caches. Multicore processors vary in terms of their instruction and
data caches, which are relatively small and fast pools of local memory.
 How cores are interconnected. Multicore processors also vary in terms of
their bus architectures.
 Isolation. The amount, typically minimal, of in-chip support for the spatial and temporal
isolation of cores:
 Physical isolation ensures that different cores cannot access the same physical
hardware (e.g., memory locations such as caches and RAM).
 Temporal isolation ensures that the execution of software on one core does not
impact the temporal behavior of software running on another core.
Homogeneous Multicore Processor

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The following figure notionally shows the architecture of a system in which 14 software
applications are allocated by a single host operating system to the cores in a homogeneous
quad-core processor. In this architecture, there are three levels of cache, which are
progressively larger but slower: L1 (consisting of an instruction cache and a data cache), L2,
and L3. Note that the L1 and L2 caches are local to a single core, whereas L3 is shared among
all four cores.

Heterogeneous Multicore Processor

The following figure notionally shows how these 14 applications could be allocated to four
different operating systems, which in turn are allocated to four different cores, in a
heterogeneous, quad-core processor. From left to right, the cores include a general-purpose
central processing unit core running Windows; a graphical processing unit (GPU) core running
graphics-intensive applications on Linux; a digital signal processing (DSP) core running a real-
time operating system (RTOS); and a high-performance core also running an RTOS.

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Current Trends in Multicore Processing

Multicore processors are replacing traditional, single-core processors so that fewer single-core
processors are being produced and supported. Consequently, single-core processors are
becoming technologically obsolete. Heterogeneous multicore processors, such as computer-
on-a-chip processors, are becoming more common.
Although multicore processors have largely saturated some application domains (e.g., cloud
computing, data warehousing, and on-line shopping), they are just starting to be used in real-
time, safety- and security-critical, cyber-physical systems. One area in which multicore
processing is becoming popular is in environments constrained by size, weight, and power, and
cooling (SWAP-C), in which significantly increased performance is required.
Pros of Multicore Processing
Multicore processing is typically commonplace because it offers advantages in the following
seven areas:
1. Energy Efficiency. By using multicore processors, architects can decrease the number of
embedded computers. They overcome increased heat generation due to Moore's
Law (i.e., smaller circuits increase electrical resistance, which creates more heat), which
in turn decreases the need for cooling. The use of multicore processing reduces power
consumption (less energy wasted as heat), which increases battery life.
2. True Concurrency. By allocating applications to different cores, multicore processing
increases the intrinsic support for actual (as opposed to virtual) parallel processing
within individual software applications across multiple applications.
3. Performance. Multicore processing can increase performance by running multiple
applications concurrently. The decreased distance between cores on an integrated chip
enables shorter resource access latency and higher cache speeds when compared to
using separate processors or computers. However, the size of the performance increase

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depends on the number of cores, the level of real concurrency in the actual software,
and the use of shared resources.
4. Isolation. Multicore processors may improve (but do not guarantee) spatial
and temporal isolation (segregation) compared to single-core architectures. Software
running on one core is less likely to affect software on another core than if both are
executing on the same single core. This decoupling is due to both spatial isolation (of
data in core-specific cashes) and temporal isolation, because threads on one core are
not delayed by threads on another core. Multicore processing may also improve
robustness by localizing the impact of defects to single core. This increased isolation is
particularly important in the independent execution of mixed-criticality
applications (mission-critical, safety critical, and security-critical).
5. Reliability and Robustness. Allocating software to multiple cores increases reliability
and robustness (i.e., fault and failure tolerance) by limiting fault and/or failure
propagation from software on one core to software on another. The allocation of
software to multiple cores also supports failure tolerance by supporting failover from
one core to another (and subsequent recovery).
6. Obsolescence Avoidance. The use of multicore processors enables architects to avoid
technological obsolescence and improve maintainability. Chip manufacturers are
applying the latest technical advances to their multicore chips. As the number of cores
continues to increase, it becomes increasingly hard to obtain single-core chips.
7. Hardware Costs. By using multicore processors, architects can produce systems with
fewer computers and processors.
Cons of Multicore Processing
Although there are many advantages to moving to multicore processors, architects must
address disadvantages and associated risks in the following six areas:
1. Shared Resources. Cores on the same processor share both processor-internal resources
(L3 cache, system bus, memory controller, I/O controllers, and interconnects)
and processor-external resources (main memory, I/O devices, and networks). These
shared resources imply (1) the existence of single points of failure, (2) two applications
running on the same core can interfere with each other, and (3) software running on
one core can impact software running on another core (i.e., interference can violate
spatial and temporal isolation because multicore support for isolation is limited). The
diagram below uses the color red to illustrate six shared resources.
2. Interference. Interference occurs when software executing on one core impacts the
behavior of software executing on other cores in the same processor. This interference
includes failures of both spatial isolation (due to shared memory access) and failure
of temporal isolation (due to interference delays and/or penalties). Temporal isolation is
a bigger problem than spatial isolation since multicore processors may have special
hardware that can be used to enforce spatial isolation (to prevent software running on
different cores from accessing the same processor-internal memory). The number of
interference paths increases rapidly with the number of cores and the exhaustive
analysis of all interference paths is often impossible. The impracticality of exhaustive

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analysis necessitates the selection of representative interference paths when analyzing
isolation. The following diagram uses the color red to illustrate three possible
interference paths between pairs of applications involving six shared resources.
3. Concurrency Defects. Cores execute concurrently, creating the potential for
concurrency defects including deadlock, livelock, starvation, suspension, (data) race
conditions, priority inversion, order violations, and atomicity violations. Note that these
are essentially the same types of concurrency defects that can occur when software is
allocated to multiple threads on a single core.
4. Non-determinism. Multicore processing increases non-determinism. For example, I/O
Interrupts have top-level hardware priority (also a problem with single core processors).
Multicore processing is also subject to lock trashing, which stems from excessive lock
conflicts due to simultaneous access of kernel services by different cores (resulting in
decreased concurrency and performance). The resulting non-deterministic behavior can
be unpredictable, can cause related faults and failures, and can make testing more
difficult (e.g., running the same test multiple times may not yield the same test result).
5. Analysis Difficulty. The real concurrency due to multicore processing requires different
memory consistency models than virtual interleaved concurrency. It also breaks
traditional analysis approaches for work on single core processors. The analysis of
maximum time limits is harder and may be overly conservative. Although interference
analysis becomes more complex as the number of cores-per-processor increases, overly-
restricting the core number may not provide adequate performance.
6. Accreditation and Certification. Interference between cores can cause missed deadlines
and excessive jitter, which in turn can cause faults (hazards) and failures (accidents).
Verifying a multicore system requires proper real-time scheduling and timing analysis
and/or specialized performance testing. Moving from a single-core to a multicore
architecture may require recertification. Unfortunately, current safety policy guidelines
are based on single-core architectures and must be updated based on the
recommendations that will be listed in the final blog entry in this series.

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 COMPUTER SYSTEM ARCHITECTURE UNIT - 2
The Division Algorithm
For all positive integers a and b,
where b ≠ 0,

Example
Use the division algorithm to find
the quotient and remainder when
a = 158 and b = 17

The Euclidean Algorithm

This uses the division algorithm to:-
 find the greatest common divisor (gcd)
[ aka highest common factor (hcf)]

 find the lowest common multiple (lcm) of two numbers

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 COMPUTER SYSTEM ARCHITECTURE UNIT - 2

 reduce a fraction to its simplest form

(just divide top and bottom by the gcd)
 find relatively prime (coprime) integers
These occur when the gcd (a,b) = 1
 Solve equations of the form
gcd (a,b) =ax +by

Example
Find the gcd of 135 and 1780

Example
Find the lcm of 135 and 1780

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 COMPUTER SYSTEM ARCHITECTURE UNIT - 2

Example
Reduce the fraction 1480/128600 to
its simplest form

Example
Show that 34 and 111 are co prime

Example
Solve 34x + 111y = 1 ,
where x and y are integers

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 COMPUTER SYSTEM ARCHITECTURE UNIT - 2

Diophantine Equations
These are of the form

Example
Solve the linear Diophantine Equation
69x +27y = 1332, if it exists

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 COMPUTER SYSTEM ARCHITECTURE UNIT - 2

Example
Find the positive integer values of x and y that satisfy
69x +27y = 1332

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 COMPUTER SYSTEM ARCHITECTURE UNIT - 2

Pythagorean Triples

To find these,
Pick an odd positive number
Divide its square into two integers which are
as close to being equal as is possible
e.g. 72 = 49 = 24 + 25
gives triples 7, 24, 25
72 + 242 = 252

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 COMPUTER SYSTEM ARCHITECTURE UNIT - 2
Alternatively, pick any even integer n
triples are 2n , n2- 1 and n2 + 1
e.g. picking 8 gives 16, 63 and 65
Indeed 162 + 632 = 652
Fermat’s LastTheorem

Number Bases
To convert a number into a different base, use the Division Algorithm , taking b as the required
base.
Example
Convert 36 into binary

Example
Convert 36 into hexadecimal

Example
Convert 503793 into hexadecimal
( Remember that hexadecimal uses letters)

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DIWAKAR EDUCATION HUB

COMPUTER SYSTEM
ARCHITECTURE UNIT – 2 MCQs
As per updated syllabus
DIWAKAR EDUCATION HUB

THE LEARN WITH EXPERTIES

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 COMPUTER SYSTEM ARCHITECTURE UNIT – 2 MCQs
1. Any signed negative binary number is c) (340.67)10
recognised by its ________ d) (531.668)10
a) MSB Answer: a
b) LSB Explanation: Octal to Decimal conversion is
c) Byte obtained by multiplying 8 to the power of
d) Nibble base index along with the value at that index
Answer: a position.
Explanation: Any negative number is (532.2)8 = 5 * 82 + 3 * 81 + 2 * 80 + 2 * 8-1 =
recognized by its MSB (Most Significant Bit). (346.25)10
If it’s 1, then ít’s negative, else if it’s 0, then 5. Which of the following is not a data type?
positive. a) Symbolic Data
2. The parameter through which 16 distinct b) Alphanumeric Data
values can be represented is known as c) Numeric Data
________ d) Alphabetic Data
a) Bit Answer: a
b) Byte Explanation: Data types are of three basic
c) Word types: Numeric, Alphabetic and
d) Nibble Alphanumeric. Numeric Data consists of only
Answer: c numbers.
Explanation: It can be represented up to 16 Alphabetic Data consists of only letters and a
different values with the help of a Word. blank character and alphanumeric data
Nibble is a combination of four bits and Byte consists of symbols.
is a combination of 8 bits. It is “word” which 6. ____________ is the raw material used as
is said to be a collection of 16-bits on most of input and __________ is the processed data
the systems. obtained as output of data processing.
3. If the decimal number is a fraction then its a) Data, Instructions
binary equivalent is obtained by ________ b) Instructions, Program
the number continuously by 2. c) Data, Program
a) Dividing d) Program, Code
b) Multiplying Answer: a
c) Adding Explanation: Data can be assumed as a raw
d) Subtracting material which, in turns after processing gives
Answer: b the desired output in the form of
Explanation: On multiplying the decimal instructions. Further, a set of ordered and
number continuously by 2, the binary meaningful instructions is known as a
equivalent is obtained by the collection of the program.
integer part. However, if it’s an integer, then 7. Which of the following is not a
it’s binary equivalent is determined by characteristic of a computer?
dividing the number by 2 and collecting the a) Diligence
remainders. b) I.Q.
4. The representation of octal number c) Accuracy
(532.2)8 in decimal is ________ d) Versatility
a) (346.25)10 Answer: b
b) (532.864)10 Explanation: The Computer system has no

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 COMPUTER SYSTEM ARCHITECTURE UNIT – 2 MCQs
I.Q. of its own. It does only what it is Answer: a
programmed to do. It cannot take decisions Explanation: A processor is a part of the
of its own. computer which does all the data
A computer is diligent because it can work manipulation and decision making. A
continuously for hours without getting any processor comprises of:
errors or without getting grumbled. A data path which contains the hardware
The accuracy of a computer is consistently necessary to perform all the operations. A
high and its level of accuracy depends on its controller tells the data path what needs to
design. A computer can perform any task if, it be done.
can be broken down into a series of logical The registers act as intermediate storage for
steps. Therefore, a computer is versatile. the data.
8. Fill in the blank in the diagram. 10. What does MAR stand for?
a) Main Address Register
b) Memory Access Register
c) Main Accessible Register
d) Memory Address Register
Answer: d
Explanation: MAR is a type of register which
is responsible for the fetch operation. MAR is
connected to the address bus and it specifies
the address for the read and write
operations.
11. If the control signals are generated by
combinational logic, then they are generated
a) Input Unit by a type of _______________ controlled
b) Memory Unit unit.
c) Control Unit a) Micro programmed
d) I/O Unit b) Software
Answer: c c) Logic
Explanation: The control unit manages and d) Hardwired
coordinates the operations of a computer Answer: d
system. The ALU is responsible for Explanation: The main task of a control unit
performing all the arithmetic and bitwise is to generate control signals. There are two
operations . Therefore, both these units main types of control units:
combine to form the brain of the computer A hardwired control unit generates control
,which is the central processing unit. signals by using combinational logic circuits
9. The part of a processor which contains and the Micro programmed control unit
hardware necessary to perform all the generates control signals by using some
operations required by a computer: softwares.
a) Data path 12. Which is the simplest method of
b) Controller implementing hardwired control unit?
c) Registers a) State Table Method
d) Cache b) Delay Element Method

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 COMPUTER SYSTEM ARCHITECTURE UNIT – 2 MCQs
c) Sequence Counter Method c) Multilevel Microinstruction
d) Using Circuits d) All types of microinstructions
Answer: a Answer: a
Explanation: There are 3 ways of Explanation: There are two types of
implementing hardwired control unit: microinstructions: Horizontal and Vertical.
A state table is the simplest method in which In a horizontal microinstruction, each bit
a number of circuits are designed based on represents a signal to be activated whereas,
the cells in the table. in case of vertical microinstruction bits are
A delay element method consists of a decoded and, the decoder then produces
flowchart drawn for the circuit. A D-flip flop is signals.
used as a delay element. 16. In boolean algebra, the OR operation is
A sequence counter method used k-modulo performed by which properties?
counter as a replacement for k delay a) Associative properties
elements. b) Commutative properties
13. A set of microinstructions for a single c) Distributive properties
machine instruction is called ___________ d) All of the Mentioned
a) Program Answer: d
b) Command Explanation: The expression for Associative
c) Micro program property is given by A+(B+C) = (A+B)+C &
d) Micro command A*(B*C) = (A*B)*C.
Answer: c The expression for Commutative property is
Explanation: For every micro-operation, a set given by A+B = B+A & A*B = B*A.
of microinstructions are written which The expression for Distributive property is
indicate the control signals to be activated. A given by A+BC=(A+B)(A+C) & A(B+C) = AB+AC.
set of microinstructions is a micro program. 17. The expression for Absorption law is given
The address of the next microinstruction is by _________
given by a Micro-program counter. a) A + AB = A
14. Micro-program consists of a set of b) A + AB = B
microinstructions which are strings of 0s and c) AB + AA’ = A
1s. d) A + B = B + A
a) True Answer: a
b) False Explanation: The expression for Absorption
Answer: a Law is given by: A+AB = A.
Explanation: The computer understands only Proof: A + AB = A(1+B) = A (Since 1 + B = 1 as
binary language. So, the micro-program per 1’s Property).
should have instructions which are in the 18. According to boolean law: A + 1 = ?
form of 0s and 1s. Each output line of the a) 1
micro-program corresponds to one control b) A
signal. c) 0
15. A decoder is required in case of a d) A’
______________ Answer: a
a) Vertical Microinstruction Explanation: A + 1 = 1, as per 1’s Property.
b) Horizontal Microinstruction 19. The involution of A is equal to _________
a) A

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 COMPUTER SYSTEM ARCHITECTURE UNIT – 2 MCQs
b) A’ Answer: b
c) 1 Explanation: (A’B + CD’)’ = (A’B)'(CD’)’ (By
d) 0 DeMorgan’s Theorem) = (A” + B’)(C’ + D”) (By
Answer: a DeMorgan’s Theorem) = (A + B’)(C’ + D).
Explanation: The involution of A means 24. Simplify Y = AB’ + (A’ + B)C.
double inversion of A (i.e. A”) and is equal to a) AB’ + C
A. b) AB + AC
Proof: ((A)’)’ = A c) A’B + AC’
20. A(A + B) = ? d) AB + A
a) AB Answer: a
b) 1 Explanation: Y = AB’ + (A’ + B)C = AB’ +
c) (1 + AB) (AB’)’C = (AB’ + C)( AB’ + AB’) = (AB’ + C).1 =
d) A (AB’ + C).
Answer: d 25. The boolean function A + BC is a reduced
Explanation: A(A + B) = AA + AB (By form of ____________
Distributive Property) = A + AB (A.A = A By a) AB + BC
Commutative Property) = A(1 + B) = A*1 (1 + b) (A + B)(A + C)
B = 1 by 1’s Property) = A. c) A’B + AB’C
21. DeMorgan’s theorem states that d) (A + C)B
_________ Answer: b
a) (AB)’ = A’ + B’ Explanation: (A + B)(A + C) = AA + AC + AB +
b) (A + B)’ = A’ * B BC = A + AC + AB + BC (By Commutative
c) A’ + B’ = A’B’ Property) = A(1 + C + B) + BC = A + BC (1 + B +
d) (AB)’ = A’ + B C =1 By 1’s Property).
Answer: a 26. What is an ambiguous condition in a
Explanation: The DeMorgan’s law states that NAND based S’-R’ latch?
(AB)’ = A’ + B’ & (A + B)’ = A’ * B’, as per the a) S’=0, R’=1
Dual Property. b) S’=1, R’=0
22. (A + B)(A’ * B’) = ? c) S’=1, R’=1
a) 1 d) S’=0, R’=0
b) 0 Answer: d
c) AB Explanation: In a NAND based S-R latch, If
d) AB’ S’=0 & R’=0 then both the outputs (i.e. Q &
Answer: b Q’) goes HIGH and this condition is called as
Explanation: The DeMorgan’s law states that ambiguous/forbidden state. This state is also
(AB)’ = A’ + B’ & (A + B)’ = A’ * B’, as per the known as an Invalid state as the system goes
Dual Property. into an unexpected situation.
23. Complement of the expression A’B + CD’ 27. In a NAND based S’-R’ latch, if S’=1 & R’=1
is _________ then the state of the latch is ____________
a) (A’ + B)(C’ + D) a) No change
b) (A + B’)(C’ + D) b) Set
c) (A’ + B)(C’ + D) c) Reset
d) (A + B’)(C + D’) d) Forbidden

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 COMPUTER SYSTEM ARCHITECTURE UNIT – 2 MCQs
Answer: a 31. The difference between a flip-flop & latch
Explanation: In a NAND based S’-R, latch if is ____________
S’=1 & R’=1 then there is no any change in a) Both are same
the state. It remains in its prior state. This b) Flip-flop consist of an extra output
state is used for the storage of data. c) Latches has one input but flip-flop has two
28. A NAND based S’-R’ latch can be d) Latch has two inputs but flip-flop has one
converted into S-R latch by placing Answer: c
____________ Explanation: Flip-flop is a modified version of
a) A D latch at each of its input latch. To determine the changes in states, an
b) An inverter at each of its input additional control input is provided to the
c) It can never be converted latch.
d) Both a D latch and an inverter at its input 32. How many types of flip-flops are?
Answer: d a) 2
Explanation: A NAND based S’-R’ latch can be b) 3
converted into S-R latch by placing either a D c) 4
latch or an inverter at its input as it’s d) 5
operations will be complementary. Answer: c
29. One major difference between a NAND Explanation: There are 4 types of flip-flops,
based S’-R’ latch & a NOR based S-R latch is viz., S-R, J-K, D, and T. D flip-flop is an
____________ advanced version of S-R flip-flop, while T flip-
a) The inputs of NOR latch are 0 but 1 for flop is an advanced version of J-K flip-flop.
NAND latch 33. The S-R flip flop consist of ____________
b) The inputs of NOR latch are 1 but 0 for a) 4 AND gates
NAND latch b) Two additional AND gates
c) The output of NAND latch becomes set if c) An additional clock input
S’=0 & R’=1 and vice versa for NOR latch d) 3 AND gates
d) The output of NOR latch is 1 but 0 for Answer: b
NAND latch Explanation: The S-R flip flop consist of two
Answer: a additional AND gates at the S and R inputs of
Explanation: Due to inverted input of NAND S-R latch.
based S’-R’ latch, the inputs of NOR latch are 34. What is one disadvantage of an S-R flip-
0 but 1 for NAND latch. flop?
30. The characteristic equation of S-R latch is a) It has no Enable input
____________ b) It has a RACE condition
a) Q(n+1) = (S + Q(n))R’ c) It has no clock input
b) Q(n+1) = SR + Q(n)R d) Invalid State
c) Q(n+1) = S’R + Q(n)R Answer: d
d) Q(n+1) = S’R + Q'(n)R Explanation: The main drawback of s-r flip
Answer: a flop is invalid output when both the inputs
Explanation: A characteristic equation is are high, which is referred to as Invalid State.
needed when a specific gate requires a 35. One example of the use of an S-R flip-flop
specific output in order to satisfy the truth is as ____________
table. The characteristic equation of S-R latch a) Racer
is Q(n+1) = (S + Q(n))R’. b) Stable oscillator

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 COMPUTER SYSTEM ARCHITECTURE UNIT – 2 MCQs
c) Binary storage register group of bits, which are called bytes.
d) Transition pulse generator Computer codes use binary coding schemes.
Answer: c 39. BCD uses 6 bits to represent a symbol.
Explanation: S-R refers to set-reset. So, it is a) True
used to store two values 0 and 1. Hence, it is b) False
referred to as binary storage element. It Answer: a
functions as memory storage during the No Explanation: In a Binary Coded Decimal
Change State. format, 64 characters i.e. 26 different
36. When is a flip-flop said to be transparent? characters can be represented. It is one of
a) When the Q output is opposite the input the early computer codes.
b) When the Q output follows the input 40. Which of the following is not a type of
c) When you can see through the IC computer code?
packaging a) EBCDIC
d) When the Q output is complementary of b) BCD
the input c) ASCII
Answer: b d) EDIC
Explanation: Flip-flop have the property of Answer: d
responding immediately to the changes in its Explanation: There is no coding scheme like
inputs. This property is called transparency. EDIC. EBCDIC stands for Extended Binary
37. On a positive edge-triggered S-R flip-flop, Coded Decimal Interchange Code. BCD stands
the outputs reflect the input condition when for Binary Coded Decimal. ASCII stands for
________ American Standard Code for information
a) The clock pulse is LOW interchange.
b) The clock pulse is HIGH 41. The BCD representation of (34)10 is
c) The clock pulse transitions from LOW to _______________
HIGH a) 6
d) The clock pulse transitions from HIGH to b) 7
LOW c) 8
Answer: c d) 5
Explanation: Edge triggered device will follow Answer: b
when there is transition. It is a positive edge Explanation: BCD numbers are represented
triggered when transition takes place from as:
low to high, while, it is negative edge 34 = (0011 0100)BCD.
triggered when the transition takes place Each digit is individually taken and an
from high to low. equivalent standard 4 bit term is written for
38. A group of bits used to represent a the respective digit.
symbol is called a ____________ 42. Perform BCD addition of (23)BCD + (20)BCD .
a) byte a) 00110100
b) memory b) 01000011
c) nibble c) 10011
d) code d) 11100
Answer: a Answer: b
Explanation: In binary coding, every symbol Explanation: To add any two BCD numbers :
that appears in data is represented by a Simply perform the addition : 23+20=43.

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 COMPUTER SYSTEM ARCHITECTURE UNIT – 2 MCQs
Then, write the equivalent BCD number = Answer: c
(0100 0011)BCD. Explanation: To obtain the 10’s complement,
43. The weights used in Binary coded decimal we first obtain the 9’s complement and then
code are: add 1 to it.
a) 4,2,1 999-455=544 (9’s)
b) 8,4,2,1 544+1=545(10’s).
c) 6,4,2,1 47. The Excess-3 representation of
d) 2,1 (0100)BCD is __________
Answer: b a) 0110
Explanation: BCD is a weighted code and it b) 1110
uses the weights 8,4,2,1 respectively. It is c) 0111
often called the 8421 code. Since, it uses 4 d) 1100
bits for the representation therefore the Answer: c
weights are assigned as : 23 = 8, 22 = 4, 21 = 2, Explanation: The excess-3 code is obtained
20 = 1. by adding 3 to the BCD code.
44. Write the decimal equivalent for Here, 0100+0011=0111.
(110001)BCD. Also, 4+3=7.
a) 31 48. What is the hold condition of a flip-flop?
b) 13 a) Both S and R inputs activated
c) C1 b) No active S or R input
d) 1C c) Only S is active
Answer: a d) Only R is active
Explanation: To obtain the decimal Answer: b
equivalent : Explanation: The hold condition in a flip-flop
We start from the rightmost bit and make is obtained when both of the inputs are LOW.
groups of 4, then write the decimal It is the No Change State or Memory Storage
equivalent accordingly. state if a flip-flop.
0011 0001 = (31)10. 49. If an active-HIGH S-R latch has a 0 on the
45. The 9’s complement of 45 is S input and a 1 on the R input and then the R
_____________ input goes to 0, the latch will be ________
a) 45 a) SET
b) 54 b) RESET
c) 64 c) Clear
d) 46 d) Invalid
Answer: b Answer: b
Explanation: The 9’s complement of a Explanation: If S=0, R=1, the flip flop is at
number is obtained by subtracting each digit reset condition. Then at S=0, R=0, there is no
from 9. Here, 99-45=54. Therefore, the 9’s change. So, it remains in reset. If S=1, R=0,
complement is 54. the flip flop is at the set condition.
46. The 10’s complement of 455 is _________ 50. The circuit that is primarily responsible
a) 543 for certain flip-flops to be designated as
b) 544 edge-triggered is the _____________
c) 545 a) Edge-detection circuit
d) 546 b) NOR latch

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 COMPUTER SYSTEM ARCHITECTURE UNIT – 2 MCQs
c) NAND latch inputs are at logic 0 or all inputs are at logic 1,
d) Pulse-steering circuit then it is EX-NOR. (The truth tables for NOR
Answer: a and EX-NOR Gates are shown in above table).
Explanation: The circuit that is primarily 52. The code where all successive numbers
responsible for certain flip-flops to be differ from their preceding number by single
designated as edge-triggered is the edge- bit is __________
detection circuit. a) Alphanumeric Code
51. The output of a logic gate is 1 when all b) BCD
the input are at logic 0 as shown below: c) Excess 3
d) Gray
INPUT OUTPUT Answer: d
Explanation: The code where all successive
A B C numbers differ from their preceding number
by single bit is gray code. It is an unweighted
0 0 1 code. The most important characteristic of
this code is that only a single bit change
0 1 0 occurs when going from one code number to
next. BCD Code is one in which decimal digits
are represented by a group of 4-bits each,
1 0 0
whereas, in Excess-3 Code, the decimal
numbers are incremented by 3 and then
1 1 0 written in their BCD format.
53. The following switching functions are to
INPUT OUTPUT be implemented using a decoder:
f1 = ∑m(1, 2, 4, 8, 10, 14) f2 = ∑m(2, 5, 9, 11)
A B C f3 = ∑m(2, 4, 5, 6, 7)
The minimum configuration of decoder will
0 0 1 be __________
a) 2 to 4 line
b) 3 to 8 line
0 1 0
c) 4 to 16 line
d) 5 to 32 line
1 0 0
Answer: c
Explanation: 4 to 16 line decoder as the
1 1 1 minterms are ranging from 1 to 14.
The gate is either _________ 54. How many AND gates are required to
a) A NAND or an EX-OR realize Y = CD + EF + G?
b) An OR or an EX-NOR a) 4
c) An AND or an EX-OR b) 5
d) A NOR or an EX-NOR c) 3
d) 2
Answer: d
Explanation: The output of a logic gate is 1 Answer: d
when all inputs are at logic 0. The gate is Explanation: To realize Y = CD + EF + G, two
NOR. The output of a logic gate is 1 when all
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 COMPUTER SYSTEM ARCHITECTURE UNIT – 2 MCQs
AND gates are required and two OR gates are generated in the previous stage. Thus three
required. inputs and two outputs (Sum and Carry) are
55. The NOR gate output will be high if the there. In case of half adder circuit, there are
two inputs are __________ only two inputs bits and two outputs (SUM
a) 00 and CARRY).
b) 01 59. How many two input AND gates and two
c) 10 input OR gates are required to realize Y = BD
d) 11 + CE + AB?
Answer: a a) 3, 2
Explanation: In 01, 10 or 11 output is low if b) 4, 2
any of the I/P is high. So, the correct option c) 1, 1
will be 00. d) 2, 3
56. How many two-input AND and OR gates Answer: a
are required to realize Y = CD+EF+G? Explanation: There are three product terms.
a) 2, 2 So, three AND gates of two inputs are
b) 2, 3 required. As only two input OR gates are
c) 3, 3 available, so two OR gates are required to get
d) 3, 2 the logical sum of three product terms.
Answer: a 60. Which of following are known as universal
Explanation: Y = CD + EF + G gates?
The number of two input AND gate = 2 a) NAND & NOR
The number of two input OR gate = 2. b) AND & OR
57. A universal logic gate is one which can be c) XOR & OR
used to generate any logic function. Which of d) EX-NOR & XOR
the following is a universal logic gate? Answer: a
a) OR Explanation: The NAND & NOR gates are
b) AND known as universal gates because any digital
c) XOR circuit can be realized completely by using
d) NAND either of these two gates, and also they can
Answer: d generate the 3 basic gates AND, OR and NOT.
Explanation: An Universal Logic Gate is one 61. The gates required to build a half adder
which can generate any logic function and are __________
also the three basic gates: AND, OR and NOT. a) EX-OR gate and NOR gate
Thus, NOR and NAND can generate any logic b) EX-OR gate and OR gate
function and are thus Universal Logic Gates. c) EX-OR gate and AND gate
58. A full adder logic circuit will have d) EX-NOR gate and AND gate
__________ Answer: c
a) Two inputs and one output Explanation: The gates required to build a
b) Three inputs and three outputs half adder are EX-OR gate and AND gate. EX-
c) Two inputs and two outputs OR outputs the SUM of the two input bits
d) Three inputs and two outputs whereas AND outputs the CARRY of the two
Answer: d input bits.
Explanation: A full adder circuit will add two 62. The CISC stands for ___________
bits and it will also accounts the carry input a) Computer Instruction Set Compliment

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 COMPUTER SYSTEM ARCHITECTURE UNIT – 2 MCQs
b) Complete Instruction Set Compliment 66. Both the CISC and RISC architectures have
c) Computer Indexed Set Components been developed to reduce the ______
d) Complex Instruction set computer a) Cost
Answer: d b) Time delay
Explanation: CISC is a computer architecture c) Semantic gap
where in the processor performs more d) All of the mentioned
complex operations in one step. Answer: c
63. The computer architecture aimed at Explanation: The semantic gap is the gap
reducing the time of execution of instructions between the high level language and the low
is ________ level language.
a) CISC 67. Out of the following which is not a CISC
b) RISC machine.
c) ISA a) IBM 370/168
d) ANNA b) VAX 11/780
Answer: b c) Intel 80486
Explanation: The RISC stands for Reduced d) Motorola A567
Instruction Set Computer. Answer: d
3. The Sun micro systems processors usually Explanation: None.
follow _____ architecture. 68. Pipe-lining is a unique feature of _______
a) CISC a) RISC
b) ISA b) CISC
c) ULTRA SPARC c) ISA
d) RISC d) IANA
Answer: d Answer: a
Explanation: The Risc machine aims at Explanation: The RISC machine architecture
reducing the instruction set of the computer. was the first to implement pipe-lining.
64. The RISC processor has a more 69. In CISC architecture most of the complex
complicated design than CISC. instructions are stored in _____
a) True a) Register
b) False b) Diodes
Answer: b c) CMOS
Explanation: The RISC processor design is d) Transistors
more simpler than CISC and it consists of Answer: d
fewer transistors. Explanation: In CISC architecture more
65. The iconic feature of the RISC machine emphasis is given on the instruction set and
among the following is _______ the instructions take over a cycle to
a) Reduced number of addressing modes complete.
b) Increased memory size 70. Which of the architecture is power
c) Having a branch delay slot efficient?
d) All of the mentioned a) CISC
Answer: c b) RISC
Explanation: A branch delay slot is an c) ISA
instruction space immediately following a d) IANA
jump or branch.
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 COMPUTER SYSTEM ARCHITECTURE UNIT – 2 MCQs
Answer: b Answer: b
Explanation: Hence the RISC architecture is Explanation: The answer is Logical. To handle
followed in the design of mobile devices. user programs properly, the operating system
71. A task carried out by the OS and and the hardware should support a basic
hardware to accommodate multiple form of module to provide protection and
processes in main memory. sharing.
a) Memory control 75. An executing process must be loaded
b) Memory management entirely in main memory. What kind of a
c) Memory sharing memory organization is this?
d) Memory usage a) Physical
Answer: b b) Logical
Explanation: Memory management is carried c) Structural
out by the OS and hardware to accommodate d) Simple
multiple processes in main memory. Answer: d
72. An HTML file is a text file containing small Explanation: This is simple memory
markup tags. organisation. An executing process must be
a) True loaded entirely in main memory (if overlays
b) False are not used).
Answer: a 76. FTP stands for?
Explanation: The statement is true. HTML a) File Text Protocol
stands for Hyper Text Markup Language. It is b) File Transfer Protocol
a text file containing small markup tags. c) Firm Transfer Protocol
73. Secondary memory is the long term store d) File Transplant Protocol
for programs and data while main memory Answer: b
holds program and data currently in use. Explanation: FTP stands for File Transfer
What kind of an organization is this? Protocol. It is a type of internet service use
a) Physical for the transmission of files.
b) Logical 77. A set of overlapping divisions in the main
c) Structural memory are called _______
d) Simple a) Partitions
Answer: a b) Divisions
Explanation: The secondary memory is the c) Blocks
long term store for programs and data while d) Modules
main memory holds program and data Answer: a
currently in use. This is a physical Explanation: Partition main memory into a
organization. set of non overlapping regions called
74. Memory organization in which users write partitions. Partitions can be of equal or
programs in modules with different unequal sizes.
characteristics. 78. Any program, no matter how small,
a) Physical occupies an entire partition. This is called
b) Logical ____________
c) Structural a) fragmentation
d) Simple b) prior fragmentation

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 COMPUTER SYSTEM ARCHITECTURE UNIT – 2 MCQs
c) internal fragmentation discharge. The potential static charge that
d) external fragmentation can develop from walking on tile floors is
Answer: c greater than 15000 volts while carpeted
Explanation: It is called as internal floors can generate in excess of 30000 volts.
fragmentation. Main memory use is 82. What must be done to interface TTL to
inefficient. Any program, no matter how CMOS?
small, occupies an entire partition. This is a) A dropping resistor must be used on the
called internal fragmentation. CMOS of 12 V supply to reduce it to 5 V for
79. __________ is used to shift processes so the TTL
they are contiguous and all free memory is in b) As long as the CMOS supply voltage is 5 V
one block. they can be interfaced (however, the fan-out
a) Fragmentation of the TTL is limited to five CMOS gates)
b) Compaction c) A 5 V zener diode must be placed across
c) External Fragmentation the inputs of the TTL gates in order to protect
d) Division them from the higher output voltages of the
Answer: b CMOS gates
Explanation: Use compaction to shift d) A pull-up resistor must be used between
processes so they are contiguous and all free the TTL output-CMOS input node and Vcc;
memory is in one block. the value of RP will depend on the number of
80. _______ searches for smallest block. The CMOS gates connected to the node
fragment left behind is small as possible. Answer: d
a) best fit Explanation: To interface TTL to CMOS a pull-
b) first fit up resistor must be used between the TTL
c) next fit output-CMOS input node and Vcc. A pull-up
d) last fit resistor is used to avoid the floating state on
Answer: a the input node of the CMOS, thus using a
Explanation: Best fit searches for the smallest small amount of current. The value of RP will
block. The fragment left behind is as small as depend on the number of CMOS gates
possible. connected to the node.
81. What is the static charge that can be 83. What causes low-power Schottky TTL to
stored by your body as you walk across a use less power than the 74XX series TTL?
carpet? a) The Schottky-clamped transistor
a) 300 volts b) A larger value resistor
b) 3000 volts c) The Schottky-clamped MOSFET
c) 30000 volts d) A small value resistor
d) Over 30000 volts Answer: b
Answer: d Explanation: A larger value resistor causes
Explanation: When a person walks across a low power low-power Schottky TTL to use
carpeted or tile floor electric charge builds up less power than the 74XX series TTL.
in the body due to the friction between shoes 84. What are the major differences between
and floor material. If the friction static is the 5400 and 7400 series of ICs?
greater the voltage potential develop in the a) The 5400 series are military grade and
body will be greater. You start act as a require tighter supply voltages and
capacitor. This is called Electrostatic temperatures

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 COMPUTER SYSTEM ARCHITECTURE UNIT – 2 MCQs
b) The 5400 series are military grade and It consists of a control unit and the arithmetic
allow for a wider range of supply voltages and logic unit. It is responsible for performing
and temperatures all the processes and operations.
c) The 7400 series are an improvement over 87. Control Unit acts as the central nervous
the original 5400s system of the computer.
d) The 7400 series was originally developed a) True
by Texas Instruments and the 5400 series was b) False
brought out by National Semiconductors Answer: a
after TI’s patents expired as a second supply Explanation: The control unit is referred to as
source the central nervous system because it selects
Answer: b and interprets the instructions and
Explanation: The 5400 series are military coordinates execution.
grade and allow for a wider range of supply 88. What does MBR stand for?
voltages and temperatures, these are the a) Main Buffer Register
major differences between the 5400 and b) Memory Buffer Routine
7400 series of ICs. Also, the working c) Main Buffer Routine
temperature range of 5400 series is -50 to d) Memory Buffer Register
125C while that for 7400 is 0 to 70C. Answer: d
85. Which of the following statements apply Explanation: The binary subtraction 0 – 1
to CMOS devices? gives the result 1.
a) The devices should not be inserted into A borrow of 1 is although generated and is
circuits with the power on removed from the next higher column.
b) All tools, test equipment and metal 89. In the instruction ADD A, B, the answer
workbenches should be tied to earth ground gets stored in ___________
c) The devices should be stored and shipped a) B
in antistatic tubes or conductive foam b) A
d) All of the Mentioned c) Buffer
Answer: d d) C
Explanation: For CMOS devices, all the Answer: b
mentioned statements are applicable. The Explanation: In any instruction of the form
devices should not be inserted into circuits ADD A, B; the answer gets stored in the A
with the power on. All tools, test equipment register. The format is: ADD Destination,
and metal workbenches should be tied to Source.
earth ground. Also, the devices should be
90. What is the high speed memory between
stored and shipped in antistatic tubes or
the main memory and the CPU called?
conductive foam.
a) Register Memory
86. Brain of computer is ____________ b) Cache Memory
a) Control unit c) Storage Memory
b) Arithmetic and Logic unit d) Virtual Memory
c) Central Processing Unit
Answer: b
d) Memory
Explanation: It is called the Cache Memory.
Answer: c The cache memory is the high speed memory
Explanation: The CPU is referred to as the between the main memory and the CPU.
brain of a computer.

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91. Cache Memory is implemented using the c) Write back
DRAM chips. d) Buffered write
a) True Answer: b
b) False Explanation: There is no policy which is called
Answer: b as the write within policy. The other three
Explanation: The Cache memory is options are the write policies which are used
implemented using the SRAM chips and not to avoid cache coherence.
the DRAM chips. SRAM stands for Static RAM. 96. What does PC stand for?
It is faster and is expensive. a) Program Changer
92. Whenever the data is found in the cache b) Program Counter
memory it is called as _________ c) Performance Counter
a) HIT d) Performance Changer
b) MISS Answer: b
c) FOUND Explanation: The Program counter contains
d) ERROR the address of the next instruction which is to
Answer: a be fetched by the control unit.
Explanation: Whenever the data is found in All other options are invalid.
the cache memory, it is called as Cache HIT. 97. Which of the following holds the last
CPU first checks in the cache memory since it instruction fetched?
is closest to the CPU. a) PC
93. LRU stands for ___________ b) MAR
a) Low Rate Usage c) MBR
b) Least Rate Usage d) IR
c) Least Recently Used Answer: d
d) Low Required Usage Explanation: The IR which stands for the
Answer: c instruction register contains the last
Explanation: LRU stands for Least Recently instruction fetched.
Used. LRU is a type of replacement policy All the others options are registers which are
used by the cache memory. used for the fetch operation.
94. When the data at a location in cache is 98. The portion of the processor which
different from the data located in the main contains the hardware required to fetch the
memory, the cache is called _____________ operations is _______
a) Unique a) Datapath
b) Inconsistent b) Processor
c) Variable c) Control
d) Fault d) Output unit
Answer: b Answer: a
Explanation: The cache is said to be Explanation: The datapath contains the
inconsistent. Inconsistency must be avoided hardware required to fetch the operations.
as it leads to serious data bugs. The control tells the data path what needs to
95. Which of the following is not a write be done.
policy to avoid Cache Coherence? 99. Causing the CPU to step through a series
a) Write through of micro operations is called _________
b) Write within a) Execution

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 COMPUTER SYSTEM ARCHITECTURE UNIT – 2 MCQs
b) Runtime several inputs and gives one output
c) Sequencing b) A multiplexer is a device which converts
d) Pipelining many signals into one
Answer: c c) It takes one input and results into many
Explanation: Sequencing is the process of output
causing the CPU to step through a series of d) It is a type of encoder which decodes
micro operations. Execution causes the several inputs and gives one output
performance of each micro operation. Answer: b
100. The functions of execution and Explanation: A multiplexer (or MUX) is a
sequencing are performed by using device that selects one of several analog or
______________ digital input signals and forwards the selected
a) Input Signals input into a single line, depending on the
b) Output Signals active select lines.
c) Control Signals 104. Which combinational circuit is renowned
d) CPU for selecting a single input from multiple
Answer: c inputs & directing the binary information to
Explanation: Sequencing followed by the output line?
process of execution is performed by the a) Data Selector
Control signals. Sequencing is traversing each b) Data distributor
and every operation whereas execution c) Both data selector and data distributor
causes the performance of each operation. d) DeMultiplexer
101. What does D in the D-flip flop stand for? Answer: a
a) Digital Explanation: Data Selector is another name
b) Direct of Multiplexer. A multiplexer (or MUX) is a
c) Delay device that selects one of several analog or
d) Durable digital input signals and forwards the selected
Answer: c input into a single line, depending on the
Explanation: In the hardwired control unit, active select lines.
the delay element method uses D-flip flop 105. It is possible for an enable or strobe
which causes a delay. Since, in the delay input to undergo an expansion of two or
element method, there must be a finite time more MUX ICs to the digital multiplexer with
gap between the 2 steps. the proficiency of large number of
102. All input of NOR as low produces result ___________
as __________ a) Inputs
a) Low b) Outputs
b) Mid c) Selection lines
c) High d) Enable lines
d) Floating Answer: a
Answer: c Explanation: It is possible for an enable or
Explanation: All input of NOR as low strobe input to undergo an expansion of two
produces the result as high, whereas, rest all or more MUX ICs to the digital multiplexer
conditions produce output as low. with the proficiency of large number of
103. What is a multiplexer? inputs.
a) It is a type of decoder which decodes

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106. Which is the major functioning a particular computer and used directly by
responsibility of the multiplexing the computer is machine language.
combinational circuit? 109. Binary code comprises of digits from 0 to
a) Decoding the binary information 9.
b) Generation of all minterms in an output a) True
function with OR-gate b) False
c) Generation of selected path between Answer: b
multiple sources and a single destination Explanation: The statement is false. Binary as
d) Encoding of binary information the word suggests contains only 2 digits : 0
Answer: c and 1.
Explanation: The major functioning 0 denotes false and 1 denotes a truth value.
responsibility of the multiplexing 110. The ___________ contains the address
combinational circuit is generation of of the next instruction to be executed.
selected path between multiple sources and a) IR
a single destination because it makes the b) PC
circuit too flexible. A multiplexer (or MUX) is c) Accumulator
a device that selects one of several analog or d) System counter
digital input signals and forwards the selected Answer: b
input into a single line, depending on the Explanation: PC stands for program counter
active select lines. (It contains the address of the next
107. What is the function of an enable input instruction to be executed).
on a multiplexer chip? 111. The memory unit is made up of _____
a) To apply Vcc bytes.
b) To connect ground a) 256
c) To active the entire chip b) 124
d) To active one half of the chip c) 4096
Answer: c d) 3096
Explanation: Enable input is used to active Answer: c
the chip, when enable is high the chip works Explanation: The memory unit is made up of
(ACTIVE), when enable is low the chip does 4,096 bytes. Memory unit is responsible for
not work (MEMORY). However, Enable can be the storage of data. It is an important entity
Active-High or Active-Low, indicating it is in the computer system.
active either when it is connected to VCC or
112. A document that specifies how many
GND respectively.
times and with what data the program must
108. The language made up of binary coded be run in order to thoroughly test it.
instructions. a) addressing plan
a) Machine b) test plan
b) C c) validation plan
c) BASIC d) verification plan
d) High level
Answer: b
Answer: a Explanation: Test plan is the A document that
Explanation: The language made up of binary specifies how many times and with what data
coded instructions built into the hardware of the program must be run in order to
thoroughly test it. It comes under testing.

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 COMPUTER SYSTEM ARCHITECTURE UNIT – 2 MCQs
113. An approach that designs test cases by 117. The rules that give meaning to the
looking at the allowable data values. instructions.
a) Maintenance a) Semantics
b) Evaluation b) Syntax
c) Data coverage c) Code
d) Validation d) Cases
Answer: c Answer: a
Explanation: Data coverage is the term used. Explanation: The answer is semantics. They
It is responsible for designing the test cases. are the rules that give meaning to the
114. The formal grammar rules governing the instructions. The syntax is the formal rules
construction of valid instruction. that ensure validation of code.
a) test case 118. One multiplexer can take the place of
b) syntax ___________
c) program a) Several SSI logic gates
d) semantics b) Combinational logic circuits
Answer: b c) Several Ex-NOR gates
Explanation: Syntax determines the d) Several SSI logic gates or combinational
grammatical rules in a code. Semantics give logic circuits
meaning to the instructions. Answer: d
115. A program that reads each of the Explanation: A multiplexer (or MUX) is a
instructions in mnemonic form and translates device that selects one of several analog or
it into the machine-language equivalent. digital input signals and forwards the selected
a) Machine language input into a single line, depending on the
b) Assembler active select lines. Since many operational
c) Interpreter behaviour can be performed by using a
d) C program multiplexer. Whereas, a combinational circuit
Answer: b is a combination of many logic gates which
Explanation: Assembler does this job. A makes the circuit more complex.
language that uses mnemonic codes for the 119. A digital multiplexer is a combinational
representation of machine-language circuit that selects ___________
instructions is called assembly language. a) One digital information from several
116. An approach that designs test cases by sources and transmits the selected one
looking at the allowable data values. b) Many digital information and convert them
a) Data coverage into one
b) Code Coverage c) Many decimal inputs and transmits the
c) Debugging selected information
d) Validation d) Many decimal outputs and accepts the
Answer: a selected information
Explanation: Data coverage is an approach Answer: a
that designs test cases by looking at the Explanation: A digital multiplexer is a
allowable data values. Code coverage is an combinational circuit that selects one digital
approach that designs test cases by looking at information from several sources and
the code. transmits the selected information on a single
output line depending on the status of the

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 COMPUTER SYSTEM ARCHITECTURE UNIT – 2 MCQs
select lines. That is why it is also known as a c) Rotary switch
data selector. d) Linear stepper
120. In a multiplexer, the selection of a Answer: c
particular input line is controlled by Explanation: A basic multiplexer principle can
___________ be demonstrated through the use of a rotary
a) Data controller switch. Since its behaviour is similar to the
b) Selected lines multiplexer. There are around 10 digits out of
c) Logic gates which one is selected one at a time and fed
d) Both data controller and selected lines to the output.
Answer: b 124. How many NOT gates are required for
Explanation: The selection of a particular the construction of a 4-to-1 multiplexer?
input line is controlled by a set of selected a) 3
lines in a multiplexer, which helps to select a b) 4
particular input from several sources. c) 2
121. If the number of n selected input lines is d) 5
equal to 2^m then it requires _____ select Answer: c
lines. Explanation: There are two NOT gates
a) 2 required for the construction of 4-to-1
b) m multiplexer. x0, x1, x2 and x3 are the inputs
c) n and C1 and C0 are the select lines and M is
d) 2n the output.
Answer: b The diagram of a 4-to-1 multiplexer is shown
Explanation: If the number of n selected below:
input lines is equal to 2^m then it requires m
select lines to select one of m select lines.
122. How many select lines would be
required for an 8-line-to-1-line multiplexer?
a) 2
b) 4
c) 8
d) 3
Answer: d
Explanation: 2n input lines, n control lines 125. In the given 4-to-1 multiplexer, if c1 = 0
and 1 output line available for MUX. Here, 8 and c0 = 1 then the output M is ___________
input lines mean 23 inputs. So, 3 control lines
are possible. Depending on the status of the
select lines, the input is selected and fed to
the output.
123. A basic multiplexer principle can be
demonstrated through the use of a
___________
a) Single-pole relay
b) DPDT switch
a) X0
b) X1
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 COMPUTER SYSTEM ARCHITECTURE UNIT – 2 MCQs
c) X2 c) Threads
d) X3 d) Concurrency
Answer: b Answer: d
Explanation: The output will be X1, because Explanation: Concurrency is the term used
c1 = 0 and c0 = 1 results into 1 which further for the same. When several things are
results as X1. And rest of the AND gates gives accessed simultaneously, the job is said to be
output as 0. concurrent.
126. The enable input is also known as 130. ______________ leads to concurrency.
___________ a) Serialization
a) Select input b) Parallelism
b) Decoded input c) Serial processing
c) Strobe d) Distribution
d) Sink Answer: b
Answer: c Explanation: Parallelism leads naturally to
Explanation: The enable input is also known Concurrency. For example, Several processes
as strobe which is used to cascade two or trying to print a file on a single printer.
more multiplexer ICs to construct a 131. A parallelism based on increasing
multiplexer with a larger number of inputs. processor word size.
Enable input activates the multiplexer to a) Increasing
operate. b) Count based
127. Execution of several activities at the c) Bit based
same time. d) Bit level
a) processing Answer: d
b) parallel processing Explanation: Bit level parallelism is based on
c) serial processing increasing processor word size. It focuses on
d) multitasking hardware capabilities for structuring.
Answer: b 132. A type of parallelism that uses micro
Explanation: Execution of several activities at architectural techniques.
the same time is referred to as parallel a) instructional
processing. Like, Two multiplications at the b) bit level
same time on 2 different processes. c) bit based
128. Parallel processing has single execution d) increasing
flow. Answer: a
a) True Explanation: Instructional level uses micro
b) False architectural techniques. It focuses on
Answer: b program instructions for structuring.
Explanation: The statement is false. 133. MIPS stands for?
Sequential programming specifically has a) Mandatory Instructions/sec
single execution flow. b) Millions of Instructions/sec
129. A term for simultaneous access to a c) Most of Instructions/sec
resource, physical or logical. d) Many Instructions / sec
a) Multiprogramming Answer: b
b) Multitasking Explanation: MIPS stands for Millions of

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 COMPUTER SYSTEM ARCHITECTURE UNIT – 2 MCQs
Instructions/sec. MIPS is a way to measure as inputs which range from 0-9. So, total 10
the cost of computing. inputs are there in a decimal-to-BCD encoder.
134. The measure of the “effort” needed to 138. How many outputs will a decimal-to-BCD
maintain efficiency while adding processors. encoder have?
a) Maintainablity a) 4
b) Efficiency b) 8
c) Scalabilty c) 12
d) Effectiveness d) 16
Answer: c Answer: a
Explanation: The measure of the “effort” Explanation: An encoder is a combinational
needed to maintain efficiency while adding circuit encoding the information of 2n input
processors is called as scalabilty. lines to n output lines, thus producing the
135. The rate at which the problem size need binary equivalent of the input. Thus, a
to be increased to maintain efficiency. decimal to BCD encoder has 4 outputs.
a) Isoeffciency 139. How is an encoder different from a
b) Efficiency decoder?
c) Scalabilty a) The output of an encoder is a binary code
d) Effectiveness for 1-of-N input
Answer: a b) The output of a decoder is a binary code
Explanation: Isoefficiency is the rate at which for 1-of-N input
the problem size need to be increased to c) The output of an encoder is a binary code
maintain efficiency. for N-of-1 output
136. Several instructions execution d) The output of a decoder is a binary code
simultaneously in ________________ for N-of-1 output
a) processing Answer: a
b) parallel processing Explanation: An encoder is a combinational
c) serial processing circuit encoding the information of 2n input
d) multitasking lines to n output lines, thus producing the
Answer: b binary equivalent of the input. It performs
Explanation: In parallel processing, the the opposite operation of a decoder which
several instructions are executed results in 2n outputs from n inputs. Thus, an
simultaneously. encoder different from a decoder because of
137. How many inputs will a decimal-to-BCD the output of an encoder is a binary code for
encoder have? 1-of-N input.
a) 4 140. The full form of ROM is __________
b) 8 a) Read Outside Memory
c) 10 b) Read Out Memory
d) 16 c) Read Only Memory
Answer: c d) Read One Memory
Explanation: An encoder is a combinational Answer: c
circuit encoding the information of 2n input Explanation: The full form of ROM is Read
lines to n output lines, thus producing the Only Memory.
binary equivalent of the input. Thus, a 141. ROM consist of __________
Decimal-to-bcd converter has decimal values a) NOR and OR arrays

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 COMPUTER SYSTEM ARCHITECTURE UNIT – 2 MCQs
b) NAND and NOR arrays 145. PLDs with programmable AND and fixed
c) NAND and OR arrays OR arrays are called __________
d) NOR and AND arrays a) PAL
Answer: c b) PLA
Explanation: ROM consists of NAND and OR c) APL
arrays which can be programmed by the user d) PPL
to implement combinational & sequential Answer: a
functions. Combinational Operations like that Explanation: PLDs with programmable AND
of adders and subtractors and Sequential and fixed OR arrays are called PAL (i.e.
Functions like that of storing in the memory. Programmable Array Logic). However, PAL is
142. For reprogrammability, PLDs use less flexible but has higher speed.
__________ 146. When both the AND and OR are
a) PROM programmable, such PLDs are known as
b) EPROM __________
c) CDROM a) PAL
d) PLA b) PPL
Answer: b c) PLA
Explanation: For reprogrammability, PLDs use d) APL
EPROM (i.e. Erasable PROM). It erases the Answer: c
previous program and starts uploading a new Explanation: When both the AND and OR are
one. However, data is erased by exposing it programmable, such PLDs are known as PLA
to UV-light, which is a tedious and time- (i.e. Programmable Logic Array). However,
consuming process. PLA is more flexible but has less speed.
143. The full form of PROM is __________ 147. ASIC stands for __________
a) Previous Read Only Memory a) Application Special Integrated Circuits
b) Programmable Read Out Memory b) Applied Special Integrated Circuits
c) Programmable Read Only Memory c) Application Specific Integrated Circuits
d) Previous Read Out Memory d) Applied Specific Integrated Circuits
Answer: c Answer: c
Explanation: The full form of PROM is Explanation: In digital electronics, ASIC
Programmable Read Only Memory, where stands for Application Specific Integrated
the ROM can be programmed by the user. Circuits. It is a customized integrated circuit
144. The full form of EPROM is __________ which is produced for a specific use and not
a) Easy Programmable Read Only Memory for a common-purpose.
b) Erasable Programmable Read Only 148. The programmability and high density of
Memory PLDs make them useful in the design of
c) Eradicate Programmable Read Only __________
Memory a) ISAC
d) Easy Programmable Read Out Memory b) ASIC
Answer: b c) SACC
Explanation: The full form of EPROM is d) CISF
Erasable Programmable Read Only Memory, Answer: b
where the ROM can be erased and re-used by Explanation: The programmability and high
the user. density of PLDs make them useful in the

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 COMPUTER SYSTEM ARCHITECTURE UNIT – 2 MCQs
design of ASIC (i.e. Application Specific Answer: b
Integrated Circuits) where design changes Explanation: If we record any music in any
can be more rapidly and inexpensively. recorder, it means that we are giving data to
149. FPGA stands for __________ a recorder. So, such process is called
a) Full Programmable Gate Array encoding. Getting back the music from the
b) Full Programmable Genuine Array recorded data, is known as decoding.
c) First Programmable Gate Array 153. Can an encoder be a transducer?
d) Field Programmable Gate Array a) Yes
Answer: d b) No
Explanation: In digital electronics, FPGA c) May or may not be
stands for Field Programmable Gate Array. d) Both are not even related slightly
This type of integrated circuit is for general- Answer: a
purpose which is configured by the user as Explanation: Of course, a transducer is a
per their requirement. device which has the capability to emit data
150. Which of the following is a as well as to accept. Transducer converts
reprogrammable gate array? signal from one form of energy to another.
a) EPROM 154. How many OR gates are required for a
b) FPGA Decimal-to-bcd encoder?
c) Both EPROM and FPGA a) 2
d) ROM b) 10
Answer: c c) 3
Explanation: Both FPGA and EPROM are d) 4
reprogrammable gate array. Answer: d
151. The difference between FPGA and PLD is Explanation: An encoder is a combinational
that __________ circuit encoding the information of 2^n input
a) FPGA is slower than PLD lines to n output lines, thus producing the
b) FPGA has high power dissipation binary equivalent of the input.
c) FPGA incorporates logic blocks This is clear from the diagram that it requires
d) All of the Mentioned 4 OR gates:
Answer: c
Explanation: The differences between FPGA
and PLD is that FPGA incorporates logic
blocks instead of fixed AND-OR gates and is
faster with low power dissipation. FPGAs are
designed for having higher gate count
whereas, PLDs are used for lesser gate
counts.
152. If we record any music in any recorder,
such types of process is called ___________
a) Multiplexing
b) Encoding .
c) Decoding 155. Separation of user logical memory and
d) Demultiplexing physical memory is ___________
a) Memory control

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 COMPUTER SYSTEM ARCHITECTURE UNIT – 2 MCQs
b) Memory management used. LRU is least recently used. It replaces
c) Memory sharing page with the smallest count.
d) Virtual memory 160. An allocation that uses a proportional
Answer: d allocation scheme using priorities rather than
Explanation: The separation of user logical size.
memory and physical memory is called virtual a) Priority allocation
memory. Only part of the program needs to b) File allocation
be in memory for execution. c) Preference allocation
156. Logical Address space can be larger than d) Simple allocation
physical address space. Answer: a
a) True Explanation: Priority allocation uses a
b) False proportional allocation scheme using
Answer: a priorities rather than size.
Explanation: The statement is true. Since, a 161. A process selects a replacement frame
part of the program needs to be in memory from the set of all frames.
for the process of execution, the logical space a) Local replacement
can therefore be much larger than the b) Global replacement
physical address space. c) Block replacement
157. Virtual Memory can be implemented via d) Module replacement
__________ Answer: b
a) Demand Paging Explanation: Global replacement process
b) Logical paging selects a replacement frame from the set of
c) Structural way all frames; one process can take a frame from
d) Simple division another.
Answer: a 162. How many OR gates are required for an
Explanation: Demand paging can implement octal-to-binary encoder?
virtual memory. Another way is demand a) 3
segmentation. b) 2
158. COW stands for? c) 8
a) Copy over write d) 10
b) Convert over write Answer: a
c) Count over write Explanation: An encoder is a combinational
d) Copy over write circuit encoding the information of 2n input
Answer: d lines to n output lines, thus producing the
Explanation: COW stands for Copy over binary equivalent of the input. Thus, in octal
write. COW allows both parent and child to binary encoder there are 8 (=23) inputs,
processes to share the same pages initially. thus 3 output lines.
159. LRU stands for? 163. For 8-bit input encoder how many
a) Least Recently used combinations are possible?
b) Less Recently used a) 8
c) Least Recurrently used b) 2^8
d) Least Randomly used c) 4
Answer: a d) 2^4
Explanation: LRU stands for Least Recently
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 COMPUTER SYSTEM ARCHITECTURE UNIT – 2 MCQs
Answer: b are active on a priority encoder, the input of
Explanation: An encoder is a combinational higher value will be coded in the output.
circuit encoding the information of 2n input 167. How many outputs are present in a BCD
lines to n output lines, thus producing the decoder?
binary equivalent of the input. There are a) 4
28 combinations are possible for an 8-bit b) 5
input encoder but out of which only 8 are c) 15
used using 3 output lines. It is a disadvantage d) 10
of encoder. Answer: d
164. The discrepancy of 0 output due to all Explanation: A binary decoder is a
inputs being 0 or D0, being 0 is resolved by combinational logic circuit which decodes
using additional input known as ___________ binary information from n-inputs to a
a) Enable maximum of 2n outputs. A BCD to Decimal
b) Disable decoder has 10 number of outputs because
c) Strobe the decimal digit’s range is from 0 to 9.
d) Clock 168. Which digital system translates coded
Answer: a characters into a more useful form?
Explanation: Such problems are resolved by a) Encoder
using enable input, which behaves as active if b) Display
it gets 0 as input since it is an active-low pin. c) Counter
165. Can an encoder be called as multiplexer? d) Decoder
a) No Answer: d
b) Yes Explanation: A binary decoder is a
c) Sometimes combinational logic circuit which decodes
d) Never binary information from n-inputs to a
Answer: b maximum of 2n outputs. Decoder converts
Explanation: A multiplexer or MUX is a the coded characters into our required data
combination circuit that contains more than form.
one input line, one output line and more than 169. What control signals may be necessary
one selection line. Whereas, an encoder is to operate a 1-line-to-16 line decoder?
also considered a type of multiplexer but a) Flasher circuit control signal
without a single output line and without any b) A LOW on all gate enable inputs
selection lines. c) Input from a hexadecimal counter
166. If two inputs are active on a priority d) A HIGH on all gate enable circuits
encoder, which will be coded on the output? Answer: b
a) The higher value Explanation: A LOW on all gate enable inputs
b) The lower value is necessary to operate a 1-line-to-16 line
c) Neither of the inputs decoder because enable pins are usually,
d) Both of the inputs active-low pins.
Answer: a 170. How many inputs are required for a 1-
Explanation: An encoder is a combinational of-10 BCD decoder?
circuit encoding the information of 2n input a) 4
lines to n output lines, thus producing the b) 8
binary equivalent of the input. If two inputs

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 COMPUTER SYSTEM ARCHITECTURE UNIT – 2 MCQs
c) 10 b) 16
d) 2 c) 8
Answer: a d) 4
Explanation: A binary decoder is a Answer: d
combinational logic circuit which decodes Explanation: A binary decoder is a
binary information from n-inputs to a combinational logic circuit which decodes
maximum of 2n outputs. Therefore, for a BCD binary information from n-inputs to a
to decimal decoder, No. of inputs = 4 such maximum of 2n outputs. Here, number of
that number of outputs is <= 2n. outputs = 16.
171. A BCD decoder will have how many rows 16 = 24 = 2n. Thus, number of inputs is 4.
in its truth table? 175. A truth table with output columns
a) 10 numbered 0–15 may be for which type of
b) 9 decoder IC?
c) 8 a) Hexadecimal 1-of-16
d) 3 b) Dual octal outputs
Answer: a c) Binary-to-hexadecimal
Explanation: A binary decoder is a d) Hexadecimal-to-binary
combinational logic circuit which decodes Answer: a
binary information from n-inputs to a Explanation: A binary decoder is a
maximum of 2n outputs. Thus, BCD decoder combinational logic circuit which decodes
will have 10 rows as it’s input ranges from 0 binary information from n-inputs to a
to 9. maximum of 2n outputs. A truth table with
172. How many possible outputs would a output columns numbered 0–15 may be for
decoder have with a 6-bit binary input? Hexadecimal 1-of-16. Because, hexadecimal
a) 32 occupies less space in a system.
b) 64 176. How can the active condition (HIGH or
c) 128 LOW) or the decoder output be determined
d) 16 from the logic symbol?
Answer: c a) A bubble indicates active-HIGH
Explanation: The possible outputs would be: b) A bubble indicates active-LOW
2n = 64 (Since n = 6 here). c) A triangle indicates active-HIGH
173. One way to convert BCD to binary using d) A triangle indicates active-LOW
the hardware approach is: Answer: b
a) By using MSI IC circuits Explanation: A bubble indicates active-LOW
b) By using a keyboard encoder in a decoder always. Enable pin of the
c) By using an ALU decoder is usually active-LOW and is
d) By using UART triggered on input being at 0.
Answer: a 177. A code converter is a logic circuit that
Explanation: One way to convert BCD to _____________
binary using the hardware approach is MSI a) Inverts the given input
(medium scale integration) IC circuits. b) Converts into decimal number
174. How many inputs are required for a 1- c) Converts data of one type into another
of-16 decoder? type
a) 2 d) Converts to octal

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 COMPUTER SYSTEM ARCHITECTURE UNIT – 2 MCQs
Answer: c representation of discrete information. Codes
Explanation: A code converter is a logic can be anything like numbers, letter or
circuit that changes data presented in one words, written in terms of group of symbols.
type of binary code to another type of binary 181. One way to convert BCD to binary using
code. the hardware approach is ___________
178. Use the weighting factors to convert the a) With MSI IC circuits
following BCD numbers to binary b) With a keyboard encoder
___________ c) With an ALU
0101 0011 & 0010 0110 1000 d) UART
a) 01010011 001001101000 Answer: a
b) 11010100 100001100000 Explanation: One way to convert BCD to
c) 110101 100001100 binary using the hardware approach is MSI IC
d) 101011 001100001 (i.e. medium scale integration) circuits.
Answer: c 182. Why is the Gray code more practical to
Explanation: Firstly, convert every 4 sets of use when coding the position of a rotating
binary to decimal from the given: 0101=5, shaft?
0011=3. Then convert 53 to binary, which will a) All digits change between counts
give 110101. Again, do the same with the b) Two digits change between counts
next 4 set of binary digits. c) Only one digit changes between counts
179. The primary use for Gray code is d) Alternate digit changes between counts
___________ Answer: c
a) Coded representation of a shaft’s Explanation: The Gray code is more practical
mechanical position to use when coding the position of a rotating
b) Turning on/off software switches shaft because only one digit changes
c) To represent the correct ASCII code to between counts that is reflected to the next
indicate the angular position of a shaft on count.
rotating machinery 183. Reflected binary code is also known as
d) To convert the angular position of a shaft ___________
on rotating machinery into hexadecimal code a) BCD code
Answer: a b) Binary code
Explanation: Gray code is useful because only c) ASCII code
one bit changes at a time, which is d) Gray Code
implemented easily in Coded representation Answer: d
of a shaft’s mechanical position. In Gray Explanation: The reflected binary code is also
Code, every sequence of successive bits known as gray code because one digit
differs by 1 bit only. reflected to the next bit. In Gray Code, every
180. Code is a symbolic representation of sequence of successive bits differs by 1 bit
___________ only.
a) Discrete information 184. Why do we use gray codes?
b) Continuous information a) To count the no of bits changes
c) Decimal information into binary b) To rotate a shaft
d) Binary information into decimal c) Error correction
Answer: a d) Error Detetction
Explanation: Code is a symbolic

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 COMPUTER SYSTEM ARCHITECTURE UNIT – 2 MCQs
Answer: c 1 1 0 1 1 1
Explanation: Today, Gray codes are widely 188. Each personal computer has a
used to facilitate error correction in digital _________ that manages the computer’s
communications such as digital terrestrial arithmetical, logical and control activities.
television and some cable TV systems. a) Microprocessor
185. Earlier, reflected binary codes were b) Assembler
applied to ___________ c) Microcontroller
a) Binary addition d) Interpreter
b) 2’s complement Answer: a
c) Mathematical puzzles Explanation: Microprocessor handles all
d) Binary multiplication these activities. Each family of processors has
Answer: c its own set of instructions for handling
Explanation: The reflected binary code is also various operations like getting input from
known as gray code because one digit keyboard, displaying information on a screen
reflected to the next bit. In Gray Code, every and performing various other jobs.
sequence of successive bits differs by 1 bit 189. Assembly Language requires less
only. Reflected binary codes were applied to memory and execution time.
mathematical puzzles before they became a) True
known to engineers. b) False
186. The binary representation of BCD Answer: a
number 00101001 (decimal 29) is Explanation: The statement is true.
___________ Advantages of using assembly language are:
a) 0011101 • It requires less memory and execution time.
b) 0110101 • It allows hardware-specific complex jobs in
c) 1101001 an easier way.
d) 0101011 • It is suitable for time-critical jobs.
Answer: a 190. The data size of a word is _________
Explanation: The given BCD number a) 2-byte
00101001 has three 1s. So, it can be b) 4-byte
rewritten as 0000001-1, 0001000-8, c) 8-byte
0010100-20 and after addition, we get d)16-byte
0011101 as output. Answer: a
187. Convert binary number into gray code: Explanation: The processor supports the
100101. following data sizes:
a) 101101 • Word: a 2-byte data item
b) 001110 • Double word: a 4-byte (32 bit) data item,
c) 110111 etc.
d) 111001 191. A direct reference of specific location.
Answer: c a) Segment Address
Explanation: : Conversion from Binary To b) Absolute Address
Gray Code: c) Offset
1 (XOR) 0 (XOR) 0 (XOR) 1 (XOR) 0 (XOR) 1 d) Memory Address
Answer: b
↓ ↓ ↓ ↓ ↓ Explanation: There are two kinds of memory

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 COMPUTER SYSTEM ARCHITECTURE UNIT – 2 MCQs
addresses: b) Memory
• An absolute address – a direct reference of c) Units
specific location. d) Registers
• The segment address (or offset) – starting Answer: d
address of a memory segment with the offset Explanation: The processor has some internal
value. memory storage locations, known as
192. A Borland Turbo Assembler. registers. The registers stores data elements
a) nasm for processing without having to access
b) tasm memory.
c) gas 196. To locate the exact location of data in
d) asm memory, we need the starting address of the
Answer: b segment, which is found in the DS register
Explanation: Tasm is the borland turbo and an offset value. This offset value is also
assembler. Nasm is used with linux generally. called?
Gas is the GNU assembler. a) Effective Address
193. The instructions that tell the assembler b) Direct offset address
what to do. c) Memory address
a) Executable instructions d) General Address
b) Pseudo-ops Answer: a
c) Logical instructions Explanation: When operands are specified in
d) Macros memory addressing mode, direct access to
Answer: a main memory, usually to the data segment, is
Explanation: The executable instructions or required. This way of addressing results in
simple instructions tell the processor what to slower processing of data. To get the exact
do. Each instruction consists of an operation location of data in memory, we need
code (opcode). Each executable instruction segment start address, which is found in the
generates one machine language instruction. DS register and an offset value. This offset
194. The segment containing data values value is called an effective address.
passed to functions and procedures within 197. Each byte of character is stored as its
the program. ASCII value in _______
a) Code a) Hexadecimal
b) Data b) Binary
c) Stack c) Octal
d) System d) Decimal
Answer: c Answer: a
Explanation: The stack segment contains Explanation: Assembly language deals with
data values passed to functions and hexadecimal values only. Each decimal value
procedures within the program. The code is automatically converted to its 16-bit binary
segment defines an area in memory that equivalent and stored as a hexadecimal
stores the instruction codes. number.
195. To speed up the processor operations, 198. A latch is an example of a ___________
the processor includes some internal memory a) Monostable multivibrator
storage locations, called ___________ b) Astable multivibrator
a) Drives

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 COMPUTER SYSTEM ARCHITECTURE UNIT – 2 MCQs
c) Bistable multivibrator 202. How many types of latches are
d) 555 timer ___________
Answer: c a) 4
Explanation: A latch is an example of a b) 3
bistable multivibrator. A Bistable c) 2
multivibrator is one in which the circuit is d) 5
stable in either of two states. It can be flipped Answer: a
from one state to the other state and vice- Explanation: There are four types of latches:
versa. SR latch, D latch, JK latch and T latch. D latch
199. Latch is a device with ___________ is a modified form of SR latch whereas, T
a) One stable state latch is an advanced form of JK latch.
b) Two stable state 203. The full form of SR is ___________
c) Three stable state a) System rated
d) Infinite stable states b) Set reset
Answer: b c) Set ready
Explanation: Since, a latch works on the d) Set Rated
principal of bistable multivibrator. A Bistable Answer: b
multivibrator is one in which the circuit is Explanation: The full form of SR is set/reset.
stable in either of two states. It can be flipped It is a type of latch having two stable states.
from one state to the other state and vice- 204. The SR latch consists of ___________
versa. So a latch has two stable states. a) 1 input
200. Why latches are called a memory b) 2 inputs
devices? c) 3 inputs
a) It has capability to stare 8 bits of data d) 4 inputs
b) It has internal memory of 4 bit Answer: b
c) It can store one bit of data Explanation: SR or Set-Reset latch is the
d) It can store infinite amount of data simplest type of bistable multivibrator having
Answer: c two stable states.
Explanation: Latches can be memory devices, The diagram of SR latch is shown below:
and can store one bit of data for as long as
the device is powered. Once device is turned
off, the memory gets refreshed.
201. Two stable states of latches are
___________
a) Astable & Monostable
b) Low input & high output
c) High output & low output 205. The outputs of SR latch are ___________
d) Low output & high input a) x and y
Answer: c b) a and b
Explanation: A latch has two stable states, c) s and r
following the principle of Bistable d) q and q’
Multivibrator. There are two stable states of Answer: d
latches and these states are high-output and Explanation: SR or Set-Reset latch is the
low-output. simplest type of bistable multivibrator having

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 COMPUTER SYSTEM ARCHITECTURE UNIT – 2 MCQs
two stable states. The inputs of SR latch are s from the diagram:
and r while outputs are q and q’. It is clear
from the diagram:

209. When a high is applied to the Set line of

. an SR latch, then ___________
206. The NAND latch works when both inputs a) Q output goes high
are ___________ b) Q’ output goes high
a) 1 c) Q output goes low
b) 0 d) Both Q and Q’ go high
c) Inverted Answer: a
d) Don’t cares Explanation: S input of a SR latch is directly
Answer: a connected to the output Q. So, when a high is
Explanation: The NAND latch works when applied Q output goes high and Q’ low.
both inputs are 1. Since, both of the inputs 210. When both inputs of SR latches are low,
are inverted in a NAND latch. the latch ___________
207. The first step of analysis procedure of SR a) Q output goes high
latch is to ___________ b) Q’ output goes high
a) label inputs c) It remains in its previously set or reset
b) label outputs state
c) label states d) it goes to its next set or reset state
d) label tables Answer: c
Answer: b Explanation: When both inputs of SR latches
Explanation: All flip flops have at least one are low, the latch remains in it’s present
output labeled Q (i.e. inverted). This is so state. There is no change in the output.
because the flip flops have inverting gates 211. When both inputs of SR latches are high,
inside them, hence in order to have both Q the latch goes ___________
and Q complement available, we have atleast a) Unstable
one output labelled. b) Stable
208. The inputs of SR latch are ___________ c) Metastable
a) x and y d) Bistable
b) a and b Answer: c
c) s and r Explanation: When both gates are identical
d) j and k and this is “metastable”, and the device will
be in an undefined state for an indefinite
Answer: c period.
Explanation: SR or Set-Reset latch is the 212. Latches constructed with NOR and
simplest type of bistable multivibrator having NAND gates tend to remain in the latched
two stable states. The inputs of SR latch are s condition due to which configuration
and r while outputs are q and q’. It is clear feature?

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 COMPUTER SYSTEM ARCHITECTURE UNIT – 2 MCQs
a) Low input voltages K=1->0->1(1 cycle complete). The J & K flip-
b) Synchronous operation flop has 4 stable states: Latch, Reset, Set and
c) Gate impedance Toggle.
d) Cross coupling 216. Which of the following is correct for a
Answer: d gated D-type flip-flop?
Explanation: Latch is a type of bistable a) The Q output is either SET or RESET as
multivibrator having two stable states. Both soon as the D input goes HIGH or LOW
inputs of a latch are directly connected to the b) The output complement follows the input
other’s output. Such types of structure is when enabled
called cross coupling and due to which c) Only one of the inputs can be HIGH at a
latches remain in the latched condition. time
213. One example of the use of an S-R flip- d) The output toggles if one of the inputs is
flop is as ___________ held HIGH
a) Transition pulse generator Answer: a
b) Racer Explanation: In D flip flop, when the clock is
c) Switch debouncer high then the output depends on the input
d) Astable oscillator otherwise reminds previous output. In a state
Answer: c of clock high, when D is high the output Q
Explanation: The SR flip-flop is very effective also high, if D is ‘0’ then output is also zero.
in removing the effects of switch bounce, Like SR flip-flop, the D-flip-flop also have an
which is the unwanted noise caused during invalid state at both inputs being 1.
the switching of electronic devices. 217. A basic S-R flip-flop can be constructed
214. The truth table for an S-R flip-flop has by cross-coupling of which basic logic gates?
how many VALID entries? a) AND or OR gates
a) 1 b) XOR or XNOR gates
b) 2 c) NOR or NAND gates
c) 3 d) AND or NOR gates
d) 4 Answer: c
Answer: c Explanation: The basic S-R flip-flop can be
Explanation: The SR flip-flop actually has constructed by cross coupling of NOR or
three inputs, Set, Reset and its current state. NAND gates. Cross coupling means the
The Invalid or Undefined State occurs at both output of second gate is fed to the input of
S and R being at 1. first gate and vice-versa.
215. When both inputs of a J-K flip-flop cycle, 218. The logic circuits whose outputs at any
the output will ___________ instant of time depends only on the present
a) Be invalid input but also on the past outputs are called
b) Change a) Combinational circuits
c) Not change b) Sequential circuits
d) Toggle c) Latches
Answer: c d) Flip-flops
Explanation: After one cycle the value of Answer: b
each input comes to the same value. Eg: Explanation: In sequential circuits, the output
Assume J=0 and K=1. After 1 cycle, it signals are fed back to the input side. So, The
becomes as J=0->1->0(1 cycle complete) and circuits whose outputs at any instant of time

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 COMPUTER SYSTEM ARCHITECTURE UNIT – 2 MCQs
depends only on the present input but also 222. The basic latch consists of ___________
on the past outputs are called sequential a) Two inverters
circuits. Unlike sequential circuits, if output b) Two comparators
depends only on the present state, then it’s c) Two amplifiers
known as combinational circuits. d) Two adders
219. Whose operations are more faster Answer: a
among the following? Explanation: The basic latch consists of two
a) Combinational circuits inverters. It is in the sense that if the output
b) Sequential circuits Q = 0 then the second output Q’ = 1 and vice
c) Latches versa.
d) Flip-flops 223. In S-R flip-flop, if Q = 0 the output is said
Answer: a to be ___________
Explanation: Combinational circuits are often a) Set
faster than sequential circuits. Since, the b) Reset
combinational circuits do not require c) Previous state
memory elements whereas the sequential d) Current state
circuits need memory devices to perform Answer: b
their operations in sequence. Latches and Explanation: In S-R flip-flop, if Q = 0 the
Flip-flops come under sequential circuits. output is said to be reset and set for Q = 1.
220. How many types of sequential circuits 224. What is a trigger pulse?
are? a) A pulse that starts a cycle of operation
a) 2 b) A pulse that reverses the cycle of
b) 3 operation
c) 4 c) A pulse that prevents a cycle of operation
d) 5 d) A pulse that enhances a cycle of operation
Answer: a Answer: a
Explanation: There are two type of Explanation: Trigger pulse is defined as a
sequential circuits viz., (i) synchronous or pulse that starts a cycle of operation.
clocked and (ii) asynchronous or unclocked. 225. The circuits of NOR based S-R latch
Synchronous Sequential Circuits are triggered classified as asynchronous sequential circuits,
in the presence of a clock signal, whereas, why?
Asynchronous Sequential Circuits function in a) Because of inverted outputs
the absence of a clock signal. b) Because of triggering functionality
221. The sequential circuit is also called c) Because of cross-coupled connection
___________ d) Because of inverted outputs & triggering
a) Flip-flop functionality
b) Latch Answer: c
c) Strobe Explanation: The cross-coupled connections
d) Adder from the output of one gate to the input of
Answer: b the other gate constitute a feedback path.
Explanation: The sequential circuit is also For this reason, the circuits of NOR based S-R
called a latch because both are a memory latch classified as asynchronous sequential
cell, which are capable of storing one bit of circuits. Moreover, they are referred to as
information.

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 COMPUTER SYSTEM ARCHITECTURE UNIT – 2 MCQs
asynchronous because they function in the will count till 22-1 = 3. Thus, it will count from
absence of a clock pulse. 0 to 3.
226. In digital logic, a counter is a device 229. How many types of the counter are
which ____________ there?
a) Counts the number of outputs a) 2
b) Stores the number of times a particular b) 3
event or process has occurred c) 4
c) Stores the number of times a clock pulse d) 5
rises and falls Answer: b
d) Counts the number of inputs Explanation: Counters are of 3 types, namely,
Answer: b (i)asynchronous/synchronous, (ii)single and
Explanation: In digital logic and computing, a multi-mode & (iii)modulus counter. These
counter is a device which stores (and further can be subdivided into Ring Counter,
sometimes displays) the number of times a Johnson Counter, Cascade Counter, Up/Down
particular event or process has occurred, Counter and such like.
often in relationship to a clock signal. 230. A decimal counter has ______ states.
227. A counter circuit is usually constructed a) 5
of ____________ b) 10
a) A number of latches connected in cascade c) 15
form d) 20
b) A number of NAND gates connected in Answer: b
cascade form Explanation: Decimal counter is also known
c) A number of flip-flops connected in as 10 stage counter. So, it has 10 states. It is
cascade also known as Decade Counter counting from
d) A number of NOR gates connected in 0 to 9.
cascade form 231. Ripple counters are also called
Answer: c ____________
Explanation: A counter circuit is usually a) SSI counters
constructed of a number of flip-flops b) Asynchronous counters
connected in cascade. Preferably, JK Flip-flops c) Synchronous counters
are used to construct counters and registers. d) VLSI counters
228. What is the maximum possible range of Answer: b
bit-count specifically in n-bit binary counter Explanation: Ripple counters are also called
consisting of ‘n’ number of flip-flops? asynchronous counter. In Asynchronous
a) 0 to 2n counters, only the first flip-flop is connected
b) 0 to 2n + 1 to an external clock while the rest of the flip-
c) 0 to 2n – 1 flops have their preceding flip-flop output as
d) 0 to 2n+1/2 clock to them.
Answer: c 232. Synchronous counter is a type of
Explanation: The maximum possible range of ____________
bit-count specifically in n-bit binary counter a) SSI counters
consisting of ‘n’ number of flip-flops is 0 to b) LSI counters
2n-1. For say, there is a 2-bit counter, then it c) MSI counters
d) VLSI counters

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 COMPUTER SYSTEM ARCHITECTURE UNIT – 2 MCQs
Answer: c d) The group of flip-flops suitable for storing
Explanation: Synchronous Counter is a binary information
Medium Scale Integrated (MSI). In Answer: d
Synchronous Counters, the clock pulse is Explanation: A register is defined as the
supplied to all the flip-flops simultaneously. group of flip-flops suitable for storing binary
233. Three decade counter would have information. Each flip-flop is a binary cell
____________ capable of storing one bit of information. The
a) 2 BCD counters data in a register can be transferred from one
b) 3 BCD counters flip-flop to another.
c) 4 BCD counters 237. The register is a type of ___________
d) 5 BCD counters a) Sequential circuit
Answer: b b) Combinational circuit
Explanation: Three decade counter has 30 c) CPU
states and a BCD counter has 10 states. So, it d) Latches
would require 3 BCD counters. Thus, a three Answer: a
decade counter will count from 0 to 29. Explanation: Register’s output depends on
234. BCD counter is also known as the past and present states of the inputs. The
____________ device which follows these properties is
a) Parallel counter termed as a sequential circuit. Whereas,
b) Decade counter combinational circuits only depend on the
c) Synchronous counter present values of inputs.
d) VLSI counter 238. How many types of registers are?
Answer: b a) 2
Explanation: BCD counter is also known as b) 3
decade counter because both have the same c) 4
number of stages and both count from 0 to 9. d) 5
235. The parallel outputs of a counter circuit Answer: c
represent the _____________ Explanation: There are 4 types of shift
a) Parallel data word registers, viz., Serial-In/Serial-Out, Serial-
b) Clock frequency In/Parallel-Out, Parallel-In/Serial-Out and
c) Counter modulus Parallel-In/Parallel-Out.
d) Clock count 239. The main difference between a register
Answer: d and a counter is ___________
Explanation: The parallel outputs of a a) A register has no specific sequence of
counter circuit represent the clock count. A states
counter counts the number of times an event b) A counter has no specific sequence of
takes place in accordance to the clock pulse. states
236. A register is defined as ___________ c) A register has capability to store one bit of
a) The group of latches for storing one bit of information but counter has n-bit
information d) A register counts data
b) The group of latches for storing n-bit of Answer: a
information Explanation: The main difference between a
c) The group of flip-flops suitable for storing register and a counter is that a register has
one bit of information

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 COMPUTER SYSTEM ARCHITECTURE UNIT – 2 MCQs
no specific sequence of states except in Answer: b
certain specialised applications. Explanation: The register capable of shifting
240. In D register, ‘D’ stands for ___________ information either to the right or to the left is
a) Delay termed as shift register. A register in which
b) Decrement data can be shifted only in one direction is
c) Data called unidirectional shift register, while if
d) Decay data can shifted in both directions, it is
Answer: c known as a bidirectional shift register.
Explanation: D stands for “data” in case of 244. How many methods of shifting of data
flip-flops and not delay. Registers are made are available?
of a group of flip-flops. a) 2
241. Registers capable of shifting in one b) 3
direction is ___________ c) 4
a) Universal shift register d) 5
b) Unidirectional shift register Answer: a
c) Unipolar shift register Explanation: There are two types of shifting
d) Unique shift register of data are available and these are serial
Answer: b shifting & parallel shifting.
Explanation: The register capable of shifting 245. In serial shifting method, data shifting
in one direction is unidirectional shift occurs ____________
register. The register capable of shifting in a) One bit at a time
both directions is known as a bidirectional b) simultaneously
shift register. c) Two bit at a time
242. A register that is used to store binary d) Four bit at a time
information is called ___________ Answer: a
a) Data register Explanation: As the name suggests serial
b) Binary register shifting, it means that data shifting will take
c) Shift register place one bit at a time for each clock pulse in
d) D – Register a serial fashion. While in parallel shifting,
Answer: b shifting will take place with all bits
Explanation: A register that is used to store simultaneously for each clock pulse in a
binary information is called a binary register. parallel fashion.
A register in which data can be shifted is 246. Memory is a/an ___________
called shift register. a) Device to collect data from other computer
243. A shift register is defined as b) Block of data to keep data separately
___________ c) Indispensable part of computer
a) The register capable of shifting information d) Device to connect through all over the
to another register world
b) The register capable of shifting information Answer: c
either to the right or to the left Explanation: Memory is an indispensable unit
c) The register capable of shifting information of a computer and microprocessor based
to the right only systems which stores permanent or
d) The register capable of shifting information temporary data.
to the left only

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 COMPUTER SYSTEM ARCHITECTURE UNIT – 2 MCQs
247. The instruction used in a program for c) An automatic keyboard input
executing them is stored in the __________ d) An automatic mouse input
a) CPU Answer: b
b) Control Unit Explanation: The very first computer memory
c) Memory consisted of a minute magnetic toroid, which
d) Microprocessor required large, bulky circuit boards stored in
Answer: c large cabinates.
Explanation: All of the program and the 252. A minute magnetic toroid is also called
instructions are stored in the memory. The as __________
processor fetches it as and when required. a) Large memory
248. A flip flop stores __________ b) Small memory
a) 10 bit of information c) Core memory
b) 1 bit of information d) Both small and large memory
c) 2 bit of information Answer: c
d) 3-bit information Explanation: A minute magnetic toroid is also
Answer: b called as core memory which is made up of a
Explanation: A flip-flop has capability to store semiconductor. A semiconductor is a device
1 bit of information. It can be used further whose electrical conductivity lies between
after erasing previous information. that of conductor and insulator.
249. A register is able to hold __________ 253. Which one of the following has
a) Data capability to store data in extremely high
b) Word densities?
c) Nibble a) Register
d) Both data and word b) Capacitor
Answer: b c) Semiconductor
Explanation: Register is also a part of d) Flip-Flop
memory inside a computer. It stands there to Answer: c
hold a word. A word is a group of 16-bits or 2- Explanation: Semiconductor has capability to
bytes. store data in extremely high densities.
250. A register file holds __________ 254. A large memory is compressed into a
a) A large number of word of information small one by using __________
b) A small number of word of information a) LSI semiconductor
c) A large number of programs b) VLSI semiconductor
d) A modest number of words of information c) CDR semiconductor
Answer: d d) SSI semiconductor
Explanation: A register file is different from a Answer: b
simple register because of capability to hold a Explanation: VLSI (Very Large Scale
modest number of words of information. A Integration) semiconductor is used in modern
word is a group of 16-bits or 2-bytes. computers to short the size of memory.
251. The very first computer memory 255. VLSI chip utilizes __________
consisted of __________ a) NMOS
a) A small display b) CMOS
b) A large memory storage equipment c) BJT
d) All of the Mentioned

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 COMPUTER SYSTEM ARCHITECTURE UNIT – 2 MCQs
Answer: d 260. A ROM is defined as __________
Explanation: VLSI (Very Large Scale a) Read Out Memory
Integration) is a memory chip which is made b) Read Once Memory
up of NMOS, CMOS, BJT, and BiCMOS. It can c) Read Only Memory
include 10,000 to 100,000 gates per IC. d) Read One Memory
256. CD-ROM refers to __________ View Answer
a) Floppy disk Answer: c
b) Compact Disk-Read Only Memory Explanation: A ROM is defined as Read Only
c) Compressed Disk-Read Only Memory Memory which can read the instruction
d) Compressed Disk- Random Access Memory stored in a computer.
Answer: b 261. Which of the circuits in figure (a to d) is
Explanation: CD-ROM refers to Compact the sum-of-products implementation of
Disk-Read Only Memory. figure (e)?
257. Data stored in an electronic memory cell
can be accessed at random and on demand
using __________
a) Memory addressing
b) Direct addressing
c) Indirect addressing
d) Control Unit
Answer: b
Explanation: Direct addressing eliminates the
need to process a large stream of irrelevant
data in order to the desired data word.
258. The full form of PLD is __________
a) Programmable Large Device
b) Programmable Long Device
c) Programmable Logic Device
d) Programmable Lengthy Device
Answer: c
Explanation: The full form of PLD is
Programmable Logic Device.
259. The evolution of PLD began with
__________
a) EROM
b) RAM
c) PROM
d) EEPROM
a) a
Answer: a
b) b
Explanation: The evolution of PLD
c) c
(Programmable Logic Device) began with
d) d
Programmable Read Only Memory (i.e.
Answer: d
PROM). Here, the ROM can be externally
Explanation: SOP means Sum Of Products
programmed as per the user.

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 COMPUTER SYSTEM ARCHITECTURE UNIT – 2 MCQs
form which represents the sum of product 264. What type of logic circuit is represented
terms having variables in complemented as by the figure shown below?
well as in uncomplemented form. Here, the
diagram of d contains the OR gate followed
by the AND gates, so it is in SOP form.
262. Which of the following logic expressions
represents the logic diagram shown?

a) XOR
b) XNOR
c) AND
d) XAND
Answer: b
Explanation: After solving the circuit we get
a) X=AB’+A’B (A’B’)+AB as output, which is XNOR
b) X=(AB)’+AB operation. Thus, it will produce 1 when inputs
c) X=(AB)’+A’B’ are even number of 1s or all 0s, and produce
d) X=A’B’+AB 0 when input is odd number of 1s.
Answer: d 265. For a two-input XNOR gate, with the
Explanation: 1st output of AND gate is = A’B’ input waveforms as shown below, which
2nd AND gate’s output is = AB and, output waveform is correct?
OR gate’s output is = (A’B’)+(AB) = AB + A’B’.
263. The device shown here is most likely a
________

a) d
a) Comparator
b) a
b) Multiplexer
c) c
c) Inverter
d) b
d) Demultiplexer
Answer: a
Answer: d
Explanation: When both inputs are same
Explanation: The given diagram is
then the o/p is high for a XNOR gate.
demultiplexer, because it takes single input &
i.e., A B O/P
gives many outputs. A demultiplexer is a
001
combinational circuit that takes a single
010
output and latches it to multiple outputs
100
depending on the select lines.

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 COMPUTER SYSTEM ARCHITECTURE UNIT – 2 MCQs
1 1 1. b) All are LOW
Thus, it will produce 1 when inputs are even c) All but Y0 are LOW
number of 1s or all 0s, and produce 0 when d) All but Y0 are HIGH
input is odd number of 1s. Answer: d
266. Which of the following combinations of Explanation: In the given diagram, S0 and S1
logic gates can decode binary 1101? are selection bits. So,
a) One 4-input AND gate I/P S0 S1 O/P
b) One 4-input AND gate, one inverter D = 0 0 0 Y0
c) One 4-input AND gate, one OR gate D = 0 0 1 Y1
d) One 4-input NAND gate, one inverter D = 0 1 0 Y2
Answer: b D = 0 1 1 Y3
Explanation: For decoding any number Hence, inputs are S0 and S1 are Low means 0,
output must be high for that code and this is so output is Y0 and rest all are HIGH.
possible in One 4-input NAND gate, one 269. The carry propagation can be expressed
inverter option only. A decoder is a as ________
combinational circuit that converts binary a) Cp = AB
data to n-coded data upto 2n outputs. b) Cp = A + B
267. What is the indication of a short to c) All but Y0 are LOW
ground in the output of a driving gate? d) All but Y0 are HIGH
a) Only the output of the defective gate is Answer: b
affected Explanation: This happens in parallel adders
b) There is a signal loss to all load gates (where we try to add numbers in parallel via
c) The node may be stuck in either the HIGH more than one adders). A carry propagation
or the LOW state occurs when carry from one adder needs to
d) The affected node will be stuck in the HIGH be forwarded to other adder and that second
state adder is holding the computation (addition)
Answer: b because carry from first adder has not come
Explanation: Short to ground in the output of yet. So, there is a slight delay for second
a driving gate indicates of a signal loss to all adder and this is known as carry propagation.
load gates. This results in information being 270. 3 bits full adder contains ________
disrupted and loss of data. a) 3 combinational inputs
268. For the device shown here, assume the b) 4 combinational inputs
D input is LOW, both S inputs are LOW and c) 6 combinational inputs
the input is LOW. What is the status of the Y’ d) 8 combinational inputs
outputs? Answer: d
Explanation: Full Adder is a combinational
circuit with 3 input bits and 2 output bits
CARRY and SUM. Three bits full adder
requires 23 = 8 combinational circuits.
271. The ‘heart’ of the processor which
performs many different operations
_____________
a) Arithmetic and logic unit
a) All are HIGH b) Motherboard

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 COMPUTER SYSTEM ARCHITECTURE UNIT – 2 MCQs
c) Control Unit negative else if it is 0, the number is positive.
d) Memory Here, +1=0001 and for -1=1001.
Answer: a 275. IEEE stands for ___________
Explanation: The Arithmetic and logic unit a) Instantaneous Electrical Engineering
performs all the basic operations of the b) Institute of Emerging Electrical Engineers
computer system. It performs all the c) Institute of Emerging Electronic Engineers
arithmetic(+,-,*,/,etc) as well as the logical d) Institute of Electrical and electronics
operations( AND, OR, NOT, etc.). engineers
272. ALU is the place where the actual Answer: d
executions of instructions take place during Explanation: The IEEE is an organization of
the processing operation. professionals in the field of electronics and
a) True electrical engineering. IEEE has given certain
b) False standards of its own which are followed in
Answer: a the field of computer science and electrical
Explanation: ALU is a combinational engineering.
electronic circuit which basically performs all 276. The ALU gives the output of the
the logical or the bitwise operations and the operations and the output is stored in the
arithmetic operations. Therefore, it is the ________
place where the actual executions of a) Memory Devices
instructions take place. b) Registers
273. Which of the following is not a bitwise c) Flags
operator? d) Output Unit
a) | Answer: b
b) ^ Explanation: Any output generated by the
c) . ALU gets stored in the registers. The registers
d) << are the temporary memory locations within
Answer: c the processor that are connected by signal
Explanation: All except the dot(.) operator paths to the CPU.
are bitwise operators. 278. The process of division on memory
| : Bitwise OR spaces is called ______________
^ : Bitwise XOR a) Paging
<< : Shift Left b) Segmentation
274. The sign magnitude representation of -1 c) Bifurcation
is __________ d) Dynamic Division
a) 0001 Answer: b
b) 1110 Explanation: The memory space is divided
c) 1000 into segments of dynamic size. The
d) 1001 programmer is aware of the segmentation
Answer: d and can reallocate the segments accordingly.
Explanation: The first leftmost bit i.e. the 279. Number of bits in ALU is _________
most significant bit in the sign magnitude a) 4
represents if the number is positive or b) 8
negative. If the MSB is 1, the number is c) 16
d) 2

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 COMPUTER SYSTEM ARCHITECTURE UNIT – 2 MCQs
Answer: c a) Positive
Explanation: Arithmetic and Logic Unit b) Negative
consists of 16bits. They perform certain c) Double
Arithmetic and bitwise operations (add, d) Unsigned
subtract, AND, OR, XOR, Increment, Answer: c
decrement, shift). Explanation: The zoned format can represent
280. Which flag indicates the number of 1 bit numeric values of type Positive, negative and
that results from an operation? unsigned numbers. A sign indicator is used in
a) Zero the zone position of the rightmost digit.
b) Parity 284. The sign indicator of unsigned numbers
c) Auxiliary is ____________
d) Carry a) C
Answer: b b) D
Explanation: The parity flag indicates the c) F
number of 1 bit in any operation. The d) X
resultant bit is called the parity bit. The main Answer: c
aim of the parity bit is to check for errors. Explanation: A sign indicator is used in the
281. The bitwise complement of 0 is zone position of the rightmost digit. A sign
___________ indicator C is used for positive, D for negative
a) 00000001 and F is used for negative numbers.
b) 10000000 285. The EBCDIC value of the number 345 in
c) 11111111 zoned format is __________
d) 11111110 a) F3F4F5
Answer: c b) E3E4E5
Explanation: Bitwise complement is basically c) F3F4C5
used to convert all the 0 digits to 1 and the 1s d) F3F4D5
to 0s. Answer: a
So, for 0 = 00000000(in 8-bits) ::: Explanation: F is used for the representation
11111111(1s complement). The bitwise of unsigned numbers therefore, F3F4F5
complement is often referred to as the 1s represents 345. F3F4C5 represents +345 .
complement. F3F4D5 represents -345.
282. Unicode provides a consistent way of 286. Which of the following logic families has
encoding multilingual plain text. the highest maximum clock frequency?
a) True a) S-TTL
b) False b) AS-TTL
Answer: a c) HS-TTL
Explanation: Unicode defines codes for d) HCMOS
characters used in all major languages of the Answer: b
world. Explanation: AS-TTL (Advanced Schottky) has
It is a coding system which supports almost a maximum clock frequency of 105 MHz. S-
all the languages. It defines special codes for TTL (Schottky High Speed TTL) has 100 MHz.
different characters, symbols, diacritics, etc. Found nothing as HS-TTL. There are H and S
283. Which of the following is not a type of separate TTL. HCMOS has 50 MHz clock
numeric value in zoned format? frequency.

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 COMPUTER SYSTEM ARCHITECTURE UNIT – 2 MCQs
287. Why is the fan-out of CMOS gates output. Logic circuits that are designated as
frequency dependent? buffers, drivers or buffer/drivers are designed
a) Each CMOS input gate has a specific to have a greater current/voltage capability
propagation time and this limits the number than an ordinary logic circuit.
of different gates that can be connected to 289. Which of the following will not normally
the output of a CMOS gate be found on a data sheet?
b) When the frequency reaches the critical a) Minimum HIGH level output voltage
value the gate will only be capable of b) Maximum LOW level output voltage
delivering 70% of the normal output voltage c) Minimum LOW level output voltage
and consequently the output power will be d) Maximum HIGH level input current
one-half of normal and this defines the upper Answer: c
operating frequency Explanation: Minimum LOW level output
c) The higher number of gates attached to voltage will not normally be found on a data
the output the more frequently they will have sheet.
to be serviced thus reducing the frequency at 290. Which of the following logic families has
which each will be serviced with an input the shortest propagation delay?
signal a) S-TTL
d) The input gates of the FETs are b) AS-TTL
predominantly capacitive and as the signal c) HS-TTL
frequency increases the capacitive loading d) HCMOS
also increases thereby limiting the number of
Answer: b
loads that may be attached to the output of
Explanation: AS-TTL (Advanced Schottky) has
the driving gate
a maximum clock frequency that is 105 MHz.
Answer: d So, the propagation delay will be given by
Explanation: Fan out is the measure of 1/105 sec which is the lowest one. It is
maximum number of inputs that a single logic followed by S-TTL and HCMOS in terms of
gate output can drive. Actually power increasing propagation delay.
dissipation in CMOS circuits depends on clock
291. ARM stands for _____________
frequency. As the frequency increases Pd also
a) Advanced Rate Machines
increases so fan-out depends on frequency.
b) Advanced RISC Machines
288. Logic circuits that are designated as c) Artificial Running Machines
buffers, drivers or buffers/drivers are d) Aviary Running Machines
designed to have:
Answer: b
a) A greater current/voltage capability than
Explanation: ARM is a type of system
an ordinary logic circuit
architecture.
b) Greater input current/voltage capability
than an ordinary logic circuit 292. The main importance of ARM micro-
c) A smaller output current/voltage capability processors is providing operation with
than an ordinary logic ______
d) Greater the input and output a) Low cost and low power consumption
current/voltage capability than an ordinary b) Higher degree of multi-tasking
logic circuit c) Lower error or glitches
d) Efficient memory management
Answer: a
Explanation: Buffer circuits are usually Answer: a
incorporated to isolate the input from the Explanation: The Stand alone feature of the

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 COMPUTER SYSTEM ARCHITECTURE UNIT – 2 MCQs
ARM processors is that they’re economically Answer: b
viable. Explanation: It is called so because it
293. ARM processors where basically performs its operation at the assembly level.
designed for _______ 298. The fetch and execution cycles are
a) Main frame systems interleaved with the help of ________
b) Distributed systems a) Modification in processor architecture
c) Mobile systems b) Clock
d) Super computers c) Special unit
Answer: c d) Control unit
Explanation: These ARM processors are Answer: b
designed for handheld devices. Explanation: The time cycle of the clock is
294. The ARM processors don’t support Byte adjusted to perform the interleaving.
addressability. 299. Each stage in pipelining should be
a) True completed within ___________ cycle.
b) False a) 1
Answer: b b) 2
Explanation: The ability to store data in the c) 3
form of consecutive bytes. d) 4
295. The address space in ARM is Answer: a
___________ Explanation: The stages in the pipelining
a) 224 should get completed within one cycle to
b) 264 increase the speed of performance.
c) 216 300. In pipelining the task which requires the
d) 232 least time is performed first.
Answer: d a) True
Explanation: None. b) False
296. ______ have been developed specifically Answer: b
for pipelined systems. Explanation: This is done to avoid starvation
a) Utility software of the longer task.
b) Speed up utilities 301. If a unit completes its task before the
c) Optimizing compilers allotted time period, then _______
d) None of the mentioned a) It’ll perform some other task in the
Answer: c remaining time
Explanation: The compilers which are b) Its time gets reallocated to a different task
designed to remove redundant parts of the c) It’ll remain idle for the remaining time
code are called as optimizing compilers. d) None of the mentioned
297. The pipelining process is also called as Answer: c
______ Explanation: None.
a) Superscalar operation 302. To increase the speed of memory access
b) Assembly line operation in pipelining, we make use of _______
c) Von Neumann cycle a) Special memory locations
d) None of the mentioned b) Special purpose registers
c) Cache
d) Buffers
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 COMPUTER SYSTEM ARCHITECTURE UNIT – 2 MCQs
Answer: c a) Height factors
Explanation: By using the cache we can b) Size factors
reduce the speed of memory access by a c) Scale factors
factor of 10. d) None of the mentioned
303. The periods of time when the unit is idle Answer: c
is called as _____ Explanation: These are called as scale factors
a) Stalls cause they’re responsible in determining the
b) Bubbles degree of specification of a number.
c) Hazards 308. If the decimal point is placed to the right
d) Both Stalls and Bubbles of the first significant digit, then the number
Answer: d is called ________
Explanation: The stalls are a type of hazards a) Orthogonal
that affect a pipelined system. b) Normalized
304. The contention for the usage of a c) Determinate
hardware device is called ______ d) None of the mentioned
a) Structural hazard Answer: b
b) Stalk Explanation: None.
c) Deadlock 309. ________ constitute the representation
d) None of the mentioned of the floating number.
Answer: a a) Sign
Explanation: None. b) Significant digits
305. The situation wherein the data of c) Scale factor
operands are not available is called ______ d) All of the mentioned
a) Data hazard Answer: d
b) Stock Explanation: The following factors are
c) Deadlock responsible for the representation of the
d) Structural hazard number.
Answer: a 310. The sign followed by the string of digits
Explanation: Data hazards are generally is called as ______
caused when the data is not ready on the a) Significant
destination side. b) Determinant
306. The decimal numbers represented in the c) Mantissa
computer are called as floating point d) Exponent
numbers, as the decimal point floats through Answer: c
the number. Explanation: The mantissa also consists of
a) True the decimal point.
b) False 311. In IEEE 32-bit representations, the
Answer: a mantissa of the fraction is said to occupy
Explanation: By doing this the computer is ______ bits.
capable of accommodating the large float a) 24
numbers also. b) 23
307. The numbers written to the power of 10 c) 20
in the representation of decimal numbers are d) 16
called as _____
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 COMPUTER SYSTEM ARCHITECTURE UNIT – 2 MCQs
Answer: b c) The amount of data transfer possible
Explanation: The mantissa is made to occupy d) None of the mentioned
23 bits, with 8 bit exponent. Answer: d
312. The normalized representation of Explanation: DMA is an approach of
0.0010110 * 2 9 is _______ performing data transfers in bulk between
a) 0 10001000 0010110 memory and the external device without the
b) 0 10000101 0110 intervention of the processor.
c) 0 10101010 1110 317. The DMA transfers are performed by a
d) 0 11110100 11100 control circuit called as __________
Answer: b a) Device interface
Explanation: Normalized representation is b) DMA controller
done by shifting the decimal point. c) Data controller
313. The 32 bit representation of the decimal d) Overlooker
number is called as ___________ Answer: b
a) Double-precision Explanation: The Controller performs the
b) Single-precision functions that would normally be carried out
c) Extended format by the processor.
d) None of the mentioned 318. In DMA transfers, the required signals
Answer: b and addresses are given by the __________
Explanation: None. a) Processor
314. In 32 bit representation the scale factor b) Device drivers
as a range of ________ c) DMA controllers
a) -128 to 127 d) The program itself
b) -256 to 255 Answer: c
c) 0 to 255 Explanation: The DMA controller acts as a
d) None of the mentioned processor for DMA transfers and overlooks
Answer: a the entire process.
Explanation: Since the exponent field has 319. After the completion of the DMA
only 8 bits to store the value. transfer, the processor is notified by
315. In double precision format, the size of __________
the mantissa is ______ a) Acknowledge signal
a) 32 bit b) Interrupt signal
b) 52 bit c) WMFC signal
c) 64 bit d) None of the mentioned
d) 72 bit Answer: b
Answer: b Explanation: The controller raises an
Explanation: The double precision format is interrupt signal to notify the processor that
also called as 64 bit representation. the transfer was complete.
316. The DMA differs from the interrupt 320. The DMA controller has _______
mode by __________ registers.
a) The involvement of the processor for the a) 4
operation b) 2
b) The method of accessing the I/O devices c) 3
d) 1

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 COMPUTER SYSTEM ARCHITECTURE UNIT – 2 MCQs
Answer: c a) Cycle stealing
Explanation: The Controller uses the registers b) Memory stealing
to store the starting address, word count and c) Memory Con
the status of the operation. d) Burst mode
330. When the R/W bit of the status register Answer: d
of the DMA controller is set to 1. Explanation: The controller is given full
a) Read operation is performed control of the memory access cycles and can
b) Write operation is performed transfer blocks at a faster rate.
c) Read & Write operation is performed 335. The side of the interface circuits, that
d) None of the mentioned has the data path and the control signals to
Answer: a transfer data between interface and device is
Explanation: None. _____
331. The controller is connected to the ____ a) BUS side
a) Processor BUS b) Port side
b) System BUS c) Hardwell side
c) External BUS d) Software side
d) None of the mentioned Answer: b
Answer: b Explanation: This side connects the device to
Explanation: The controller is directly the motherboard.
connected to the system BUS to provide 336. What is the interface circuit?
faster transfer of data. a) Helps in installing of the software driver for
332. Can a single DMA controller perform the device
operations on two different disks b) Houses the buffer that helps in data
simultaneously? transfer
a) True c) Helps in the decoding of the address on the
b) False address BUs
Answer: a d) None of the mentioned
Explanation: The DMA controller can perform Answer: c
operations on two different disks if the Explanation: Once the address is put on the
appropriate details are known. BUS the interface circuit decodes the address
333. The technique whereby the DMA and uses the buffer space to transfer data.
controller steals the access cycles of the 337. The conversion from parallel to serial
processor to operate is called __________ data transmission and vice versa takes place
a) Fast conning inside the interface circuits.
b) Memory Con a) True
c) Cycle stealing b) False
d) Memory stealing Answer: a
Answer: c Explanation: By doing this the interface
Explanation: The controller takes over the circuits provide a better interconnection
processor’s access cycles and performs between devices.
memory operations. 338. The interrupt-request line is a part of the
334. The technique where the controller is ___________
given complete access to main memory is a) Data line
__________ b) Control line

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 COMPUTER SYSTEM ARCHITECTURE UNIT – 2 MCQs
c) Address line b) Interrupt latency
d) None of the mentioned c) Cycle time
Answer: b d) Switching time
Explanation: The Interrupt-request line is a Answer: b
control line along which the device is allowed Explanation: The delay in servicing of an
to send the interrupt signal. interrupt happens due to the time is taken
339. The return address from the interrupt- for contact switch to take place.
service routine is stored on the ___________ 343. Interrupts form an important part of
a) System heap _____ systems.
b) Processor register a) Batch processing
c) Processor stack b) Multitasking
d) Memory c) Real-time processing
Answer: c d) Multi-user
Explanation: The Processor after servicing Answer: c
the interrupts as to load the address of the Explanation: This forms an important part of
previous process and this address is stored in the Real time system since if a process arrives
the stack. with greater priority then it raises an
340. The signal sent to the device from the interrupt and the other process is stopped
processor to the device after receiving an and the interrupt will be serviced.
interrupt is ___________ 344. A single Interrupt line can be used to
a) Interrupt-acknowledge service n different devices.
b) Return signal a) True
c) Service signal b) False
d) Permission signal Answer: a
Answer: a Explanation: None.
Explanation: The Processor upon receiving 345. *@Ac# is a type of ________________
the interrupt should let the device know that data.
its request is received. a) Symbolic
341. When the process is returned after an b) Alphanumeric
interrupt service ______ should be loaded c) Alphabetic
again. d) Numeric
i) Register contents
ii) Condition codes Answer: b
iii) Stack contents Explanation: Alphanumeric data consists of
iv) Return addresses symbols. Alphanumeric data may be a letter,
a) i, iv either in uppercase or lowercase or some
b) ii, iii and iv special symbols like #,^,*,(, etc.)
c) iii, iv
d) i, ii 346. Which of the following is not a valid
Answer: d representation in bits?
Explanation: None. a) 8-bit
342. The time between the receiver of an b) 24-bit
interrupt and its service is ______ c) 32-bit
a) Interrupt delay

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 COMPUTER SYSTEM ARCHITECTURE UNIT – 2 MCQs
d) 64-bit false. If a result gives a truth value, it is called
tautology whereas if it returns a false term, it
Answer: b is referred to as fallacy.
Explanation: There are no criteria like the 24-
bit representation of numbers. Numbers can 350. What does FORTRAN stands for?
be written in 8-bit, 16-bit, 32-bit and 64-bit as a) Formula Transfer
per the IEEE format. b) Formula Transformation
c) Formula Translation
347. What are the entities whose values can d) Format Transformation
be changed called?
a) Constants Answer: c
b) Variables Explanation: FORTRAN is a type of computer
c) Modules language. It was developed for solving
d) Tokens mathematical and scientific problems. It is
very commonly used among the scientific
Answer: b community.
Explanation: Variables are the data entities
whose values can be changed. Constants 351. The program written by the programmer
have a fixed value. Tokens are the words in high level language is called
which are easily identified by the compiler. _____________
a) Object Program
348. Which of the following is not a basic b) Source Program
data type in C language? c) Assembled Program
a) float d) Compiled Program
b) int
c) real Answer: b
d) char Explanation: The program written by the
programmer is called a source program. The
Answer: c program generated by the compiler after
Explanation: There are 5 basic data types in C compilation is called an object program. The
language: int, char, float, double, void. object program is in machine language.
Int is for the representation of integers, char
is for strings and characters, float and double 352. A standardized language used for
are for floating point numbers whereas void commercial applications.
is a valueless special data type. a) C
b) Java
349. BOOLEAN is a type of data type which c) COBOL
basically gives a tautology or fallacy. d) FORTRAN
a) True
b) False Answer: c
Explanation: COBOL is a language used in
Answer: a business and commercial applications. It
Explanation: A Boolean representation is for stands for Common Business Oriented
giving logical values. It returns either true or
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 COMPUTER SYSTEM ARCHITECTURE UNIT – 2 MCQs
Language. It is imperative, procedural as well binary system is that it requires very large
as object oriented language. string of 1’s and 0’s to represent a decimal
number. Hence, Hexadecimal systems are
353. ______________ define how the used by processors for calculation purposes
locations can be used. as it compresses the long binary strings into
a) Data types small parts.
b) Attributes 356. The decimal equivalent of the octal
c) Links number (645)8 is ______
d) Data Objects a) (450)10
b) (451)10
Answer: b c) (421)10
Explanation: Attributes can determine how d) (501)10
any location can be used. Attributes can be
type, name, component, etc. Data objects are Answer: c
the variables and constants in a program. Explanation: Octal to Decimal conversion is
obtained by multiplying 8 to the power of
354. The decimal equivalent of the binary base index along with the value at that index
number (1011.011)2 is ________ position.
a) (11.375)10 The decimal equivalent of the octal number
b) (10.123)10 (645)8 is 6 * 82 + 4 * 81 + 5 * 80 = 6 * 64 + 4 *
c) (11.175)10 8 + 5 = 384 + 32 + 5 = (421)10.
d) (9.23)10 357. The largest two digit hexadecimal
number is ________
a) (FE)16
Answer: a
b) (FD)16
Explanation: Binary to Decimal conversion is
c) (FF)16
obtained by multiplying 2 to the power of
d) (EF)16
base index along with the value at that index
position.
1 * 23 + 0 * 22 + 1 * 21 +1*20 + 0 * 2-1 +1 * 2- Answer: c
2 + 1 * 2-3 = (11.375)10 Explanation: (FE)16 is 254 in decimal system,
Hence, (1011.011)2 = (11.375)10 while (FD)16 is 253. (EF)16 is 239 in decimal
system. And, (FF)16 is 255. Thus, The largest
355. An important drawback of binary system
two-digit hexadecimal number is (FF)16.
is ________
a) It requires very large string of 1’s and 0’s to 358. Representation of hexadecimal number
represent a decimal number (6DE)H in decimal:
b) It requires sparingly small string of 1’s and a) 6 * 162 + 13 * 161 + 14 * 160
0’s to represent a decimal number b) 6 * 162 + 12 * 161 + 13 * 160
c) It requires large string of 1’s and small c) 6 * 162 + 11 * 161 + 14 * 160
string of 0’s to represent a decimal number d) 6 * 162 + 14 * 161 + 15 * 160
d) It requires small string of 1’s and large
string of 0’s to represent a decimal number Answer: a
Explanation: Hexadecimal to Decimal
Answer: a conversion is obtained by multiplying 16 to
Explanation: The most vital drawback of the power of base index along with the value

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 COMPUTER SYSTEM ARCHITECTURE UNIT – 2 MCQs
at that index position. Answer: d
In hexadecimal number D & E represents 13 Explanation:The rules for Binary Addition are
& 14 respectively. :
So, 6DE = 6 * 162 + 13 * 161 + 14 * 160. 0+0=0
359. The quantity of double word is ________ 0+1=1
a) 16 bits 1+0=1
b) 32 bits 1 + 1 = 0 ( Carry 1)
c) 4 bits 111111
d) 8 bits 101101
+011011
Answer: b _______________
Explanation: One word means 16 bits, Thus, 1001000
the quantity of double word is 32 bits.
_______________
Therefore, the addition of 101101 + 011011 =
360. What is the addition of the binary 1001000.
numbers 11011011010 and 010100101?
362. Perform binary subtraction: 101111 –
a) 0111001000
010101 = ?
b) 1100110110
a) 100100
c) 11101111111
b) 010101
d) 10011010011
c) 011010
d) 011001
Answer: c
Explanation: The rules for Binary Addition are Answer: c
: Explanation: The rules for Binary Subtraction
0+0=0 are :
0+1=1 0–0=0
1+0=1 0 – 1 = 1 ( Borrow 1)
1 + 1 = 0 ( Carry 1) 1–0=1
1 1–1=0
101111
11011011010 -010101
____________
+00010100101 011010
_______________________ _____________
11101111111 Therefore, The subtraction of 101111 –
_______________________ 010101 = 011010.
361. Perform binary addition: 101101 + 363. Binary subtraction of 100101 – 011110 is
011011 = ? a) 000111
a) 011010 b) 111000
b) 1010100 c) 010101
c) 101110 d) 101010
d) 1001000

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 COMPUTER SYSTEM ARCHITECTURE UNIT – 2 MCQs
Answer: a b) 0100110011
Explanation: The rules for Binary Subtraction c) 101111110
are : d) 0110100101
0–0=0
0 – 1 = 1 ( Borrow 1) Answer: c
1–0=1 Explanation: The rules for binary
1–1=0 multiplication are:
100101 0*0=0
-011110 0*1=0
___________ 1*0=0
000111 1*1=1
___________ 100101
Therefore, The subtraction of 100101 – x 0110
011110 = 000111. ___________
364. Perform multiplication of the binary 000000
numbers: 01001 × 01011 = ? 1001010
a) 001100011 10010100
b) 110011100 000000000
c) 010100110 __________________
d) 101010111 011011110
___________________
Answer: a
Therefore, 100101 x 0110 = 011011110.
Explanation: The rules for binary
multiplication are: 366. On multiplication of (10.10) and (01.01),
0*0=0 we get
0*1=0 a) 101.0010
1*0=0 b) 0010.101
1*1=1 c) 011.0010
d) 110.0011
01001
x01011
Answer: c
____________ Explanation: The rules for binary
01001 multiplication are:
010010 0*0=0
0000000 0*1=0
01001000 1*0=0
000000000 1*1=1
___________________ 1 0.1 0
001100011 x 0 1.0 1
___________________ __________
Therefore, 01001 × 01011 = 001100011. 1010
365. 100101 × 0110 = ? 00000
a) 1011001111 101000

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 COMPUTER SYSTEM ARCHITECTURE UNIT – 2 MCQs
0000000 Additionally, it may have one or more
_______________ operands and the op code indicates the
0 1 1.0 0 1 0 operation to be performed.
_________________ 370. The length of a register is called _______
Therefore, 10.10 x 01.01 = 011.0010. a) word limit
b) word size
367. Divide the binary numbers: 111101 ÷
c) register limit
1001 and find the remainder
d) register size
a) 0010
b) 1010 Answer: b
c) 1100 Explanation: The length of a register is called
d) 0011 word size. It tells the number of bits a
register can store.
Registers are a part of the CPU.
Answer: d
Explanation: Binary Division is accomplished 371. The _________ holds the contents of the
using long division method. accessed memory word.
a) MAR
1001)111101(11
b) MBR
1001 c) PC
__________ d) IR
01100 Answer: b
1001 Explanation: The MBR holds the contents of
___________ the accessed (read/written) memory word.
0111 MBR stands for Memory Buffer Register.
Therefore, the remainder of 111101 ÷ 1001 = 372. Which of the following is not a visible
0111. register?
368. CPU has built-in ability to execute a a) General Purpose Registers
particular set of machine instructions, called b) Address Register
as __________ c) Status Register
a) Instruction Set d) MAR
b) Registers Answer: d
c) Sequence Set Explanation: MAR or the memory address
d) User instructions register is not a visible register. This register
Answer: a is user inaccessible. It contains the address of
Explanation: An instruction is any task which the memory block to be read or written to.
is to be performed by the processor. 373. Which of the following is a data transfer
Instructions are stored in the register. instruction?
Instruction set is the set of machine a) STA 16-bit address
instructions. b) ADD A, B
369. Opcode indicates the operations to be c) MUL C, D
performed. d) RET
a) True Answer: a
b) False Explanation: The instruction STA 16-bit
Answer: a address is a data transfer instruction.
Explanation: Every instruction has an opcode. STA means Store in Accumulator.

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 COMPUTER SYSTEM ARCHITECTURE UNIT – 2 MCQs
374. What is correct instruction if you want 378. What does ASCII stand for?
the control to go to the location 2000h? a) American Standard Code for Information
a) MOV 2000h Interchange
b) MOV A, 2000h b) American Scientific Code for Information
c) JMP 2000h Interchange
d) RET 2000h c) American Scientific Code for Interchanging
Answer: c Information
Explanation: The JMP instruction is used to d) American Standard Code for Interchanging
move to a particular location. In 8085 Information
microprocessor, JMP statement tells the Answer: a
processor to go to location 2000h (here). Explanation: The ASCII codes are used to
375. What kind of a flag is the sign flag? represent the bits into symbols and vice
a) General Purpose versa. ASCII is the American Standard Code
b) Status which is used to exchange information.
c) Address 379. The decimal representation for the
d) Instruction character ‘!’ in ASCII is ____________
Answer: b a) 31
Explanation: Sign flag is a type of status b) 32
register or the flag register. It is used to c) 33
indicate the sign of certain bits. d) 34
376. The number of sign bits in a 32-bit IEEE Answer: c
format __________ Explanation: The decimal representation of a
a) 1 few basic characters are:
b) 11 33 : !
c) 9 34 : ”
d) 23 35: #
Answer: a 36 :$.
Explanation: There is only 1 sign bit in all the 380. The two types of ASCII are
standards. In a 32-bit format, there is 1 sign _____________ and ____________
bit, 8 bits for the exponent and 23 bits for the a) ASCII-4 and ASCII-8
mantissa. b) ASCII-8 and ASCII-16
377. New CPU whose instruction set includes c) ASCII-7 and ASCII-8
the instruction set of its predecessor CPU is d) ASCII-4 and ASCII-16
said to be ___________ with its predecessor. Answer: c
a) fully compatible Explanation: The two types of ASCII are
b) forward compatible ASCII-7 and ASCII-8. ASCII-7 uses 7 bits for the
c) compatible representation of numbers and ASCII-8 uses
d) backward compatible 8-bits.
Answer: d 381. Any set of digits or alphabets are
Explanation: The CPU is called backward generally referred as ______________
compatible since it contains the instruction a) Characters
set of its predecessor. Manufacturers tend to b) Symbols
group their CPUs into families having similar c) Bits
instruction set. d) Bytes

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 COMPUTER SYSTEM ARCHITECTURE UNIT – 2 MCQs
Answer: a Answer: a
Explanation: We refer to the digits and Explanation: The ASCII-8 format will have 8
alphabets generally as characters. A character bits. The zone for the character 8 is 0011 and
is generally a unit of information in the digit is 1000. Therefore, its
computers. representation is 00111000.
382. The first 128 characters are the same in 386. Binary Coding for the letter X is
both the types of ASCII i.e. ASCII-7 and ASCII- ______________
8. a) 01011000
a) True b) 00111000
b) False c) 10001000
Answer: a d) 00010100
Explanation: There are two types of ASCII Answer: a
codes: ASCII-7 and ASCII-8. ASCII-7 uses 7 bits Explanation: The binary coding for the letter
to represent a number whereas ASCII-8 uses X is 01011000. Here, 0101 is the zone
8-bits to represent a number. whereas 1000 is the digit. The alphabets from
383. The number of characters that can be P to Z have the zone 0101.
represented in ASCII-8 are ______________ 387. Express the ASCII equivalent of the
a) 128 signed binary number (00110010)2.
b) 256 a) 2
c) 32 b) 1
d) 64 c) A
Answer: b d) ,
Explanation: ASCII-8 can represent 256 Answer: a
different characters. ASCII-8 uses 8-bits for Explanation: The ASCII characters for the
the representation of numbers i.e. it can remaining options are:
represent 28 = 256 different characters. 1 : 00110001
384. The zone of alphabetic characters from A : 01000001
A to O in ASCII is _____________ , : 00101100.
a) 1000 388. Computer has a built-in system clock
b) 0100 that emits millions of regularly spaced
c) 0010 electric pulses per _____ called clock cycles.
d) 0001 a) second
Answer: b b) millisecond
Explanation: The zone used by ASCII for c) microsecond
alphabets is 0100. For e.g. A is represented as d) minute
0100(zone)0001(digit). The hex equivalent is Answer: a
41 for A. The zone used by numbers is 0011. Explanation: The regularly spaced electric
385. The representation of the number 8 in pulses per second are referred to as the clock
binary in ASCII-8 format _________ cycles. All the jobs performed by the
a) 00111000 processor are on the basis of clock cycles.
b) 01001000 389. It takes one clock cycle to perform a
c) 1000 basic operation.
d) 00011000 a) True
b) False

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 COMPUTER SYSTEM ARCHITECTURE UNIT – 2 MCQs
Answer: a Answer: b
Explanation: It takes exactly one clock cycle Explanation: The RISC which stands for
to perform a basic operation, such as moving Reduced Instruction set computer has a fixed
a byte of memory from a location to another length of instructions. It has a small
location in the computer. instruction set. Also has reduced references
390. The operation that does not involves to memory to retrieve operands.
clock cycles is _________ 394. Processor which is complex and
a) Installation of a device expensive to produce is ________
b) Execute a) RISC
c) Fetch b) EPIC
d) Decode c) CISC
Answer: a d) Multi-core
Explanation: Normally, several clock cycles Answer: c
are required to fetch, execute and decode a Explanation: CISC stands for complex
particular program. instruction set computer. It is mostly used in
Installation of a device is done by the system personal computers. It has a large instruction
on its own. set and a variable length of instructions.
391. The number of clock cycles per second is 395. The architecture that uses a tighter
referred as ________ coupling between the compiler and the
a) Clock speed processor is ____________
b) Clock frequency a) EPIC
c) Clock rate b) Multi-core
d) Clock timing c) RISC
Answer: a d) CISC
Explanation: The number of clock cycles per Answer: a
second is the clock speed. It is generally Explanation: EPIC stands for Explicitly parallel
measured in gigahertz(109 cycles/sec) or instruction computing. It has a tighter
megahertz (106 cycles/sec). coupling between the compiler and the
392. CISC stands for ____________ processor. It enables the compiler to extract
a) Complex Information Sensed CPU maximum parallelism in the original code.
b) Complex Instruction Set Computer 396. MAR stands for ___________
c) Complex Intelligence Sensed CPU a) Memory address register
d) Complex Instruction Set CPU b) Main address register
Answer: b c) Main accessible register
Explanation: CISC is a large instruction set d) Memory accessible register
computer. It has variable length instructions. Answer: a
It also has variety of addressing modes. Explanation: The MAR stands for memory
393. Which of the following processor has a address register. It holds the address of the
fixed length of instructions? active memory location.
a) CISC 397. A circuitry that processes that responds
b) RISC to and processes the basic instructions that
c) EPIC are required to drive a computer system is
d) Multi-core ________
a) Memory

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 COMPUTER SYSTEM ARCHITECTURE UNIT – 2 MCQs
b) ALU 1’s complement of 15= 0000
c) CU 2’s complement of 15= 0000+1=0001.
d) Processor 401. Another name for base is __________
Answer: d a) root
Explanation: The processor is responsible for b) radix
processing the basic instructions in order to c) entity
drive a computer. The primary functions of a d) median
processor are fetch, decode and execute. Answer: b
398. The value of base in a decimal number Explanation: Another name for base is radix.
system is ____________ Base refers to the number of digits that a
a) 8 particular number system consists of.
b) 2 The base of decimal number system is 10,
c) 10 binary is 2 and so on.
d) 16 402. The decimal equivalent of (0.101)2 will
Answer: c be ____________
Explanation: A decimal number system a) 0.5
consists of 10 digits from 0 to 9. b) 0.625
The definition of base describes it as a c) 0.25
quantity to represent the number of digits d) 0.875
present in that particular number system. Answer: b
Therefore, here, the base is 10. Explanation: Since the base is 2 , it could be
399. Convert : (110)2 = ( __ )10. easily guessed that the number is binary.
a) 4 Conversion: 2-1 * 1 + 2-2 * 0 + 2-3 * 1 = 0.625.
b) 5 403. Which of the following is not a positional
c) 6 number system?
d) 9 a) Roman Number System
Answer: c b) Octal Number System
Explanation: The base 2 represents that the c) Binary Number System
number is binary ,whereas, the base 10 d) Hexadecimal Number System
represents that it is to be converted to the Answer: a
decimal format. Explanation: The Roman number system isn’t
Conversion: 22 * 1 + 21 * 1 + 20 *0 = 6. a positional number system since it uses
400. The 2’s complement of 15 is symbols to represent numbers.
____________ The octal number system uses digits from 0-
a) 0000 7, the binary number system uses digits from
b) 0001 0-1 whereas, the hexadecimal number
c) 0010 system uses digits from 0-15.
d) 0100
Answer: b
Explanation: 2’s complement is obtained by
adding 1 to the 1’s complement of the
number.
Here, Binary of 15 = 1111

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