Lecture 8

Latches & Flip-flops

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Learning outcomes
❑ Describethe difference between combinational and
sequential systems.
❑ Describe
the difference between synchronous and
asynchronous systems.

❑ Construct
and analyze the operation of latches made
from NAND or NOR gates.

❑ Construct flip-flops using latches.

❑ Describe the operation of D, JK, and T flip-flops.

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Combinational circuits

❑ So far you’ve just worked with combinational circuits,

where applying the same inputs always produces the
same outputs.
❑ This corresponds to a mathematical function, where
every input has a single, unique output.
❑ Outputs is thus only a function of current inputs to the
circuit.
❑ There is No internal memory.
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Sequential Circuits

Inputs Combinational Outputs

logic
Present Next
State State
Memory

❑ In contrast, the outputs of a sequential circuit depend on

not only the inputs, but also the state, or the current
contents of some memory.
❑ This means that the same inputs can yield different
outputs, depending on what’s stored in memory.
❑ Computers are sequential! For example, key presses
and mouse clicks mean different things depending on
which program is running and the state of that program.
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Sequential Circuits

Inputs Combinational Outputs

logic
Present Next
State State
Memory

❑ A sequential circuit consists of memory elements and

combinational logic:
⚫ Memory elements (latches or flip-flops) that store the
Present State
⚫ Combinational logic that computes:
➢ the circuit’s outputs, which depend on the inputs and
Present State
➢ the circuit’s Next State, which also depends on the inputs
and Present State
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Two Types of Sequential Circuits
❑ Synchronous Sequential Circuit
⚫ Uses a clock signal as an additional input
⚫ Changes in the memory elements are controlled by the
clock
⚫ Changes happen at discrete instances of time
❑ Asynchronous Sequential Circuit
⚫ No clock signal
⚫ Changes in the memory elements can happen at any
instance of time
❑ Our focus will be on Synchronous Sequential Circuits
⚫ Easier to design and analyze than asynchronous
sequential circuits
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Synchronous Sequential Circuits

Inputs Combinational Outputs

logic
Present Next
State State
Memory

Clock

❑ Synchronous sequential circuits use a clock signal

❑ The clock signal is an input to the memory elements
❑ The clock determines when the memory should be
updated
❑ The present state = output value of memory (stored)
❑ The next state = input value to memory (not stored yet)
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The Clock

Positive Negative
Clock cycle Clock cycle Pulse Pulse

Time

❑ Clock is a periodic signal = Train of pulses (1's and 0's)

❑ The same clock cycle repeats indefinitely over time

❑ Positive Pulse: when the level of the clock is 1

❑ Negative Pulse: when the level of the clock is 0

❑ Rising Edge: when the clock goes from 0 to 1

❑ Falling Edge: when the clock goes from 1 down to 0

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What exactly is memory?
❑ A memory should have at least three properties.
⚫ It should be able to hold a value.
⚫ You should be able to read the value that was saved.
⚫ You should be able to change the value that was saved.

❑ We’ll start with the simplest case, a one-bit memory.

⚫ It should be able to hold a single bit, 0 or 1.
⚫ You should be able to read the bit that was saved.
⚫ You should be able to change the value. Since there’s only a
single bit, there are only two choices:
• Set the bit to 1
• Reset, or clear, the bit to 0.
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The basic idea of storage
❑ How can a circuit “remember” anything, when it’s just a bunch of
gates that produce outputs according to the inputs?
❑ The basic idea is to use positive feedback to maintain storage
indefinitely. We make a loop, so the circuit outputs are also inputs.

Two inverters, with feedback

0 1 0 If the first input is 0, a 0 gets

Q’ fed back into it
Q

If the first input is 1, a 1 gets

fed back into it
1 0 1
Q’ Q

This circuit will hold its state forever - stable

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The basic idea of storage

Q Q’ Q

❑ Does this satisfy the properties of memory?

⚫ These circuits “remember” the output Q because its value never
changes. Similarly, Q’ never changes either.
⚫ We can also “read” the output Q by attaching a probe or another circuit.
⚫ But we can’t change the output Q! There are no external inputs here, so
we can’t control whether the output is Q=1 or Q=0.
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RS latch
❑ Let’s use NOR gates instead of inverters. The RS (Reset-Set) latch
below has two inputs R and S, which will let us control the outputs Q
and Q’.
R (Reset)
Q

S (Set) Q'

❑ Here Q and Q’ feed back into the circuit. They’re not only outputs,
they’re also inputs!
❑ To figure out how Q and Q’ change, we have to look at not only the
inputs S and R, but also the current values of Q and Q’:
Qnext = (R + Q’current)’
Q’next = (S + Qcurrent)’

❑ Let’s see how different input values for R and S affect this circuit.
es 13
Store operation: RS = 00

R (Reset) 0
Q
Qnext = (R + Q’current)’
Q’next = (S + Qcurrent)’

S (Set) 0 Q'

❑ The above equations reduce to:

Qnext = (0 + Q’current)’ = Qcurrent

Q’next = (0 + Qcurrent)’ = Q’current

❑ So when RS=00, then Qnext = Qcurrent. Whatever value Q

has, it keeps.
❑ This is exactly what we need to store values in the latch.
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Set operation: RS = 01
R (Reset) 0
Q
Qnext = (R + Q’current)’
Q’next = (S + Qcurrent)’

S (Set) 1 Q'

❑ Since S = 1, Q’next is 0, regardless of Qcurrent: Q’next = (1 + Qcurrent)’ = 0

❑ Then, this new value of Q’ goes into the top NOR gate, along with R = 0

Qnext = (0 + 0)’ = 1

❑ So when SR = 10, then Q’next = 0 and Qnext = 1.

❑ This is how you set the latch to 1. The S input stands for “set.”
❑ Notice that it can take up to two steps (two gate delays) from the time S
becomes 1 to the time Qnext becomes 1.
❑ But once Qnext becomes 1, the outputs will stop changing. This is a stable state.
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Latch delays
❑ Timing diagrams are especially useful in understanding how
sequential circuits work. Below is a diagram which shows an
example of how our latch outputs change with inputs RS=01.

R (Reset) 0
Q
Qnext = (R + Q’current)’
Q’next = (S + Qcurrent)’

S (Set) 1 Q'

0 1 2 3 4
⚫ Suppose that initially, Q = 0 and Q’ = 1.
⚫ Since S=1, Q’ will change from 1 to 0 after one NOR- S
gate delay (marked by dotted vertical lines in the
diagram for clarity). R
⚫ This change in Q’, along with R=0, causes Q to Q
become 1 after another gate delay.
⚫ The latch then stabilizes until S or R change again.
Q’
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Reset operation: RS = 10
R (Reset) 1
Q
Qnext = (R + Q’current)’
Q’next = (S + Qcurrent)’

S (Set) 0 Q'

❑ Since R = 1, Qnext is 0, regardless of Qcurrent: Qnext = (1 + Q’current)’ = 0

❑ Then, this new value of Q goes into the bottom NOR gate, where
S=0.

Q’next = (0 + 0)’ = 1

❑ So when SR = 01, then Qnext = 0 and Q’next = 1.

❑ This is how you reset, or clear, the latch to 0. The R input stands for “reset.”
❑ Again, it can take two gate delays before a change in R propagates to the
output Q’next.
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RS latches are memories!
❑ This little table shows that our S R Q
latch provides everything we 0 0 No change
need in a memory: we can set 0 1 0 (reset)
it, reset it, and remember the 1 0 1 (set)

current value.
R Q
❑ The output Q represents the
data stored in the latch. It is
sometimes called the state of
the latch. S Q'

❑ We can expand the table Inputs Current Next

above into a state table, which S R Q Q Q Q
explicitly shows that the next 0 0 0 1 0 1
0 0 1 0 1 0
values of Q depend on their
0 1 0 1 0 1
current values, as well as on 0 1 1 0 0 1
the inputs R and S. 1 0 0 1 1 0
1 0 1 0 1 0
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What about R=S=1 ?
❑ What does it mean to both set and reset at the same time?
❑ Both Qnext and Q’next will become 0. This contradicts the assumption
that Q and Q’ are always complements.
❑ Another problem is what happens when R=S=1 (Q=Q’=0) and R or
S changes to 0?
⚫ S changes to zero first → Reset wins (Q=0, Q’=1)
⚫ R changes to zero first → Set wins (Q=1, Q’=0)
⚫ Both change to 0 at same time → uncontrolled oscillation (unstable)

R Q R
S
Q
Q' Q’
S
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What about R=S=1?
❑ When both R=S change from 1 → 0 at same 1->0
time: R 0 Q
Qnext = (0 + 0)’ = 1
Q’next = (0 + 0)’ = 1 0
S Q'
❑ But these new values go back into the NOR 1->0
gates, and in the next step we get:

Qnext = (0 + 1)’ = 0
Q’next = (0 + 1)’ = 0
R 0 1 Q
❑ The circuit enters an infinite loop, where Q and
Q’ cycle between 0 and 1 forever. This is
actually the worst case, but the moral is don’t
ever set RS=11 (make it invalid input)! 1
S 0 Q'
R
S
Qnext = (R + Q’current)’
Q
Q’next = (S + Qcurrent)’
Q’
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Timing Diagram for RS latch

R Q S R Q
0 0 No change
0 1 0 (reset)
Q' 1 0 1 (set)
S

Set No change Reset No change Set Undefined Reset No change Set

S 1 0 0 0 1 1 0 0 0 1

R 0 0 1 0 0 1 0 1 0 0

Q 1 1 0 0 1 0 0 0 1

Q 0 0 1 1 0 0 1 1 0
Time
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R’S’ latch
❑ There are several varieties of latches.
❑ You can use NAND instead of NOR gates.

S’ (Set)
Q S’ R’ Q
1 1 No change
1 0 0 (reset)
0 1 1 (set)
R’ (Reset)
Q’ 0 0 Avoid!

❑ This is just like an RS latch, but with inverted inputs, as

you can see from the table.
❑ You can derive this table by writing equations for the
outputs in terms of the inputs and the current state, just
as we did for the RS latch.
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R’S’ latch operation

Set Operation Store Operation

S’ 0 1 S’ 1 1
Q Q

0 0
R’ 1 Q’ R’ 1 Q’

Reset Operation Store Operation

S’ 1 0 S’ 1 0
Q Q

1 1
R 0 Q’ R’ 1 Q’
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R’S’ latch operation – Invalid operation
Invalid Operation Oscillation Condition

S’ 0 1 S’ 0→1 1→0
Q Q

1 Q’
R’ 0 R’ 0→1 Q’
1→0

Unknown State
❑ S’ = R’ = 0 should never be
used S’ 1 0 or 1
Q
❑ If S and R change from 0 → 1
simultaneously then
oscillation occurs
R’ 1 Q’
❑ Final Q and Q’ are unknown. 1 or 0
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Enabled (Gated) RS latch
❑ An additional Enable input signal C is used:

S S’ C S R S’ R’ Q
Q 0 x x 1 1 No change
1 0 0 1 1 No change
C 1 0 1 1 0 0 (reset)
1 1 0 0 1 1 (set)
R’ Q’ 1 1 1 0 0 Avoid!
R

❑ Notice the hierarchical design!

⚫ The dotted blue box is the R’S’ latch from the previous slide.
⚫ The first additional NAND gates are simply used to generate the
correct inputs for the S’R’ latch. The NAND gates invert the S and R
inputs when C=1
❑ The control input acts just like an enable.
❑ Clock controls when the state of the latch can be changed
❑ When C=0, the latch remains in the same state
❑ When C=1, then normal latch operation
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Regular vs. Enabled RS latches

R R Q Q(enabled)
R Q Q(regular) R
S S
S Q S En Q
C

S Set Set Set

R Reset Reset

Q
(regular)

Q
(enabled)

⚫ Latch only changes when enable is asserted

⚫ Assume above that latches have no time delay (ideal)
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Enabled/Gated D-Latch
⚫ One data input 𝐷 → S=D and R=D’
D Q ⚫ No undefined state since S  R
C ⚫ Output follows (Q=D) input when latch is enabled
⚫ No change to output when latch is NOT enabled

C D Q
D Q
R Q 0 x No change
S 1 0 0
En Q
1 1 1
C

Q
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Level-sensitive memory
❑ A latch is a level Sensitive memory: as long as the
enable signal is asserted, output can change
❑ In a Level-sensitive memory, output may change a
number of times depending on the duration of the enable
pulse.

Q
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Combinational Cycles - Example
❑ We can connect a latch to an adder combinational circuit

+1 S
Adder G
X

D
Q Latches
C

❑ Let’s say these latches contain some value that we want

to increment.
⚫ The Adder read the current latch value.
⚫ It applies the “G = X + 1” operation.
⚫ The incremented value is stored back into the latches.

❑ At this point, we have to stop the cycle, so the latch value

doesn’t get incremented again by accident.
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Master Slave Flip-Flop
❑ This solution consists in adding two “gates” and open one at a time
❑ Master-Slave D Flip-Flop is a combination of 2 latches. The first
latch is master and responds to one transition of the clock and the
2nd latch to the other transition to the clock.
❑ Therefore, the final output changes during one transition of clock
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Master Slave Flip-Flop

❑ Only one latch “transparent” at any time:

⚫ master closed when slave is open
⚫ slave closed when master is open
⚫ no combinational path through flip flop
❑ Q only changes shortly after 0 → 1 transition of CLK, CLK
so flip flop appears to be “triggered” by rising edge of
CLK:
❑ Major disadvantage is that control inputs (e.g input D)
must be held stable when the master latch is
transparent, that is for CLK low.
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Master Slave Flip-Flop
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Clocks and Flip-Flops
❑ The key to proper operation is to modify the latches to form flip-
flops, which are memory elements that can change state only at
well-defined times, that is on one of the other’s clock transitions
(from 0 to 1 for a rising/positive clock edge or from 1 to 0 for a
falling/negative clock edge.

❑ Clocks are often used to synchronize circuits:

⚫ They generate a repeating, predictable pattern of 0s and 1s
that can trigger certain events in a circuit, such as writing to a
latch.
⚫ If several circuits share a common clock signal, they can
coordinate their actions with respect to one another.

clock period
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Symbols for Edge-Triggering
❑ Edge-Triggered Flip-Flop: Transition (output change) can happen
only during clock pulse transition
❑ Clock pulse transition can be positive/rising clock transition or
negative/falling clock transition
❑ The “triangle” symbol means edge-triggered

Positive-Edge Negative-Edge
Triggering Triggering
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Positive Edge-triggering

In a positive edge-triggered D Flip-

D Q Flop, the output looks at the input
only during the instant that the
The “triangle” clock changes from low to high.
symbol means clk
edge-triggered

Clock

Positive Edge-triggered D Flip-flop: Every rising edge, output is

set to the input
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Negative Edge-triggering
In a negative edge-triggered D
D Q Flip-Flop, the output looks at the
input only on the falling edge of
The “bubble” the clock.
means negative clk
edge-triggered

Clock

Negative Edge-triggered D Flip-flop: Every falling edge, output is set to

the input.
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Flip-flop variations
❑ We can make different versions of flip-flops based on the D flip-flop,
just like we made different latches based on the RS latch.
❑ A JK flip-flop has inputs that act like S and R, but the inputs JK=11
are used to complement the flip-flop’s current state.

C J K Qnext
0 x x No change
1 0 0 No change
1 0 1 0 (reset)
1 1 0 1 (set)
1 1 1 Q’current

❑ A T flip-flop can only maintain or complement its current state.

C T Qnext
0 x No change
1 0 No change
1 1 Q’current
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J-K Flip-Flops
We want to eliminate the forbidden state of the R-S Latch (when
R and S are both 1).
Idea: Q, Q are always different. Use them to control the input.

R Q Q
K
J S Q Q
clk
Jt Kt Qt Qt+1
0 0 0 0
Hold
0 0 1 1
J, K act just like Set and Reset,
0 1 0 0 Reset except: When they’re both 1,
0 1 1 0
we get a toggle.
1 0 0 1
Set
1 0 1 1
1 1 0 1 Toggle
1 1 1 0
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Toggle Flip-Flops
Build a flip-flop that toggles its state on each clock edge when
it is enabled (T is the enable).
Q+ is the Q output after the clock changes
Q
T
Q T Qt Qt+1
clk 0 0 0 T D Q Q
J Q Q 0 1 1
T
K Q Q 1 0 1 clk
clk 1 1 0

Clock
T

Q
 39
Asynchronous Presets and Clears
Clear forces the output low regardless of the other inputs.
Preset forces the output high regardless of the other inputs.
D Ordinary level-sensitive D-latch
R Q
en
S Q
preset
D R Q
en Clear - Force S=0, R=1
S Q
clear
preset preset
D R Q
Preset - Force S=1, R=0 en
S Q
clear
preset

Asynchronous - doesn’t matter whether clock is high or low

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Characteristic/state tables
❑ The tables that we’ve made so
D Q(t+1) Operation
far are called characteristic or
0 0 Reset
tables. 1 1 Set

❑ A characteristic or state table

answers the following
question: J K Q(t+1) Operation
0 0 Q(t) No change
⚫ After the occurrence of a clock 0 1 0 Reset
pulse, what is the next state 1 0 1 Set
Q(t+1) of the circuit given the 1 1 Q’(t) Complement
current state Q(t) and given the
current inputs.
⚫ For simplicity, the control inputs
T Q(t+1) Operation
are not usually listed.
0 Q(t) No change
1 Q’(t) Complement
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Flip flop timing diagrams
❑ “Present state” and “next state” are relative terms.
❑ In the example JK flip-flop timing diagram on the left, you can see
that at the first positive clock edge, J=1, K=1 and Q(1) = 1.
❑ We can use this information to find the “next” state, Q(2) = Q(1)’.
❑ Q(2) appears right after the first positive clock edge, as shown on the
right. It will not change again until after the second clock edge.

1 2 3 4 1 2 3 4
C C
J J
K K
Q Q
These values at clock cycle 1... … determine the “next” Q
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“Present” and “next” are relative
❑ Similarly, the values of J, K and Q at the second positive
clock edge can be used to find the value of Q during the
third clock cycle.
❑ When we do this, Q(2) is now referred to as the “present”
state, and Q(3) is now the “next” state.

1 2 3 4 1 2 3 4
C C
J J

K K

Q Q
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Positive edge triggered
❑ One final point to repeat: the flip-flop outputs are affected
only by the input values at the positive edge.
⚫ In the diagram below, K changes rapidly between the second
and third positive edges.
⚫ But it’s only the input values at the third clock edge (K=1, and
J=0 and Q=1) that affect the next state, so here Q changes to 0.

❑ This is a fairly simple timing model. In real life there are

“setup times” and “hold times” to worry about as well, to
account for internal and external delays.

1 2 3 4
C
J

Q
 Registers
❑ Registers can hold larger quantities of data than
individual flip-flops.
❑ An 𝑛-bit register consists of 𝑛 flip-flops and stores 𝑛
bits.
❑ Common clock: data is loaded in parallel at the same
clock edge.
❑ Common reset: All Flip-Flops are reset in parallel.
4-bit
Register
𝐷3 𝐷2 𝐷1 𝐷0
𝐷3 𝑄3
𝐷3 𝑄3 𝐷2 𝑄2 𝐷1 𝑄1 𝐷0 𝑄0 𝐷2 𝑄2
𝐷1 𝑄1
𝑅 𝑅 𝑅 𝑅 𝐷0 𝑄0
𝐶𝑙𝑜𝑐𝑘
𝑅𝑒𝑠𝑒𝑡
𝑄3 𝑄2 𝑄1 𝑄0
𝑅𝑒𝑠𝑒𝑡
 45
Summary
❑ Two types of Memory elements: latches and flip-flops.
❑ Latches are level-sensitive, flip-flops are edge-triggered.
❑ There are several different kinds of flip-flops, but they all
serve the same basic purpose of storing bits.
❑ A flip-flop can be described using a characteristic/state
table.
❑ To use memory in a larger circuit, we need to:
⚫ Keep the memory disabled until new values are ready to be
stored.
⚫ Enable the memory just long enough for the update to occur.
❑ A clock signal is used to synchronize circuits and
operations.
❑ The clock period reflects how long combinational
operations take.
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Acknowledgments
❑ Credit
is acknowledged where credit is due.
Please refer to the full list of references.