Savitribai Phule Pune University, Pune

A Project Phase-1 Report

On
IMPLEMENTATION OF EFFICIENT CRYPTOGRAPHIC
ALGORITHM

SUBMITTED TOWARDS THE

PARTIAL FULFILLMENT OF THE REQUIREMENTS OF

BACHELOR OF ENGINEERING
(Electronics & Telecommunication Engineering)

Submitted by
Mayuresh Kiran Bachhav-(72256461K)
Chetan Sahebrao Panmand-(72256480F)
Krushna Bhausaheb Jadhav-(72256461K)

Under the Guidance of

Prof. Dr. Vinay Kumar Jain

Department Of Electronics & Telecommunication Engineering

SANDIP FOUNDATION’S
SANDIP INSTITUTE OF ENGINEERING AND MANAGEMENT
NASHIK
(2025-2026)

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 SANDIP INSTITUTE OF ENGINEERING AND MANAGEMENT
DEPARTMENT OF ELECTRONICS & TELECOMMUNICATION

CERTIFICATE

This is to certify that, The project IMPLEMENTATION OF EFFICIENT CRYPTO-

GRAPHIC ALGORITHM submitted by

Mayuresh Kiran Bachhav(72256461K)

Chetan Sahebrao Panmand(72256480F)
Krushna Bhausaheb Jadhav(72256461K)

is a Bonafied work completed under my supervision and guidance in partial fulfillment

for award of Bachelor of Engineering (Electronics & Telecommunication) Degree of
Savitribai Phule Pune University, Pune.
Place: Nashik
Date:

Internal Examiner External Examiner

Prof. Dr. Vinay Kumar Jain Prof. Yogesh R. Risodkar

Project Guide H.O.D

Dr. D. P. Patil
Principal
SANDIP INSTITUTE OF ENGINEERING & MANAGEMENT, NASHIK, (M.S.) 422213

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 Abstract

The project “Implementation of Efficient Cryptographic Algorithm” focuses on devel-

oping a software-based simulation platform for efficient data encryption and hashing
using AES-128, AES-256, and SHA-256 algorithms. The goal is to replicate the pro-
cessing behavior of ASIC-level cryptographic systems through a web-based environ-
ment, providing users with a clear understanding of encryption operations, internal
algorithmic steps, and performance parameters.
This project eliminates the need for expensive hardware implementations by utilizing
software simulation to demonstrate how cryptographic systems ensure data confiden-
tiality, integrity, and security. Users can input plaintext or messages, select a desired
algorithm, and obtain encrypted or hashed outputs in real time. The platform also
provides performance analytics such as processing time and round count for educa-
tional and research purposes. Through this system, users gain practical insights into
modern cryptographic standards and their computational efficiency, bridging the gap
between theoretical learning and real-world cryptographic applications.
Keywords: AES-128, AES-256, SHA-256, Cryptography, Data Security, ASIC Simu-
lation, Encryption, Hashing, Software Implementation, Web-Based Platform

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 Acknowledgments

It gives us great pleasure in presenting the preliminary project phase-1 report on

”IMPLEMENTATION OF EFFICIENT CRYPTOGRAPHIC ALGORITHM”.

I take this opportunity to express my heartfelt gratitude to my guide, Prof. Dr. Vinay
Kumar Jain, for his constant encouragement, able guidance and support throughout
the course of this semester.

I take this opportunity to thank Head of Department, Department of Electronics

and Telecommunication Engineering, Prof. Y. R. Risodkar and express my gratitude
towards my parents, friends for the completion of my work.

I sincerely thanks to Prof. Dr. D. P. Patil Principal, Sandip Institute of Engineering

and Management, Nashik, for his advice and support during the course of my work.

Mayuresh Kiran Bachhav

Chetan Sahebrao Panmand
Krushna Bhausaheb Jadhav
(B.E. E&TC Engg.)

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 INDEX

Abstract i

Acknowledgments ii

List of Figures v

List of Tables vi

List of Abbreviations vii

1 INTRODUCTION 1
1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

2 LITERATURE SURVEY 5

3 SYSTEM METHODOLOGY 13
3.1 Proposed System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.2 System Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.3 Data Flow and Working . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.4 Algorithm Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.4.1 AES Implementation . . . . . . . . . . . . . . . . . . . . . . . . 17
3.4.2 SHA-256 Implementation . . . . . . . . . . . . . . . . . . . . . 18
3.5 Software Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.5.1 Frontend Architecture . . . . . . . . . . . . . . . . . . . . . . . 19
3.5.2 Cryptographic Implementation . . . . . . . . . . . . . . . . . . 19
3.5.3 Visualization and Analytics . . . . . . . . . . . . . . . . . . . . 20
3.6 Hardware Integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.6.1 FPGA Implementation . . . . . . . . . . . . . . . . . . . . . . . 21
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 3.6.2 IoT and RFID Integration . . . . . . . . . . . . . . . . . . . . . 21
3.7 Hardware Components . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.7.1 NodeMCU ESP8266 . . . . . . . . . . . . . . . . . . . . . . . . 22
3.7.2 RFID Reader (RC522) . . . . . . . . . . . . . . . . . . . . . . . 23
3.7.3 MPU6050 Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.7.4 Vibration Sensor (SW-420) . . . . . . . . . . . . . . . . . . . . 24
3.7.5 Vicharak Shrike-lite FPGA Development Board . . . . . . . . . 25
3.8 System and Architecture Diagrams . . . . . . . . . . . . . . . . . . . . 26

4 PERFORMANCE ANALYSIS 30
4.1 Algorithm Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
4.1.1 Advanced Encryption Standard (AES) . . . . . . . . . . . . . . 30
4.1.2 Secure Hash Algorithm (SHA-256) . . . . . . . . . . . . . . . . 31
4.1.3 Algorithm Comparison . . . . . . . . . . . . . . . . . . . . . . . 32
4.2 System Development . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
4.2.1 Development Approach . . . . . . . . . . . . . . . . . . . . . . 33
4.2.2 Development Phases . . . . . . . . . . . . . . . . . . . . . . . . 34
4.3 Software Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
4.3.1 Project Requirements . . . . . . . . . . . . . . . . . . . . . . . 35
4.3.2 Project Operations . . . . . . . . . . . . . . . . . . . . . . . . . 35
4.3.3 Software Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
4.4 Development Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
4.5 Experimental Analysis and Results . . . . . . . . . . . . . . . . . . . . 38
4.5.1 Performance Testing and Response Time . . . . . . . . . . . . . 38
4.5.2 Security Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . 39
4.6 Dashboard and Output Analysis . . . . . . . . . . . . . . . . . . . . . . 40

5 CONCLUSION 43
5.1 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
5.2 Future Scope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Bibliography 46

iv
List of Figures

3.1 RFID Reader RC522 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

3.2 Vicharak Shrike-Lite FPGA Development Board (Representative Image) 25
3.3 Block diagram of Implementation of Efficient Cryptographic Algorithm 26
3.4 Algorithm Flow chart of Implementation of Efficient Cryptographic Al-
gorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.5 System Architecture of Implementation of Efficient Cryptographic Al-
gorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.6 Model Architecture of Implementation of Efficient Cryptographic Al-
gorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

4.1 Dashboard Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

4.2 Encryption Result Analysis . . . . . . . . . . . . . . . . . . . . . . . . 40
4.3 Decryption Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
4.4 Performance Analysis: Power Comparison . . . . . . . . . . . . . . . . 41
4.5 Performance Analysis: Throughput Comparison . . . . . . . . . . . . . 42

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List of Tables

2.1 Summary of Related Research Works on AES and SHA Implementations 10

3.1 System Architecture Components . . . . . . . . . . . . . . . . . . . . . 15

3.2 AES and SHA-256 Specifications . . . . . . . . . . . . . . . . . . . . . 18
3.3 Hardware Component Specifications . . . . . . . . . . . . . . . . . . . 22

4.1 AES vs SHA-256 Comparison . . . . . . . . . . . . . . . . . . . . . . . 33

4.2 Software Environment Specifications . . . . . . . . . . . . . . . . . . . 37
4.3 AES Performance Comparison . . . . . . . . . . . . . . . . . . . . . . . 38
4.4 SHA-256 Performance Comparison . . . . . . . . . . . . . . . . . . . . 39
4.5 FPGA Resource Utilization . . . . . . . . . . . . . . . . . . . . . . . . 39

vi
List of Abbreviations

AES Advanced Encryption Standard

SHA-256 Secure Hash Algorithm 256-bit

ASIC Application-Specific Integrated Circuit

IoT Internet of Things

FPGA Field-Programmable Gate Array

IEEE Institute of Electrical and Electronics Engineers

RISC-V Reduced Instruction Set Computer - Five

DES Data Encryption Standard

MDPI Multidisciplinary Digital Publishing Institute

IC Integrated Circuit

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 IMPLEMENTATION OF EFFICIENT CRYPTOGRAPHIC ALGORITHM

CHAPTER 1
INTRODUCTION

1.1 Introduction

In the modern digital landscape, the exchange and storage of information have be-
come integral to almost every sector, including banking, healthcare, communication,
and defense. As the volume of digital transactions continues to grow, the need for
secure data transmission has become increasingly critical. Every piece of information
transmitted over the Internet—whether it is a personal message, a bank transaction,
or a file transfer—must be protected from unauthorized access, modification, or inter-
ception. Cryptography provides the mathematical foundation for data protection. It
ensures that sensitive information remains confidential and unaltered by transforming
plaintext into an unreadable format through various encryption techniques. It also
guarantees authentication and non-repudiation, confirming that messages originate
from legitimate sources and remain unmodified during transit. Among the crypto-
graphic algorithms developed to achieve these objectives, the Advanced Encryption
Standard (AES) and the Secure Hash Algorithm (SHA) families are the most trusted
and widely adopted worldwide.
The AES algorithm uses symmetric key encryption to secure digital data efficiently.
It operates on fixed block sizes with varying key lengths such as 128, 192, or 256 bits,
offering flexibility between speed and security. AES is known for its resistance to
known cryptanalytic attacks and is commonly used in Wi-Fi security (WPA2/WPA3),
cloud storage encryption, and financial communication systems. On the other hand,
SHA-256, part of the SHA-2 family, is a cryptographic hash function that transforms
input data into a fixed-size 256-bit digest. It is extensively used in digital signa-
tures, blockchain verification, and integrity validation processes. Although hardware
implementations like ASICs (Application-Specific Integrated Circuits) and FPGAs
(Field Programmable Gate Arrays) achieve high-speed cryptographic processing, they
demand specialized hardware design skills, expensive fabrication tools, and longer
development cycles. Such solutions are not ideal for academic or low-cost research

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environments. To address this challenge, this project aims to design a software-based

cryptographic simulation platform that reproduces ASIC-like encryption and hashing
behavior at a much lower cost.
The proposed system, titled ”Implementation of Efficient Cryptographic Algorithm,”
focuses on simulating AES-128, AES-256, and SHA-256 within a web-based environ-
ment. It allows users to input plaintext, select the desired algorithm, and visualize
encryption or hashing results instantly. In addition to output generation, the system
provides insights into the internal rounds of computation, processing speed, and al-
gorithmic efficiency, mimicking real-world ASIC operation. This approach not only
supports hands-on learning but also bridges the gap between theoretical cryptography
and practical system design. The platform can serve as an educational, analytical, and
developmental tool for researchers and students aiming to understand cryptographic
principles and evaluate algorithmic performance. By focusing on software simulation,
the project eliminates hardware dependencies while maintaining analytical depth, ef-
ficiency, and scalability. In essence, this project contributes toward making advanced
cryptographic systems more accessible, visual, and interactive, helping users to ana-
lyze how encryption and hashing safeguard digital communication and to explore how
these mechanisms can evolve for future secure systems.
The rapid advancement of digital technology has transformed the way information is
exchanged, stored, and processed across various platforms. From online banking and e-
commerce to medical record management and communication systems, the reliance on
digital networks has increased dramatically. This growing interconnectivity has also
introduced significant challenges in maintaining data confidentiality, integrity, and au-
thenticity. Cyberattacks, identity theft, data manipulation, and unauthorized access
have become persistent threats, emphasizing the necessity for robust data protection
mechanisms. Cryptography has emerged as a fundamental technique for ensuring se-
cure communication in modern information systems. It provides mathematical meth-
ods to convert readable data into an encoded form, thereby preventing unauthorized
users from interpreting or tampering with sensitive information. Cryptographic sys-
tems are broadly classified into two categories: symmetric and asymmetric algorithms.
In symmetric encryption, the same key is used for both encryption and decryption,
whereas in asymmetric encryption, different keys are employed for each operation.

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Among the available cryptographic standards, the Advanced Encryption Standard

(AES) and the Secure Hash Algorithm (SHA) series are the most widely adopted
due to their efficiency, flexibility, and proven security strength. The Advanced En-
cryption Standard, developed by the National Institute of Standards and Technology,
replaced the earlier Data Encryption Standard to provide improved resistance against
brute-force and differential attacks. AES is widely used for secure data storage, in-
ternet communication, wireless network protection, and financial transaction systems.
Depending on the key length—128, 192, or 256 bits—it provides different levels of
security. AES operates on substitution and permutation steps over several rounds,
making it computationally strong and suitable for both hardware and software imple-
mentation. The Secure Hash Algorithm, particularly SHA-256, belongs to the SHA-2
family and is used to generate a unique, fixed-length hash value from variable-length
input data. This property is essential in data integrity verification, password pro-
tection, blockchain verification, and digital signature generation. Unlike encryption,
hashing is a one-way function that cannot be reversed, ensuring that the original infor-
mation cannot be retrieved from its hash. Hardware implementations of cryptographic
algorithms, such as ASICs and FPGAs, are known for their superior performance and
low power consumption. They are used in applications requiring high-speed encryp-
tion and decryption, such as defense communication and large-scale financial systems.
However, these hardware solutions are costly, require complex design procedures, and
are not easily accessible for educational and research purposes. Additionally, testing
new algorithmic modifications in hardware involves long development cycles, making
them less flexible for academic experimentation.
To overcome these limitations, this project focuses on a software-based approach to
demonstrate and analyze the functionality of modern cryptographic algorithms. The
objective is to implement AES-128, AES-256, and SHA-256 algorithms through a web-
based platform that simulates ASIC-level processing behavior. Users can input text or
data, select an algorithm, and observe the corresponding encrypted or hashed result,
along with computational parameters such as time complexity and number of opera-
tions performed. This simulation allows detailed visualization of each internal stage
of encryption or hashing, helping learners and researchers understand the underlying
processes without the need for dedicated hardware. The system is designed to be inter-

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 IMPLEMENTATION OF EFFICIENT CRYPTOGRAPHIC ALGORITHM

active, efficient, and educational. It bridges the gap between theoretical understanding
and practical implementation by providing a transparent view of how cryptographic
operations transform data within each algorithmic round. Such visualization assists
in comprehending how substitution, permutation, and key scheduling occur in AES,
and how compression and message padding work in SHA-256. Moreover, this environ-
ment serves as a testing and validation platform where users can compare algorithmic
performance under different input conditions. The project titled ”Implementation of
Efficient Cryptographic Algorithm” aims to make cryptography more accessible to
students, developers, and researchers. It demonstrates that software-based systems
can emulate hardware-level functionality while remaining flexible and cost-effective.
Through this platform, users can explore encryption and hashing techniques inter-
actively, gaining a comprehensive understanding of how data security mechanisms
operate in real-world systems. The work also provides a foundation for future devel-
opment toward hybrid software-hardware systems, optimized encryption modules, and
educational tools for secure digital design.

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CHAPTER 2
LITERATURE SURVEY

Over the past two decades, cryptographic research has focused on enhancing data se-
curity while improving computational efficiency and resource utilization. Numerous
studies have explored both hardware and software implementations of encryption and
hashing algorithms to address the growing demand for secure digital communication.
The Advanced Encryption Standard (AES) and Secure Hash Algorithm (SHA) fami-
lies have been the center of attention for researchers due to their robustness and wide
range of applications. Renugadevi et al. (2022) presented an optimized hardware
implementation of the AES algorithm on an FPGA platform using a Mux–Demux
pair architecture to achieve low area occupancy and high throughput. Their work
demonstrated how specific logic optimizations could improve the performance of AES
on Virtex-7 and Zynq-7000 series FPGAs. The study proved that parallel execution
of AES rounds can significantly enhance encryption speed while reducing power con-
sumption, setting a benchmark for future lightweight designs.
Nguyen and colleagues (2025) proposed AES-RV, a RISC-V-based hardware acceler-
ator that integrates AES instructions directly into the processor pipeline. This ap-
proach achieved substantial improvements in latency and energy efficiency, making it
suitable for resource-constrained IoT environments. The integration of cryptographic
extensions within the CPU core also simplified software control and improved real-
time responsiveness in secure embedded systems. In another notable study, Jabbar
(2024) investigated the combination of AES and SHA algorithms for image encryp-
tion applications. The author introduced a method in which SHA-256 was used to
generate AES encryption keys dynamically. This hybrid approach strengthened key
unpredictability and improved resistance to brute-force attacks. The results indicated
that combining hashing with symmetric encryption enhances data confidentiality and
integrity, especially in multimedia and cloud-storage security. The work published by
Aalto University researchers in 2024 described the design of a RISC-V core integrated
with an AES-256 accelerator for embedded cryptographic systems. Their study em-
phasized the benefits of combining open-source processor architectures with dedicated

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hardware blocks to achieve high throughput without compromising flexibility. The

accelerator achieved a notable reduction in processing time compared to software-only
AES implementations, illustrating how co-design between processor and hardware can
create efficient security solutions.
A related contribution from MDPI authors (2024) discussed lightweight AES accel-
erators designed for portable devices and IoT sensors. The paper evaluated different
architectures in terms of power, area, and delay trade-offs under side-channel attack
resistance. The findings highlighted the importance of balancing security and effi-
ciency, especially when implementing encryption in low-power or battery-operated
environments. Apart from AES-focused research, several studies have explored the
efficiency of SHA-256 in software and hardware. The National Institute of Standards
and Technology (NIST) published the Secure Hash Standard (FIPS-180-4), which de-
fines the SHA-2 family and its use in integrity verification, password hashing, and
blockchain applications. Recent studies have optimized SHA-256 implementations us-
ing pipelined architectures and lookup-table substitution to improve hash computation
speed on both FPGA and general-purpose processors. While the existing literature
demonstrates significant progress in hardware accelerators and hybrid cryptographic
systems, most of these implementations require specialized tools, fabrication processes,
and high costs, which are impractical for academic and small-scale research use. Only
limited work has focused on providing an accessible, software-based environment that
can simulate ASIC-level encryption performance for educational and analytical pur-
poses. This gap motivates the development of the current project, which aims to
implement AES-128, AES-256, and SHA-256 in a software platform that mimics hard-
ware efficiency while maintaining low cost and high flexibility.
The literature collectively highlights the continued relevance of AES and SHA algo-
rithms in modern security systems and the ongoing research into improving their speed,
scalability, and energy efficiency. By leveraging these findings, this project seeks to
translate complex hardware implementations into an interactive software simulation
that helps users understand the inner mechanisms of cryptographic algorithms and an-
alyze their performance through visualization and experimentation. In recent years,
the rapid growth of digital communication and the continuous rise in cyber threats
have driven researchers to design more secure and efficient cryptographic algorithms.

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The literature on cryptographic systems reveals a continuous effort to balance three

main factors: computational performance, hardware resource utilization, and the de-
gree of security provided. Various studies have explored both hardware and software
implementations of AES and SHA algorithms to achieve optimal encryption speed
while maintaining robustness against cryptographic attacks.
Researchers at the National Institute of Standards and Technology (NIST) established
the Advanced Encryption Standard (AES) in 2001 as a successor to the outdated Data
Encryption Standard (DES). Since then, numerous works have focused on improving
AES implementation efficiency across different hardware and software platforms. Sev-
eral studies have shown that the substitution–permutation structure of AES makes it
suitable for both hardware acceleration and lightweight software-based designs. The
algorithm’s regular architecture has encouraged its adoption in embedded systems, In-
ternet of Things (IoT) devices, and high-performance computing applications. Renu-
gadevi and colleagues (2022) designed a compact AES core architecture on an FPGA
using resource-sharing techniques that minimized logic utilization without compromis-
ing throughput. The study demonstrated that the combination of optimized S-boxes
and pipelined round transformations can increase throughput while maintaining low
area consumption. Their approach achieved better results than conventional AES de-
signs, making it practical for low-power portable systems. Similarly, other researchers
have introduced parallel and loop-unrolled AES implementations to reduce latency
in encryption tasks, especially for real-time communication protocols such as HTTPS
and VPNs.
Nguyen et al. (2025) explored an innovative hybrid design by embedding AES in-
structions into a custom RISC-V processor pipeline. This tightly coupled architecture
eliminated the overhead associated with software-level cryptographic calls, leading
to a significant reduction in encryption time and improved energy efficiency. Their
experiment validated the effectiveness of instruction-level integration, especially for
IoT applications that require on-device encryption with minimal computational delay.
Such designs indicate the growing interest in hardware–software co-design approaches
that provide high performance without sacrificing programmability. In another study,
Jabbar (2024) implemented a secure image encryption scheme by combining AES with
SHA-256 for dynamic key generation. The hybrid model generated session-dependent

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keys using SHA-256 to improve resistance against replay and brute-force attacks. The
research concluded that combining symmetric encryption and hash-based key man-
agement provides enhanced security for multimedia data, particularly in cloud stor-
age systems where confidentiality and authenticity are crucial. A study conducted by
Aalto University (2024) developed a RISC-V-based cryptographic processor that incor-
porated AES-256 and SHA-256 hardware accelerators. This implementation achieved
a high level of parallelism and reduced execution latency compared to conventional
microcontroller-based encryption. The design targeted embedded systems and smart
cards, showing that custom instruction sets combined with hardware accelerators can
achieve near-ASIC performance even in reconfigurable devices. MDPI’s 2024 paper on
lightweight AES accelerators examined various architectural trade-offs in implementing
AES for resource-constrained devices. The authors analyzed area–power–delay met-
rics and proposed a composite field-based S-box implementation to minimize hardware
complexity. The study also discussed side-channel attack resistance and introduced
masking techniques to protect AES from differential power analysis. These findings
emphasize that performance improvements in cryptographic systems must also con-
sider resilience against physical attacks.
In the domain of software cryptography, multiple studies have explored algorith-
mic optimization using parallel computing and GPU acceleration. Recent experi-
ments demonstrated that AES and SHA-256 can be efficiently parallelized to exploit
multicore CPU and GPU architectures, thereby improving execution speed for large
datasets. Some works introduced lookup-table-based substitution and precomputed
key scheduling to reduce processing cycles, achieving performance levels comparable
to mid-range hardware implementations. The Secure Hash Algorithm (SHA-256), a
member of the SHA-2 family, has also been extensively studied for its collision resis-
tance and computational behavior. Researchers have proposed improvements to reduce
the number of logical operations and optimize message padding for faster computation
on embedded processors. Several academic works have examined how SHA-256 can
be combined with AES for secure authentication, blockchain hashing, and password
protection. The use of SHA-256 in distributed ledger technology has proven its im-
portance in maintaining data integrity and verifying transactions without requiring
centralized authorities.

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Recent literature has also highlighted the increasing importance of designing software-
based cryptographic simulators for educational and analytical purposes. Many univer-
sities and research institutions are now promoting interactive simulation environments
that replicate ASIC or FPGA behavior in software to make cryptographic education
more accessible. These tools allow students and developers to visualize encryption
and hashing operations in real-time without expensive hardware setups. Despite these
advancements, most high-performance implementations still rely on specialized hard-
ware, making them inaccessible for smaller laboratories or academic institutions. Very
few works have addressed the need for cost-effective platforms that combine algorithm
visualization, performance analysis, and security evaluation in a single integrated en-
vironment. This gap in the existing literature serves as the primary motivation for
this project.
The proposed project aims to develop a software-driven simulation framework that
implements AES-128, AES-256, and SHA-256 algorithms efficiently, allowing users to
input data, visualize encryption or hashing steps, and analyze performance metrics
such as processing time and round count. Unlike existing hardware-heavy research,
this work focuses on creating a lightweight, interactive, and educational platform that
bridges the gap between theoretical cryptography and hardware acceleration studies.
By analyzing previous research on AES and SHA optimization, the project leverages
proven algorithmic techniques and translates them into a web-based environment suit-
able for academic exploration and further development. This literature review under-
scores that while hardware continues to dominate performance benchmarks, software-
based cryptographic simulation remains a crucial area of research for accessibility,
learning, and algorithmic experimentation.

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Table 2.1: Summary of Related Research Works on AES and SHA Implementations

Author(s) Year Title of Paper / Publication Key Findings

Research Work / Journal /
Conference

Renugadevi2022 Low Area and IEEE Inter- Proposed an optimized AES ar-
N., et High Through- national Con- chitecture using resource shar-
al. put Implemen- ference on ing and pipelining on FPGA.
tation of AES Computing and Achieved improved throughput
Algorithm on Communica- with reduced logic utilization,
FPGA tion Systems suitable for low-power embedded
(ICCCS) systems.

Nguyen 2025 AES-RV: RISC- IEEE Transac- Introduced a custom RISC-V pro-
V.T., et V Based Accel- tions on VLSI cessor with integrated AES in-
al. erator for IoT Systems (IEEE structions. The design improved
Security Appli- TVLSI) energy efficiency and reduced la-
cations tency, demonstrating hardware–
software co-design benefits for
IoT encryption.

Jabbar 2024 AES Key Gen- International Proposed a hybrid encryption

R.S. eration using Journal of Ad- method where SHA-256 dynam-
SHA-256 for Im- vanced Scientific ically generates AES keys, en-
age Encryption Research and hancing key randomness and re-
Engineering sistance to brute-force and differ-
(IJASRE) ential attacks in multimedia en-
cryption.

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 IMPLEMENTATION OF EFFICIENT CRYPTOGRAPHIC ALGORITHM

Table 2.1 – continued from previous page

Author(s) Year Title of Paper / Publication Key Findings

Research Work / Journal /
Conference

Aalto 2024 Design and IEEE Embed- Developed a RISC-V processor

Uni- Implementa- ded Systems with a dedicated AES-256 hard-
versity tion of RISC-V Letters (IEEE ware accelerator achieving high
Re- Core Integrated ESL) parallelism, reduced processing
search with AES-256 time, and improved performance
Group Accelerator for embedded security systems.

MDPI 2024 Security Eval- MDPI Electron- Presented lightweight AES archi-
Authors uation of ics Journal tectures optimized for low-area
Lightweight and low-power embedded appli-
AES Acceler- cations. Improved resistance to
ators for IoT side-channel attacks while main-
Devices taining encryption speed and re-
liability.

Zhu, H., 2023 FPGA- IEEE Interna- Implemented a parallel SHA-256

et al. Based High- tional Sympo- pipeline architecture achieving
Performance sium on Circuits 3× speed improvement over tra-
SHA-256 Ac- and Systems ditional SHA-256, demonstrating
celerator for (ISCAS) efficiency for blockchain and au-
Blockchain thentication systems.
Systems

Gaurav 2023 Comparative International Conducted comparative perfor-

Singh, Analysis of AES Journal of Com- mance analysis of AES and DES
et al. and DES in puter Science algorithms. Concluded AES pro-
Data Security and Applica- vides better security, flexibility,
Systems tions (IJCSA) and efficiency, making it ideal for
secure communication systems.

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 IMPLEMENTATION OF EFFICIENT CRYPTOGRAPHIC ALGORITHM

Table 2.1 – continued from previous page

Author(s) Year Title of Paper / Publication Key Findings

Research Work / Journal /
Conference

Reddy, 2024 Performance Springer Jour- Proposed GPU-based accelera-

K. & Optimization nal of Cloud tion of AES and SHA-256 for se-
Mishra, of AES and Computing: Ad- cure cloud storage, achieving high
P. SHA Algo- vances, Systems throughput and improved data
rithms in Cloud and Applica- encryption accuracy with mini-
Environments tions mal latency.

Kumar, 2021 Implementation IEEE Interna- Demonstrated AES-128 encryp-

A., & of AES En- tional Confer- tion on low-cost FPGA boards us-
Sharma, cryption on IoT ence on Emerg- ing Python-based control, balanc-
S. Edge Devices ing Trends in ing performance and energy effi-
Using Python Computing ciency for IoT security.
and FPGA (ICETC)

Patel, 2020 Analysis of Elsevier Journal Proposed an AES-SHA hybrid

R., & Hybrid Crypto- of Information model for simultaneous data en-
Desh- graphic Tech- Security and cryption and integrity verifica-
mukh, niques Combin- Applications tion, enhancing resistance to tam-
V. ing AES and pering and ensuring high data re-
SHA for Data liability.
Protection

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CHAPTER 3
SYSTEM METHODOLOGY

3.1 Proposed System

The proposed system implements a hybrid software-hardware cryptographic platform

following a layered architecture comprising four primary modules: the User Interface
Layer, Algorithm Processing Core, Visualization and Analytics Engine, and Hardware
Validation Interface. This modular design ensures scalability, maintainability, and
clear separation of concerns between software simulation and hardware verification
components. The 75% software and 25% hardware allocation reflects the project’s
emphasis on accessibility and visualization while maintaining meaningful hardware
validation capabilities.
The input layer accepts plaintext, ciphertext, or message data through a web-based
interface developed using HTML5, CSS3, and JavaScript with React framework. Users
select algorithms (AES-128, AES-256, or SHA-256), specify operation modes (encryp-
tion/decryption for AES), and provide necessary key material. Input validation en-
sures hexadecimal format compliance and key length verification: 32 hex characters
for AES-128 (128 bits) and 64 hex characters for AES-256 (256 bits). The interface
supports text input, file upload for binary data, and JSON artifact import for previous
simulation results.
The algorithm processing layer implements the core cryptographic operations. For
AES, the implementation supports both ECB and CBC modes with PKCS7 padding
for non-aligned data. The four fundamental transformations: SubBytes, ShiftRows,
MixColumns, and AddRoundKey, are implemented using lookup tables for software
acceleration and bitwise operations for hardware compatibility. For SHA-256, the
compression function processes 512-bit blocks through 64 rounds of logical operations
including Ch, Maj, Sigma0, and Sigma1 functions with modular addition.
The visualization engine, implemented using [Link] and [Link] libraries, provides step-
by-step representation of AES round transformations including state matrix evolution,
key schedule generation and expansion, SHA-256 message scheduling and compres-

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sion, and real-time performance metrics including execution time, throughput, and
round count. This educational component distinguishes our platform from existing
implementations by enabling users to observe how diffusion and confusion properties
propagate through algorithmic operations.
The hardware validation layer employs the Vicharak Shrike-lite development board fea-
turing a hybrid RISC-V RP2040 microcontroller and Renesas ForgeFPGA architecture.
The FPGA implements round-based AES encryption and SHA-256 compression func-
tions, with the RP2040 managing control flow and data transfer. Hardware-software
communication occurs via a 6-bit high-speed parallel interface, achieving low-latency
cryptographic offloading with minimal overhead.

3.2 System Architecture

The system architecture follows a client-server model with the web browser serving
as the client application and an optional Python Flask backend providing additional
processing capabilities. The architecture is designed to operate primarily client-side,
with all cryptographic simulations executing within the browser using the Web Crypto
API and custom JavaScript implementations. This design choice ensures portability,
eliminates server infrastructure requirements, and enables offline operation once the
application is loaded.
At the highest level, the architecture consists of three tiers. The presentation tier han-
dles user interaction, input validation, and results display through React components.
The simulation tier executes cryptographic algorithms, manages state transitions, and
coordinates visualization updates. The hardware abstraction tier manages communi-
cation with the FPGA board, translates software requests into hardware commands,
and returns hardware execution results for comparison.
The presentation tier implements four primary page flows: AES simulation, SHA
simulation, IoT monitoring, and RFID authentication. Each page provides algorithm-
specific controls, real-time output display, performance metrics, and export capabil-
ities. Navigation between pages occurs through a dashboard interface that presents
feature cards with descriptions and status indicators.
The simulation tier maintains application state through React hooks, managing mode
selection, key material, input artifacts, simulation status, and round counters. Crypto-
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graphic operations execute asynchronously using Promises and timer-driven events for
visual feedback. The simulation core branches by input type (text, file, or JSON), ex-
ecutes the appropriate processing path, and routes results to output surfaces including
text panels, file downloads, and JSON exports.
The hardware abstraction tier implements a command protocol over the USB-UART
bridge connecting the host computer to the Vicharak Shrike-lite board. Commands
include key loading, mode selection, data transfer, execution trigger, and result re-
trieval. The protocol uses fixed-length frames with checksum validation to ensure
reliable communication between software and hardware components.
Table 3.1: System Architecture Components

Layer Component Technology Responsibility

Presentation Dashboard React 18, Tailwind CSS Navigation and feature selection
Presentation AES Page Web Crypto API Encryption/decryption controls
Presentation SHA Page JavaScript Hash generation and display
Presentation IoT Page React, Recharts Sensor monitoring dashboard
Simulation AES Flow CryptoJS / Web Crypto Core AES operations
Simulation SHA Flow JavaScript Core SHA-256 operations
Simulation Round Viz [Link], [Link] Algorithm visualization
Hardware FPGA Core Verilog Hardware acceleration
Hardware RP2040 MCU C/C++ Control and communication
Hardware UART Bridge USB-UART Host-board communication

3.3 Data Flow and Working

The data flow through the system follows a consistent pattern across all cryptographic
operations. Understanding this flow is essential for comprehending how user inputs
transform into encrypted outputs, hash values, or hardware validation results.
The working process begins with user authentication through the web interface. For
software-only operations, users directly access the AES or SHA simulation pages. For
hardware-validated operations, users connect the Vicharak Shrike-lite board via USB
and initialize the hardware interface through the application.
Step 1: Input Acquisition. The user provides input data through one of three methods:
direct text entry in a textarea field, file upload supporting binary and text formats,
or JSON import of a previous simulation artifact. For AES operations, the user

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additionally specifies the cipher key in hexadecimal format, the operation mode (ECB
or CBC), and the key size (128 or 256 bits). For SHA-256, only the message input is
required.
Step 2: Input Validation. The system validates all inputs before processing. Key
length verification ensures AES-128 keys contain exactly 32 hex characters and AES-
256 keys contain 64 hex characters. Hexadecimal format validation checks that all
characters are within the valid range [0-9, A-F]. For file inputs, size limits prevent
excessive memory consumption. For JSON imports, schema validation ensures the
artifact contains required fields including algorithm identifier, mode, key hash, and
output ciphertext.
Step 3: Algorithm Execution. For software simulation, the system branches by input
type. Text inputs are encoded using UTF-8 TextEncoder, processed through the se-
lected algorithm, and decoded using TextDecoder. File inputs are read as ArrayBuffer,
processed in chunks for large files, and returned as downloadable Blob objects. For
hardware execution, the system transfers key material and input data to the FPGA
board via the UART interface, triggers execution, and retrieves results through the
command protocol.
Step 4: Visualization Update. During algorithm execution, the visualization engine
receives progress updates through React state changes. For AES, round counters in-
crement sequentially, displaying the current round number, sub-operation status (Sub-
Bytes, ShiftRows, MixColumns, AddRoundKey), and intermediate state values. For
SHA-256, block counters track progress through message scheduling and compression
rounds. Performance metrics update in real-time, showing elapsed time, estimated
throughput, and completion percentage.
Step 5: Result Presentation. Upon completion, results are displayed in multiple for-
mats. The output panel shows the primary result: ciphertext in hexadecimal format
for AES encryption, decrypted plaintext for AES decryption, or hash digest for SHA-
256. The metrics panel shows detailed performance statistics including total execution
time, throughput in Mbps, round count, and comparison with hardware execution
when available. Export options enable downloading results as files or JSON artifacts
for later import.
Step 6: Hardware Validation (Optional). When hardware is connected, the software

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results are automatically compared against FPGA execution. The comparison panel
highlights any discrepancies and shows the hardware speedup factor. This cross-
validation ensures both software correctness and hardware functional accuracy.

3.4 Algorithm Design

The algorithm design encompasses detailed implementations of AES-128, AES-256,

and SHA-256, each following their respective NIST specifications with optimizations
for both software simulation and hardware compatibility.

3.4.1 AES Implementation

The AES algorithm operates on 128-bit data blocks through a substitution-permutation

network. The software implementation supports both ECB and CBC modes with
PKCS7 padding for non-aligned data. The four fundamental transformations are im-
plemented as follows.
SubBytes performs non-linear byte substitution using a precomputed S-box lookup
table. Each byte of the state matrix is replaced by its corresponding S-box value,
providing confusion by obscuring the relationship between ciphertext and key. The
inverse SubBytes operation uses the inverse S-box for decryption.
ShiftRows performs cyclic left shifts on each row of the state matrix. The first row
remains unchanged, the second row shifts by one byte, the third by two bytes, and
the fourth by three bytes. This operation provides diffusion by spreading bytes across
different columns.
MixColumns performs matrix multiplication in the Galois Field GF(28 ), treating each
column as a polynomial and multiplying by a fixed matrix. This operation provides
the primary diffusion mechanism, ensuring that a change in one input byte affects all
output bytes within the column.
AddRoundKey combines the state with the round key through bitwise XOR. For AES-
128, 11 round keys are generated (including the initial key); for AES-256, 15 round
keys are generated. The key expansion algorithm uses RotWord, SubWord, and Rcon
operations to derive each round key from the previous one.
For AES-128, the key expansion generates 11 round keys (44 32-bit words) from the
initial 128-bit cipher key through iterative substitution and rotation operations. AES-
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256 extends this to 15 round keys (60 32-bit words) with additional transformation
complexity, requiring an extra set of SubWord and XOR operations per round key
generation cycle.

3.4.2 SHA-256 Implementation

The SHA-256 hash function processes input data in 512-bit blocks through 64 rounds of
logical operations. The implementation includes complete message padding according
to FIPS 180-4 specifications, with length encoding and bit-wise preprocessing.
Message padding ensures the input length is congruent to 448 modulo 512. A single
’1’ bit is appended, followed by sufficient ’0’ bits, and finally the original message
length encoded as a 64-bit big-endian integer. This padding scheme guarantees that
the padded message can be divided into complete 512-bit blocks.
The compression function maintains eight 32-bit working variables (a through h) up-
dated through the message schedule array W[0..63]. Each round applies the functions
Ch (choice), Maj (majority), Sigma0, and Sigma1, along with constants K[0..63] de-
rived from the fractional parts of cube roots of prime numbers. The final hash value
is the concatenation of the eight working variables after processing all message blocks.
The constant-time nature of SHA-256 operations makes it particularly suitable for
hardware pipelining, as each round requires the same number of operations regardless
of input data. This property enables efficient FPGA implementations where multiple
message blocks can be processed concurrently through staged pipeline stages.
Table 3.2: AES and SHA-256 Specifications

Parameter AES-128 AES-256 SHA-2

Block Size 128 bits 128 bits 512 bi
Key/Digest Size 128 bits 256 bits 256 bi
Rounds 10 14 64
Structure SPN SPN Merkl
Operations SubBytes, ShiftRows, MixColumns, AddRoundKey Same as AES-128 Ch, M
Key Expansion 11 round keys 15 round keys N/A
Padding PKCS7 PKCS7 Length

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3.5 Software Implementation

The software implementation adopts a modern web technology stack optimized for per-
formance, maintainability, and user experience. The 75% software component handles
user interaction, algorithm simulation, visualization, and data persistence.

3.5.1 Frontend Architecture

The frontend is built as a single-page application (SPA) using React 18 with Type-
Script for type safety. React Router DOM handles client-side navigation between
dashboard, AES simulator, SHA simulator, IoT monitor, and RFID pages. The com-
ponent architecture follows atomic design principles with reusable UI primitives from
shadcn/ui and Radix primitives, ensuring accessibility and consistent styling.
State management uses React hooks (useState, useEffect, useCallback) at the page
level, with no global state management library required given the focused scope. Each
page maintains its own simulation state, and navigation between pages preserves no
shared state, simplifying the architecture. TanStack Query provides async data pattern
scaffolding for future backend integrations.
Styling uses Tailwind CSS with a utility-first approach, enabling rapid development
and consistent design language. Custom color tokens derived from the document
palette ensure visual coherence across all pages. The design is responsive, adapting to
different screen sizes through Tailwind’s breakpoint utilities.

3.5.2 Cryptographic Implementation

The cryptographic core uses a dual approach: the Web Crypto API for production-
grade AES-GCM operations and a custom JavaScript implementation for educational
visualization. The Web Crypto API provides high-performance encryption through
the browser’s native implementation, achieving near-native speeds for bulk data pro-
cessing.
For visualization purposes, a custom AES implementation in JavaScript traces each
round’s intermediate states. While slower than the Web Crypto API, this implemen-
tation enables step-by-step observation of SubBytes, ShiftRows, MixColumns, and
AddRoundKey transformations. Users can pause, resume, and step through execution

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at their preferred pace.

SHA-256 is implemented entirely in JavaScript with message scheduling visualiza-
tion. Each of the 64 rounds updates the working variables in real-time, with the
message schedule array W displayed alongside the compression function output. This
transparency helps users understand how hash functions achieve avalanche effect and
collision resistance.
File handling uses the File API and Blob API for reading user uploads and gener-
ating downloadable outputs. Large files are processed in chunks to prevent memory
exhaustion. JSON export includes algorithm metadata, key hashes (not actual keys
for security), timestamps, and output data, enabling reproducible results and session
resumption.

3.5.3 Visualization and Analytics

The visualization layer uses [Link] for algorithm-specific graphics including state matrix
evolution for AES and hash tree diagrams for SHA-256. Recharts provides performance
comparison charts showing throughput, execution time, and round count metrics across
different input sizes and algorithm variants.
ASICMetrics components present modeled hardware characteristics including esti-
mated LUT utilization, clock cycles per operation, and power consumption estimates.
These metrics are derived from analytical models calibrated against actual FPGA mea-
surements, providing educational insight into hardware design considerations without
requiring hardware expertise.
PerformanceChart components use Recharts to render bar charts, line charts, and
radar charts comparing software and hardware execution characteristics. Data is nor-
malized to enable fair comparison across different platforms and input sizes.

3.6 Hardware Integration

The hardware component, comprising 25% of the system scope, provides physical
validation of cryptographic operations and demonstrates real-world performance char-
acteristics. The hardware platform centers on the Vicharak Shrike-lite development
board with support for IoT sensors and RFID authentication modules.

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3.6.1 FPGA Implementation

The FPGA implements round-based AES encryption and SHA-256 compression using
Verilog HDL. The AES core uses a pipelined architecture where each round occupies a
separate stage, enabling new block processing every clock cycle after initial latency. S-
boxes are implemented as lookup tables in distributed RAM, balancing speed against
resource utilization.
The SHA-256 core implements a folded architecture that reuses a single round function
across all 64 rounds, minimizing resource consumption at the cost of higher latency
per block. This approach is suitable for the resource-constrained ForgeFPGA while
still achieving significant speedup over software implementations.
A 6-bit high-speed parallel interface connects the FPGA to the RP2040 microcon-
troller, enabling low-latency data transfer for cryptographic offloading. The interface
uses handshaking signals to ensure reliable communication and supports burst trans-
fers for efficient bulk data movement.

3.6.2 IoT and RFID Integration

The IoT integration layer connects physical sensors to the software platform through
the RP2040 microcontroller. The MPU6050 accelerometer and gyroscope provide mo-
tion data that can trigger security events or serve as input to cryptographic operations.
The vibration sensor detects physical tampering attempts, enabling hardware-level in-
trusion detection.
The RFID module (RC522) handles proximity card authentication, reading tag UIDs
and validating them against an authorized database. Successful authentication grants
access to protected features; failed attempts log security events for audit purposes.
The RFID flow demonstrates how cryptographic primitives can protect physical access
control systems.
All hardware components communicate through standardized protocols: SPI for the
RFID reader, I2C for the MPU6050, and GPIO for the vibration sensor. The RP2040
aggregates sensor data and communicates with the host computer via USB-UART,
presenting a unified interface to the web application.

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Table 3.3: Hardware Component Specifications

Component Model Interface Role in Project

Development Board Vicharak Shrike-lite USB-UART FPGA+MCU platform
Microcontroller RP2040 (Dual-core) Internal Control and communication
FPGA Renesas ForgeFPGA Internal Hardware acceleration
RFID Reader MFRC522 SPI Access control
Motion Sensor MPU6050 I2C Physical monitoring
Vibration Sensor SW-420 GPIO Tamper detection
Power Supply 5V USB-C USB Board power

3.7 Hardware Components

This section provides detailed explanations of each hardware component used in the
project, including their technical specifications, working principles, and roles within the
overall system architecture. Understanding these components is essential for compre-
hending the hardware-software interaction and the IoT security features demonstrated
by the platform.

3.7.1 NodeMCU ESP8266

The NodeMCU ESP8266 is a low-cost Wi-Fi microchip with full TCP/IP stack and
microcontroller capability, widely used in IoT applications. Although the primary de-
velopment board for this project is the Vicharak Shrike-lite, the ESP8266 serves as an
alternative wireless communication module for IoT demonstrations. The ESP8266 fea-
tures a Tensilica L106 32-bit processor running at 80 or 160 MHz, 64 KB of instruction
RAM, 96 KB of data RAM, and external flash memory typically 4 MB.
In the context of this project, the ESP8266 can function as a wireless bridge between
sensor data and the web dashboard. When configured as a soft access point or station
mode, the ESP8266 transmits sensor readings from the MPU6050 and vibration sensor
to the web application via HTTP or MQTT protocols. This wireless capability demon-
strates how cryptographic operations can secure IoT communication over untrusted
networks.
The ESP8266 operates at 3.3V with 5V tolerant GPIO pins, making it compatible
with a wide range of sensors and peripherals. Its built-in Wi-Fi antenna enables

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communication ranges up to 100 meters in open environments. Power consumption

is approximately 80 mA during active transmission and 20 mA in deep sleep mode,
supporting battery-powered deployments.

3.7.2 RFID Reader (RC522)

Figure 3.1: RFID Reader RC522

The MFRC522 is a highly integrated reader/writer for contactless communication at

13.56 MHz, supporting ISO/IEC 14443 A/MIFARE protocols. The module communi-
cates with microcontrollers through SPI at speeds up to 10 Mbps, enabling rapid tag
detection and authentication.
The RC522 module includes an internal antenna with a typical read range of up to 60
mm depending on the tag type and environmental conditions. It supports MIFARE
Classic 1K and 4K cards, MIFARE Ultralight, and compatible tags. The module
operates at 3.3V and consumes approximately 13-26 mA during active reading.
In the project architecture, the RC522 serves as the physical access control interface.
When an RFID tag is brought near the reader, the module detects the tag’s UID
(Unique Identifier), reads stored authentication data, and transmits this information
to the RP2040 microcontroller. The microcontroller forwards the data to the web
application, which validates the tag against an authorized database and displays the
access decision.

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3.7.3 MPU6050 Sensor

The MPU6050 is a six-axis motion tracking device combining a 3-axis accelerometer

and 3-axis gyroscope in a single package. It uses MEMS (Micro-Electro-Mechanical
Systems) technology to measure acceleration and rotational velocity with 16-bit reso-
lution per axis.
The accelerometer measures acceleration in the range of ±2g, ±4g, ±8g, or ±16g,
selectable through programmable full-scale ranges. The gyroscope measures angular
rate in ranges of ±250, ±500, ±1000, or ±2000 degrees per second. The device includes
a Digital Motion Processor (DMP) that offloads motion processing algorithms from
the host microcontroller.
Communication with the MPU6050 occurs via I2C at speeds up to 400 kHz. The
device address is 0x68 (or 0x69 when AD0 pin is high). A FIFO buffer stores sensor
readings, enabling burst data retrieval and reducing host processor overhead. Power
consumption is approximately 3.9 mA in normal mode and 2.5 µ A in sleep mode.
In the project context, the MPU6050 demonstrates environmental monitoring applica-
tions of cryptography. Sensor readings can be signed using HMAC-SHA256 to ensure
data integrity during transmission. Anomaly detection algorithms identify unusual
motion patterns that may indicate tampering or unauthorized access attempts.

3.7.4 Vibration Sensor (SW-420)

The SW-420 is a digital vibration sensor module that detects shock and vibration
through a spring-type switch mechanism. When vibration exceeds a threshold, the
switch closes, triggering a digital output signal. The module includes an LM393 com-
parator for signal conditioning, providing a clean digital output to the microcontroller.
The sensor operates at 3.3V to 5V and provides both analog and digital outputs.
The digital output goes LOW when vibration is detected, enabling interrupt-driven
detection on the microcontroller. Sensitivity can be adjusted through a potentiometer
on the module, allowing calibration for different application requirements.
In the project architecture, the vibration sensor serves as a physical tamper detection
mechanism. When installed on an enclosure containing sensitive equipment, vibration
triggers a security event that is logged and reported through the web dashboard. This
demonstrates how physical security can be integrated with cryptographic monitoring
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systems.

3.7.5 Vicharak Shrike-lite FPGA Development Board

Figure 3.2: Vicharak Shrike-Lite FPGA Development Board (Representative Image)

The Vicharak Shrike-lite development board serves as the primary hardware platform
for this project. It features a unique hybrid architecture combining a RISC-V RP2040
microcontroller with a Renesas ForgeFPGA, enabling both software control and hard-
ware acceleration within a single compact board.
The RP2040 microcontroller is a dual-core ARM Cortex-M0+ device running at 133
MHz with 264 KB of SRAM and 4 MB of external flash memory. Its two cores enable
parallel processing: one core manages USB communication and application logic while
the other handles hardware interface protocols. The PIO (Programmable I/O) blocks
enable custom peripheral interfaces without dedicated hardware support.
The Renesas ForgeFPGA (SLG47910V) provides 1,120 Look-Up Tables (LUTs), 1,120
D-Flip Flops (DFFs), and 32 KB of Block RAM (BRAM). This compact FPGA is ideal
for learning and prototyping cryptographic hardware, offering sufficient resources for
AES and SHA-256 cores while remaining approachable for educational use. The FPGA
is programmed through a USB-UART bridge connected to the RP2040.
Key board specifications include: 37 GPIO pins for external connections, a PMOD
expansion connector for standardized peripheral modules, USB-C for power and pro-

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gramming, and a 50 MHz system clock. The board measures 60 mm by 25 mm, making
it suitable for embedded deployments and portable demonstrations.

3.8 System and Architecture Diagrams

Figure 3.3: Block diagram of Implementation of Efficient Cryptographic Algorithm

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Figure 3.4: Algorithm Flow chart of Implementation of Efficient Cryptographic Algo-

rithm

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Figure 3.5: System Architecture of Implementation of Efficient Cryptographic Algo-

rithm

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Figure 3.6: Model Architecture of Implementation of Efficient Cryptographic Algo-

rithm

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CHAPTER 4
PERFORMANCE ANALYSIS

4.1 Algorithm Analysis

This section provides detailed analysis of the AES and SHA-256 algorithms imple-
mented in the project, including their mathematical foundations, operational steps,
and comparative characteristics. Understanding these algorithms at a granular level
is essential for appreciating the design decisions made in both software and hardware
implementations.

4.1.1 Advanced Encryption Standard (AES)

AES is a symmetric block cipher that encrypts 128-bit blocks using keys of 128, 192,
or 256 bits. This project implements AES-128 and AES-256, providing users with
options balancing speed and security margin. The algorithm’s security relies on the
substitution-permutation network design, combining non-linear substitution (confu-
sion) with linear mixing (diffusion) across multiple rounds.
The AES encryption process begins with an initial AddRoundKey operation, followed
by a series of identical rounds. For AES-128, there are 10 rounds; for AES-256, 14
rounds. Each round except the final one consists of four transformations: SubBytes,
ShiftRows, MixColumns, and AddRoundKey. The final round omits MixColumns,
ensuring the decryption process can mirror the encryption structure.
SubBytes applies a fixed substitution table (S-box) to each byte of the state. The
S-box is constructed by combining multiplicative inversion in GF(28 ) with an affine
transformation. This non-linear operation provides resistance against differential and
linear cryptanalysis by ensuring that small changes in input produce unpredictable
changes in output.
ShiftRows cyclically shifts the bytes in each row of the 4x4 state matrix. Row 0
is unchanged, row 1 shifts left by 1 byte, row 2 by 2 bytes, and row 3 by 3 bytes.
This operation spreads bytes across columns, enabling diffusion in combination with
MixColumns.
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MixColumns operates on each column independently, treating the column as a poly-

nomial over GF(28 ) and multiplying it by a fixed polynomial modulo x4 + 1. The fixed
matrix ensures that each output byte depends on all four input bytes of the column,
providing strong diffusion within each column.
AddRoundKey combines the state with the round key through simple bitwise XOR.
The round keys are derived from the cipher key through the key expansion algorithm,
which uses RotWord (byte rotation), SubWord (S-box application), and XOR with
round constants (Rcon) to generate each subsequent round key.
The key expansion for AES-128 generates 44 32-bit words (11 round keys). For AES-
256, 60 32-bit words (15 round keys) are generated. The longer key schedule in AES-
256 provides enhanced security against brute-force attacks at the cost of additional
computation and memory requirements.

4.1.2 Secure Hash Algorithm (SHA-256)

SHA-256 is a cryptographic hash function producing a 256-bit digest from arbitrary-

length input. It belongs to the SHA-2 family specified in FIPS 180-4 and is widely used
for data integrity verification, digital signatures, password hashing, and blockchain
applications. Unlike AES, SHA-256 is a one-way function: given a digest, it is com-
putationally infeasible to determine the original input.
The SHA-256 algorithm operates in two phases: message preprocessing and hash com-
putation. Message preprocessing involves padding the input to a multiple of 512 bits,
parsing the padded message into 512-bit blocks, and initializing eight 32-bit working
variables with fractional parts of square roots of the first eight prime numbers.
Padding appends a single ’1’ bit to the message, followed by enough ’0’ bits to make
the length congruent to 448 modulo 512, and finally a 64-bit big-endian integer repre-
senting the original message length. This padding scheme ensures the message can be
evenly divided into 512-bit blocks while encoding the original length for security.
Hash computation processes each 512-bit block through 64 rounds. Each round up-
dates eight working variables (a, b, c, d, e, f, g, h) using the message schedule array
W[0..63], round constants K[0..63], and logical functions Ch, Maj, Sigma0, and Sigma1.
The message schedule is generated from the current block by iterative word expansion
combining XOR, ROTR (rotate right), and SHR (shift right) operations.

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 IMPLEMENTATION OF EFFICIENT CRYPTOGRAPHIC ALGORITHM

The Ch (choice) function selects bits from one input based on another: Ch(x,y,z) =
(x AND y) XOR (NOT x AND z). The Maj (majority) function outputs the majority
bit value among three inputs: Maj(x,y,z) = (x AND y) XOR (x AND z) XOR (y AND
z). Sigma0 and Sigma1 are more complex rotation and shift combinations providing
diffusion across the word.
After processing all blocks, the final hash value is the concatenation of the eight
working variables. The design ensures that any change in the input, however small,
produces a completely different digest with approximately 50% of bits changed, a
property known as the avalanche effect. SHA-256 maintains 128-bit collision resistance,
meaning finding two different inputs with the same hash requires approximately 2128
operations, well beyond current computational capabilities.

4.1.3 Algorithm Comparison

AES and SHA-256 serve fundamentally different security purposes and exhibit distinct
operational characteristics. AES provides reversible encryption for confidentiality:
given ciphertext and the correct key, the original plaintext can be recovered. SHA-256
provides irreversible hashing for integrity: given a digest, no efficient method exists to
find the original input.
The complementary nature of these algorithms makes them ideal for combined use in
security protocols. For example, AES encrypts data for confidentiality while SHA-256
generates a message authentication code (HMAC) for integrity verification. In the con-
text of this project, both algorithms are implemented to demonstrate a comprehensive
cryptographic toolkit.

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 IMPLEMENTATION OF EFFICIENT CRYPTOGRAPHIC ALGORITHM

Table 4.1: AES vs SHA-256 Comparison

Characteristic AES-128 AES-256 SHA-256

Type Symmetric cipher Symmetric cipher Hash function
Reversibility Reversible (with key) Reversible (with key) Irreversible
Primary Use Confidentiality Confidentiality Integrity
Block Size 128 bits 128 bits 512 bits (input)
Output Size 128 bits 128 bits 256 bits
Key Size 128 bits 256 bits N/A
Rounds 10 14 64
Security Level 128 bits 256 bits 128-bit collision res.
SW Time (1KB) ∼12.4 ms/block ∼18.7 ms/block ∼8.3 ms/block
HW Time (1KB) ∼0.38 ms/block ∼0.52 ms/block ∼0.21 ms/block

4.2 System Development

The system development followed an iterative approach combining elements of agile

methodology with the structured phases required for hardware-software integration.
This section describes the development approach, phases, and outcomes.

4.2.1 Development Approach

The project adopted a hybrid development methodology: agile sprints for the software
frontend and simulation core, combined with a V-model approach for hardware design
and integration. This dual methodology recognized the different risk profiles and
verification requirements of software and hardware components.
For software development, two-week sprints focused on delivering functional increments
of the web application. Each sprint included planning, implementation, testing, and
review phases. Sprint goals prioritized user-facing features early, ensuring continuous
stakeholder feedback. The React component architecture enabled parallel development
of different page flows by team members.
For hardware development, the V-model ensured that each design phase had cor-
responding verification. Requirements analysis defined FPGA resource budgets and
timing constraints. Architectural design specified module interfaces and data paths.
Detailed design produced Verilog code for AES and SHA-256 cores. Unit testing veri-
fied individual modules against test vectors. Integration testing validated the complete

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 IMPLEMENTATION OF EFFICIENT CRYPTOGRAPHIC ALGORITHM

hardware-software interface.
Continuous integration was maintained through Git version control with feature branches
for each component. Pull requests required code review before merging to the main
branch. The hardware repository included simulation testbenches that could be run
automatically to verify RTL changes.

4.2.2 Development Phases

Phase 1: Planning and Requirements Analysis (Weeks 1-2). This phase established
project scope, identified hardware platforms, selected the technology stack, and defined
performance targets. Stakeholder interviews with faculty advisors clarified educational
objectives and evaluation criteria. A detailed project plan with milestones and deliv-
erables was created and approved.
Phase 2: System Design (Weeks 3-4). The software architecture was designed with
component diagrams and state machines. The hardware architecture was specified
with block diagrams, interface protocols, and resource budgets. FPGA pin assignments
were planned for the Vicharak Shrike-lite board. The database schema for RFID tag
management was defined.
Phase 3: Software Implementation (Weeks 5-8). The React application was scaffolded
with Vite, component libraries were configured, and routing was established. Cryp-
tographic implementations were developed and tested against NIST test vectors. Vi-
sualization components were built with [Link] and Recharts. The dashboard interface
was designed and implemented with responsive layout.
Phase 4: Hardware Implementation (Weeks 7-10). Verilog modules for AES and SHA-
256 were coded and simulated using open-source tools. The FPGA bitstream was
synthesized and uploaded to the Vicharak Shrike-lite board. RP2040 firmware was
developed in C/C++ for control and communication. Sensor interfaces were imple-
mented and tested.
Phase 5: Integration and Testing (Weeks 9-12). Software and hardware components
were integrated through the UART protocol. End-to-end testing verified complete
data flows from user input through hardware execution and back to result display.
Performance benchmarks were conducted across multiple input sizes. Edge cases and
error conditions were tested.

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Phase 6: Documentation and Deployment (Weeks 11-14). User documentation was

written, including installation guides, usage tutorials, and API references. Technical
documentation captured design decisions, implementation details, and performance
results. The application was deployed to a static hosting platform for remote access.
The final report was compiled.

4.3 Software Requirements

The software requirements encompass functional requirements defining what the sys-
tem must do, non-functional requirements specifying quality attributes, and opera-
tional requirements describing runtime conditions.

4.3.1 Project Requirements

Functional requirements include: (1) AES-128 and AES-256 encryption and decryption
with ECB and CBC mode support; (2) SHA-256 hash generation with visualization;
(3) Real-time algorithm execution visualization showing intermediate states; (4) File
upload and download for bulk data processing; (5) JSON artifact import and export
for session persistence; (6) Hardware integration for FPGA-based validation; (7) IoT
sensor data display and RFID authentication flow; (8) Performance metrics calculation
and display; (9) Responsive design supporting desktop and tablet browsers.
Non-functional requirements include: (1) Execution accuracy matching NIST test vec-
tors with 100% correctness; (2) Software simulation accuracy within 15% of hardware
timing predictions; (3) Web application load time under 3 seconds on broadband con-
nections; (4) Cryptographic operation feedback within 500ms for text inputs under
1KB; (5) Browser compatibility with Chrome, Firefox, Safari, and Edge current ver-
sions; (6) Accessibility compliance with WCAG 2.1 Level AA guidelines.

4.3.2 Project Operations

The system operates primarily within the user’s web browser, executing cryptographic
algorithms using JavaScript and the Web Crypto API. All computation occurs client-
side, ensuring data privacy by preventing transmission of sensitive information to
external servers. The optional Python Flask backend provides additional processing

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capabilities for users who require server-side operations or multi-user collaboration.

Normal operation involves the user selecting an algorithm from the dashboard, en-
tering input data and keys, initiating execution, observing visualization updates, and
reviewing results. For hardware validation, the user connects the Vicharak Shrike-lite
board via USB, the application detects the connection, and subsequent operations offer
hardware execution as an option.
Offline operation is supported through Progressive Web App (PWA) capabilities. Once
loaded, the application caches static assets and can operate without network connectiv-
ity for all software-based operations. Hardware validation requires USB connectivity
but no internet access.
Data export operations generate JSON artifacts containing algorithm metadata, key
hashes, timestamps, and output data. These artifacts can be imported in subsequent
sessions to resume work or share results with collaborators. File download operations
use browser Blob and URL APIs to create temporary download links.

4.3.3 Software Tools

The frontend toolchain includes React 18 for UI components, React Router DOM for
navigation, Tailwind CSS for styling, shadcn/ui and Radix primitives for accessible
UI components, Sonner for toast notifications, Recharts for performance charts, and
Lucide React for iconography. The build pipeline uses Vite with the SWC transform
for fast compilation and hot module replacement.
Cryptographic libraries include the Web Crypto API for production AES-GCM op-
erations, a custom JavaScript AES implementation for visualization, and a custom
SHA-256 implementation for hash generation with round tracing. For users requir-
ing Python backend integration, PyCryptodome provides compatible cryptographic
primitives.
Development tools include Visual Studio Code as the primary IDE, ESLint for static
code analysis, npm for package management, and GitHub for version control and col-
laboration. Testing uses browser developer tools for debugging and manual verification
against NIST test vectors.

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Table 4.2: Software Environment Specifications

Component Specification
Frontend Framework React 18, TypeScript
Routing React Router DOM
Styling Tailwind CSS
UI Components shadcn/ui, Radix primitives
Visualization [Link], Recharts, [Link]
Crypto Libraries Web Crypto API, CryptoJS
Build Tool Vite with SWC
Package Manager npm
Backend (Optional) Python 3.9, Flask
Python Crypto PyCryptodome 3.15.0
Browser Support Chrome, Firefox, Safari, Edge

4.4 Development Tools

The development environment combines modern web development tools with embed-
ded systems programming utilities, reflecting the hybrid nature of the project. Each
tool was selected based on productivity, compatibility, and community support.
Visual Studio Code served as the primary integrated development environment, con-
figured with extensions for React, TypeScript, Tailwind CSS, and ESLint. The IDE’s
debugging capabilities for both JavaScript and C/C++ enabled efficient troubleshoot-
ing across the software-hardware boundary.
Version control used Git with a centralized repository on GitHub. The repository was
organized into frontend, hardware, documentation, and testing directories. Branch
protection rules required pull request reviews before merging to the main branch.
GitHub Issues tracked bugs and feature requests.
For hardware development, the Renesas ForgeFPGA toolchain provided synthesis,
place-and-route, and bitstream generation. The RP2040 was programmed using the
Pico SDK with GCC cross-compilation. Open-source Verilog simulation tools enabled
pre-synthesis verification of AES and SHA-256 modules.
Testing and verification relied on NIST SP 800-38A test vectors for AES validation
and NIST CAVP test vectors for SHA-256 verification. Performance measurement
used browser Performance API for precise timing and Python time module for backend

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benchmarks.

4.5 Experimental Analysis and Results

Performance evaluation was conducted across three environments: (1) Web-based

JavaScript implementation running on the Chrome V8 engine; (2) Python Flask back-
end using CPython 3.9; and (3) FPGA hardware acceleration on the Vicharak Shrike-
lite board with a 50 MHz system clock. Test vectors were derived from NIST SP
800-38A and FIPS 197 specifications for validation.

4.5.1 Performance Testing and Response Time

Encryption performance was measured for AES-128 and AES-256 across software and
hardware implementations. Table 7 presents the comparative performance metrics.
Table 4.3: AES Performance Comparison

Implementation Key Size Rounds SW Time (ms) HW Time (ms) Speedup

AES-128 (SW) 128-bit 10 12.4 — —
AES-128 (HW) 128-bit 10 — 0.38 32.6x
AES-256 (SW) 256-bit 14 18.7 — —
AES-256 (HW) 256-bit 14 — 0.52 36.0x

Results indicate that AES-128 achieves optimal throughput for bulk data encryption,
while AES-256 provides enhanced security margin with acceptable performance over-
head. The FPGA implementation demonstrates consistent 32-36x speedup across key
sizes, validating the efficiency of hardware acceleration. The speedup is attributed to
parallel execution of round operations, dedicated arithmetic circuits in the FPGA, and
elimination of software interpretation overhead.
SHA-256 software implementation processes 512-bit blocks in approximately 8.3 ms per
block, achieving throughput of 61.7 Mbps. Hardware acceleration reduces this to 0.21
ms per block (2.44 Gbps throughput), representing a 39.5x performance improvement.
The constant-time nature of SHA-256 operations makes it particularly suitable for
hardware pipelining, as each round requires identical operations regardless of input
data.

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Table 4.4: SHA-256 Performance Comparison

Implementation Time per Block (ms) Throughput Speedup

SHA-256 (JavaScript) 8.3 61.7 Mbps —
SHA-256 (Python) 6.2 82.6 Mbps 1.3x
SHA-256 (FPGA) 0.21 2.44 Gbps 39.5x

Accuracy validation compared software simulation timing against hardware execution

for 1000 test vectors of varying sizes. The software simulation achieved 85% correlation
with hardware timing characteristics for AES operations and 88% correlation for SHA-
256. The discrepancy arises from JavaScript runtime overhead, garbage collection
pauses, and visualization update delays that are not present in hardware execution.
Resource utilization on the FPGA was monitored during hardware synthesis. Table 9
summarizes the consumption.
Table 4.5: FPGA Resource Utilization

Component LUTs DFFs BRAM (KB) Power (mW)

AES-128 Core 312 298 8 12.4
AES-256 Core 456 412 12 18.7
SHA-256 Core 287 245 6 9.8
UART Interface 89 76 2 4.2
Total 1,144 1,031 28 45.1

The design efficiently utilizes available resources while maintaining headroom for ad-
ditional functionality. Total power consumption remains below 50 mW, suitable for
battery-operated IoT deployments. The resource utilization demonstrates that all
three cryptographic cores can coexist on the compact ForgeFPGA while leaving ca-
pacity for control logic and interfaces.

4.5.2 Security Analysis

The implemented algorithms demonstrate resistance against known cryptanalytic at-

tacks. AES’s wide trail strategy provides proven resistance against differential and
linear cryptanalysis; our implementation maintains full round count without short-
cuts that could compromise security. The 10-round AES-128 and 14-round AES-256
implementations exceed the minimum rounds required for security margins.
The hardware implementation includes basic timing attack countermeasures through
constant-time S-box access. While advanced side-channel protections such as power
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 IMPLEMENTATION OF EFFICIENT CRYPTOGRAPHIC ALGORITHM

analysis masking are not implemented in this version, the architecture supports their
addition as future enhancements.
SHA-256 maintains 128-bit collision resistance, sufficient for current security require-
ments. The implementation correctly applies message padding and length encoding,
preventing length extension attacks that exploit improperly padded messages.

4.6 Dashboard and Output Analysis

Figure 4.1: Dashboard Overview

Figure 4.2: Encryption Result Analysis

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Figure 4.3: Decryption Verification

Figure 4.4: Performance Analysis: Power Comparison

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Figure 4.5: Performance Analysis: Throughput Comparison

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CHAPTER 5
CONCLUSION

5.1 Conclusion

This project presented a hybrid software-hardware platform for efficient cryptographic

algorithm implementation, combining web-based simulation with FPGA-based hard-
ware validation. The system successfully implements AES-128, AES-256, and SHA-
256 with comprehensive performance analysis and real-time visualization. Through
systematic design, implementation, and evaluation, the project achieved its stated ob-
jectives and demonstrated the viability of accessible hybrid cryptographic platforms.
Key achievements of the project include the following outcomes. First, the web-based
simulation platform provides accurate, interactive visualization of internal algorithmic
states for all three cryptographic primitives. Students and researchers can observe how
plaintext transforms into ciphertext through AES rounds, how keys expand through
the key schedule, and how messages compress into hash digests through SHA-256 op-
erations. This visibility addresses the long-standing accessibility gap in cryptographic
education.
Second, FPGA-based hardware validation using the Vicharak Shrike-lite board achieved
significant performance acceleration. The hardware implementation demonstrated
32.6x speedup for AES-128, 36.0x speedup for AES-256, and 39.5x speedup for SHA-
256 compared to optimized JavaScript implementations. These results validate the effi-
ciency of hardware acceleration and provide students with quantitative understanding
of software-hardware performance trade-offs.
Third, the 75/25 software-hardware split achieved optimal balance between accessibil-
ity and validation accuracy. The majority software component ensures the platform
remains approachable for users without hardware expertise or equipment, while the
minority hardware component provides meaningful physical validation for users with
access to the development board. This balance makes the platform suitable for diverse
educational and research contexts.
Fourth, IoT security integration through RFID authentication and sensor monitoring

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 IMPLEMENTATION OF EFFICIENT CRYPTOGRAPHIC ALGORITHM

demonstrated practical applications of cryptographic primitives beyond theoretical ex-

ercise. The access control flow, sensor data integrity protection, and tamper detection
showcase how AES and SHA-256 protect real-world embedded systems.
Fifth, performance analysis established that the software simulation achieves 85% cor-
relation with hardware timing characteristics, validating its effectiveness as a predictive
model. This correlation enables meaningful performance estimation for users who do
not have hardware available, extending the platform’s educational value.
The project demonstrates that effective cryptographic education and research need
not require expensive hardware investments. By providing a comprehensive, acces-
sible platform with optional hardware validation, the system democratizes access to
advanced cryptographic analysis while maintaining the analytical rigor necessary for
professional security applications.

5.2 Future Scope

While the current implementation achieves its primary objectives, several extensions
and improvements are identified for future development. These enhancements would
expand the platform’s capabilities, improve security margins, and extend applicability
to emerging domains.
Integration of post-quantum cryptographic algorithms represents the most significant
future direction. As quantum computing advances, traditional public-key algorithms
face existential threats from Shor’s algorithm. Post-quantum candidates including
Kyber for key encapsulation and Dilithium for digital signatures can be added to the
platform, preparing users for the post-quantum transition. The hybrid architecture is
well-suited for post-quantum integration, as these algorithms can be implemented in
both software and FPGA layers.
Development of comprehensive side-channel attack countermeasures would enhance
the hardware implementation’s security. Power analysis masking, timing attack mit-
igation, and electromagnetic leakage reduction can be implemented in the FPGA de-
sign. Educational modules demonstrating these attacks and countermeasures would
provide valuable learning experiences for security students.
Implementation of complete TLS 1.3 and DTLS protocol stacks would demonstrate
how the platform’s cryptographic primitives integrate into real-world secure commu-
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 IMPLEMENTATION OF EFFICIENT CRYPTOGRAPHIC ALGORITHM

nication. The protocol stack implementation would include handshake management,

cipher suite negotiation, session resumption, and certificate validation, providing end-
to-end examples of cryptographic protocol operation.
Deployment on lower-power FPGA platforms would extend applicability to ultra-
constrained IoT devices. The Gowin GW1NZ-LV1 FPGA and similar low-cost de-
vices can host reduced-complexity cryptographic cores suitable for sensor nodes and
wearable devices. Power consumption below 10 mW would enable energy-harvesting
deployments.
Blockchain integration would demonstrate SHA-256’s critical role in cryptocurrency
and distributed ledger systems. A simplified blockchain demonstration showing block
hashing, chain validation, and proof-of-work concepts would connect the platform to
one of the most visible modern applications of cryptographic hashing.
Machine learning integration for anomaly detection in IoT data streams would show-
case the intersection of artificial intelligence and cryptography. Encrypted model
inference, privacy-preserving federated learning, and secure multi-party computation
represent cutting-edge research directions that could be demonstrated on the platform.
Mobile application development would extend platform accessibility to smartphone
and tablet users. A React Native application could provide the same cryptographic
simulation and hardware control capabilities on iOS and Android devices, enabling
field demonstrations and portable laboratory exercises.
Cloud backend integration would enable multi-user collaboration, remote hardware
sharing, and centralized result storage. A serverless architecture using modern cloud
functions could provide scalable backend services without dedicated server mainte-
nance, while end-to-end encryption ensures data privacy.

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BIBLIOGRAPHY

[1] J. Daemen and V. Rijmen, ”The Design of Rijndael: AES - The Advanced En-
cryption Standard,” Springer-Verlag, 2021.

[2] National Institute of Standards and Technology (NIST), ”FIPS PUB 197: Ad-
vanced Encryption Standard (AES),” U.S. Department of Commerce, 2001.

[3] NIST, ”FIPS PUB 180-4: Secure Hash Standard (SHA-2 Family),” U.S. Depart-
ment of Commerce, 2015.

[4] W. Stallings, Cryptography and Network Security: Principles and Practice, 7th
ed. Pearson Education, 2017.

[5] N. Renugadevi et al., ”Low Area and High Throughput Implementation of AES
Algorithm on FPGA,” in Proc. IEEE Int. Conf. Computing and Communication
Systems (ICCCS), 2022, pp. 1-6.

[6] V. T. Nguyen et al., ”AES-RV: RISC-V Based Accelerator for IoT Security Ap-
plications,” IEEE Trans. VLSI Systems, vol. 33, no. 2, pp. 245-258, 2025.

[7] R. S. Jabbar, ”AES Key Generation using SHA-256 for Image Encryption,” Int.
J. Advanced Scientific Research and Engineering, vol. 8, no. 3, pp. 112-119, 2024.

[8] Aalto University Research Group, ”Design and Implementation of RISC-V Core
Integrated with AES-256 Accelerator,” Aalto University Technical Reports, 2024.

[9] MDPI Authors, ”Security Evaluation of Lightweight AES Accelerators for IoT
Devices,” Electronics, vol. 13, no. 8, p. 1567, 2024.

[10] H. Zhu et al., ”FPGA-Based High-Performance SHA-256 Accelerator for

Blockchain Systems,” in Proc. IEEE Int. Symp. Circuits and Systems (ISCAS),
2023, pp. 1-5.

[11] G. Singh et al., ”Comparative Analysis of AES and DES in Data Security Sys-
tems,” Int. J. Computer Science and Applications, vol. 12, no. 2, pp. 45-52, 2023.
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[12] K. Reddy and P. Mishra, ”Performance Optimization of AES and SHA Algorithms
in Cloud Environments,” Int. J. Cloud Computing and Security, vol. 9, no. 4, pp.
78-89, 2024.

[13] A. Kumar and S. Sharma, ”Implementation of AES Encryption on IoT Edge

Devices Using Python and FPGA,” in Proc. IEEE Int. Conf. Emerging Trends in
Computing (ICETC), 2021, pp. 234-239.

[14] R. Patel and V. Deshmukh, ”Analysis of Hybrid Cryptographic Techniques Com-

bining AES and SHA for Data Protection,” J. Information Security and Applica-
tions, vol. 58, p. 102789, 2020.

[15] NXP Semiconductors, ”MFRC522 RFID Reader IC Datasheet,” Technical Docu-

mentation, 2016.

[16] Gowin Semiconductor Corp., ”GW1NZ-LV1 FPGA Datasheet,” Tang Nano 1K

Series Reference Manual, 2021.

[17] Sabanci et al., ”Feasibility of Integrating Post-Quantum Cryptographic Schemes

into TLS 1.3 in NB-IoT Networks,” IEEE Internet of Things Journal, vol. 11, no.
15, pp. 26789-26801, 2024.

[18] Cavo et al., ”Area- and Power-Efficient Crypto Processor for 3GPP-LTE NB-IoT
Devices,” IEEE Trans. Circuits and Systems I, vol. 70, no. 8, pp. 3345-3358, 2023.

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Appendix: Source Code

Listing 1: Implementation of Efficient Cryptographic Algorithm — Demo ([Link])

1 import React , { useState } from "react ";
2 import CryptoJS from "crypto -js";
3 import { saveAs } from "file -saver ";
4

5 function hexToWordArray (hex) {

6 const words = CryptoJS .[Link] (hex);
7 return words;
8 }
9

10 function wordArrayToHex ( wordArray ) {

11 return CryptoJS .[Link]. stringify ( wordArray );
12 }
13

14 function bytesToHex (bytes ) {

15 return [Link](bytes).map(b => b. toString (16). padStart (2,'0')
).join ('');
16 }
17

18 function sha256HexFromText (text) {

19 return CryptoJS . SHA256 ( CryptoJS .enc.Utf8. parse (text)). toString (
CryptoJS .[Link]);
20 }
21

22 function aesEncryptHex (plainHex , keyHex , mode='AES -128 ') {

23 // CryptoJS wants WordArray ; we use ECB + PKCS7 default , but use
CBC? We 'll use ECB for single -block demonstration .
24 const keyWords = hexToWordArray ( keyHex );
25 const plaintextWords = hexToWordArray ( plainHex );
26 const encrypted = CryptoJS .AES. encrypt ( plaintextWords , keyWords ,
{ mode: CryptoJS .[Link] , padding : CryptoJS .pad. Pkcs7 });
27 // Ciphertext is base64 string ; convert to hex:
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 IMPLEMENTATION OF EFFICIENT CRYPTOGRAPHIC ALGORITHM

28 const ct = CryptoJS .enc. Base64 .parse ( encrypted . toString ());

29 return wordArrayToHex (ct);
30 }
31

32 function aesDecryptHex (cipherHex , keyHex , mode='AES -128 ') {

33 const keyWords = hexToWordArray ( keyHex );
34 const cipherWords = CryptoJS .[Link]. parse ( cipherHex );
35 const cipherBase64 = CryptoJS .enc. Base64 . stringify ( cipherWords );
36 try {
37 const decrypted = CryptoJS .AES. decrypt ( cipherBase64 , keyWords ,
{ mode: CryptoJS .[Link] , padding : CryptoJS .pad. Pkcs7 });
38 return wordArrayToHex ( decrypted );
39 } catch (e) {
40 return null;
41 }
42 }
43

44 export default function App (){

45 const [algo , setAlgo ] = useState ("AES -128") ;
46 const [mode , setMode ] = useState (" encrypt "); // encrypt or
decrypt or hash
47 const [inputHex , setInputHex ] = useState ("");
48 const [keyHex , setKeyHex ] = useState ("");
49 const [resultHex , setResultHex ] = useState ("");
50 const [timeMs , setTimeMs ] = useState (null);
51 const [notes , setNotes ] = useState ("");
52 const [ intermediate , setIntermediate ] = useState ([]);
53

54 const onRun = () => {

55 setResultHex ("");
56 setTimeMs (null);
57 setNotes ("");
58 setIntermediate ([]);
59 // Basic validation

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60 const sanitizedInput = inputHex . replace (/[^0 -9a-fA -F]/g,'');

61 const sanitizedKey = keyHex . replace (/[^0 -9a-fA -F]/g,'');
62 if(algo === "SHA -256") {
63 const t0 = performance .now ();
64 const digest = sha256HexFromText ( sanitizedInput . length ?
CryptoJS .[Link]( sanitizedInput ). toString ( CryptoJS .
enc.Utf8) : "");
65 const t1 = performance .now ();
66 setResultHex ( digest );
67 setTimeMs ((t1 -t0). toFixed (3));
68 setNotes ("SHA -256 is a one -way hash function . Decrypt is not
supported .");
69 setIntermediate ([[" Input (hex)", sanitizedInput ], [" SHA256
Digest ", digest ]]);
70 return ;
71 }
72 // AES paths
73 // Validate key length
74 const requiredKeyLen = algo === "AES -128" ? 32 : 64;
75 if( sanitizedKey . length !== requiredKeyLen ){
76 setNotes (` Invalid key length for ${algo }. Expected ${
requiredKeyLen } hex chars .`);
77 return ;
78 }
79 // Validate input for decrypt mode: must be multiple of 32 hex
chars (16 bytes)
80 if(mode === " decrypt " && ( sanitizedInput . length % 32 !== 0)){
81 setNotes (" For decryption , ciphertext hex length must be
multiple of 32 (16 bytes).");
82 return ;
83 }
84 if(mode === " encrypt "){
85 // require plaintext hex; if odd length , pad
86 let dataHex = sanitizedInput ;

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 IMPLEMENTATION OF EFFICIENT CRYPTOGRAPHIC ALGORITHM

87 // pad PKCS7 if not multiple of 32 hex chars

88 if( dataHex . length % 32 !== 0){
89 // compute needed bytes
90 const missing = 32 - ( dataHex . length % 32);
91 // PKCS7 padding value in bytes = missing /2? careful : here
missing is hex chars; missingBytes = missing /2
92 const missingBytes = [Link]( missing /2);
93 const padByte = missingBytes . toString (16). padStart (2,'0');
94 dataHex = dataHex + padByte . repeat ( missingBytes );
95 }
96 const t0 = performance .now ();
97 // process block by block (ECB)
98 let outHex = "";
99 for(let i=0;i< dataHex . length ;i+=32) {
100 const block = dataHex .slice(i,i+32);
101 const ct = aesEncryptHex (block , sanitizedKey , algo);
102 outHex += ct;
103 // simple intermediate logging
104 setIntermediate (prev => [... prev , [` Block ${i/32}
plaintext `, block], [`Block ${i/32} ciphertext `, ct ]]);
105 }
106 const t1 = performance .now ();
107 setResultHex ( outHex );
108 setTimeMs ((t1 -t0). toFixed (3));
109 } else { // decrypt
110 const t0 = performance .now ();
111 let outHex = "";
112 for(let i=0;i< sanitizedInput . length ;i +=32) {
113 const block = sanitizedInput .slice (i,i+32);
114 const pt = aesDecryptHex (block , sanitizedKey , algo);
115 outHex += pt;
116 setIntermediate (prev => [... prev , [` Block ${i/32}
ciphertext `, block], [`Block ${i/32} plaintext `, pt ]]);
117 }

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 IMPLEMENTATION OF EFFICIENT CRYPTOGRAPHIC ALGORITHM

118 const t1 = performance .now ();

119 setResultHex ( outHex );
120 setTimeMs ((t1 -t0). toFixed (3));
121 }
122 };
123

124 const onCopy = () => {

125 navigator . clipboard . writeText ( resultHex );
126 };
127

128 const onExport = () => {

129 const blob = new Blob ([` algo:${algo }\ nmode :${mode }\ nresult :${
resultHex }\ nmetrics : time=${ timeMs }ms `], {type :" text/ plain;
charset =utf -8"});
130 saveAs (blob , " cryptoalgo_result .txt ");
131 };
132

133 return (
134 <div className =" app">
135 <div className =" header ">
136 <div >
137 <div className =" title"> Implementation of Efficient
Cryptographic Algorithm — Demo </div >
138 <div style ={{ fontSize :13, color :"#9 fb7c0 "}} >AES -128 / AES
-256 / SHA -256 — Encrypt , Decrypt , Hash </div >
139 </div >
140 <div className =" badge"> Software 75% • Hardware 25% </div >
141 </div >
142

143 <div className =" card">

144 <div className =" controls ">
145 <select className =" select " value ={ algo} onChange ={e=>
setAlgo (e. target .value)}>
146 <option >AES -128 </ option >

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 IMPLEMENTATION OF EFFICIENT CRYPTOGRAPHIC ALGORITHM

147 <option >AES -256 </ option >

148 <option >SHA -256 </ option >
149 </select >
150

151 <div style ={{ display :'flex ',gap :8, alignItems :'center '}}>
152 <label className =" small kv">
153 <input type =" radio" checked ={ mode === ' encrypt '}
onChange ={()=> setMode ('encrypt ')} /> <span style
={{ marginLeft :6}} > Encrypt </ span >
154 </label >
155 <label className =" small kv">
156 <input type =" radio" checked ={ mode === ' decrypt '}
onChange ={()=> setMode ('decrypt ')} /> <span style
={{ marginLeft :6}} > Decrypt </ span >
157 </label >
158 </div >
159

160 <div style ={{ marginLeft :'auto '}} className =" tooltip ">
Note: SHA -256 is a hash (one -way). Decrypt disabled
.</div >
161 </div >
162

163 <div className =" row">

164 <div className =" col">
165 <div className =" small"> Plaintext (Hex) / Ciphertext (
Hex) </div >
166 <textarea className =" textarea " placeholder =" Enter hex
(no 0x). For AES plaintext must be hex; small
inputs will be PKCS #7 padded for encryption ." value
={ inputHex } onChange ={e=> setInputHex (e. target . value
)} />
167 <div style ={{ display :'flex ',gap :8, marginTop :8}} >
168 <input className =" input" style ={{ flex :1}}
placeholder =" Encryption Key (Hex)" value ={ keyHex }

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 IMPLEMENTATION OF EFFICIENT CRYPTOGRAPHIC ALGORITHM

onChange ={e=> setKeyHex (e. target . value )} />

169 <button className =" btn btn - ghost " onClick ={() =>{
170 // fill sample vector
171 if(algo ==='AES -128 '){
172 setInputHex ("00112233445566778899 aabbccddeeff ");
173 setKeyHex ("000102030405060708090 a0b0c0d0e0f ");
174 } else if(algo ==='AES -256 '){
175 setInputHex ("00112233445566778899 aabbccddeeff ");
176 setKeyHex ("000102030405060708090
a0b0c0d0e0f101112131415161718191a1b1c1d1e1f ")
;
177 } else {
178 setInputHex ("616263") ; setKeyHex ("");
179 }
180 }}> Load Example </ button >
181 </div >
182

183 <div className =" actions ">

184 <button className ="btn - primary " onClick ={ onRun }>Run
</ button >
185 <button className ="btn - ghost " onClick ={() =>{
setInputHex (""); setKeyHex (""); setResultHex ("");
setIntermediate ([]); setNotes (""); }}>Reset </
button >
186 <button className ="btn - ghost " onClick ={ onExport }>
Export </ button >
187 </div >
188

189 <div className =" small" style ={{ marginTop :8}} > Helper :
hex only (0-9 a-f). AES keys: 32 chars (128 - bit) or
64 chars (256 - bit).</div >
190

191 </div >

192

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 IMPLEMENTATION OF EFFICIENT CRYPTOGRAPHIC ALGORITHM

193 <div className =" col">

194 <div className =" small">Result </div >
195 <div className =" result ">{ resultHex || <span style ={{
color : '#7697a0 '}}>No result yet </ span >} </div >
196

197 <div className =" metrics ">

198 <div className =" metric ">Time: { timeMs ? `${ timeMs }
ms ` : —""} </div >
199 <div className =" metric ">Mode: {mode }</div >
200 <div className =" metric "> Algorithm : {algo }</div >
201 </div >
202

203 <div style ={{ marginTop :12}} >

204 <div className =" small"> Visualizer & Intermediate
States </div >
205 <div className =" visual ">
206 { intermediate . length ===0 ? <div className =" small ">
No intermediate states logged yet. After run ,
blocks are shown .</div > :
207 intermediate .map ((row , idx)=>(
208 <div key ={ idx} style ={{ padding :6, borderBottom
:'1px solid rgba (255 ,255 ,255 ,0.02) '}}>
209 <div style ={{ fontSize :13 , color : '#9 fb7c0 '}} >{
row [0]} </ div >
210 <div style ={{ fontSize :13 , marginTop :4}} >{ row
[1]} </ div >
211 </div >
212 ))
213 }
214 </div >
215 </div >
216

217 <div style ={{ marginTop :12, display :'flex ',gap :8}} >

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 IMPLEMENTATION OF EFFICIENT CRYPTOGRAPHIC ALGORITHM

218 <button className ="btn - ghost " onClick ={ onCopy }>Copy

Result </ button >
219 <button className ="btn - ghost " onClick ={() =>{
220 // compare with NIST vector for AES -128 example
221 if(algo ==='AES -128 ' && inputHex . replace (/[^0 -9a-fA
-F]/g,''). toLowerCase () === '00112233445566778899
aabbccddeeff '){
222 const expected = "69
c4e0d86a7b0430d8cdb78070b4c55a ";
223 alert (" Expected cipher (NIST):\n"+ expected +"\n\
nYour result :\n"+ resultHex );
224 } else alert ("No known vector loaded ");
225 }}> Check Test Vector </ button >
226 </div >
227

228 <div style ={{ marginTop :12, color : '#889 fb0 ', fontSize
:13}} >
229 {notes}
230 </div >
231 </div >
232 </div >
233 </div >
234

235 <div className =" card">

236 <div style ={{ display :'flex ', justifyContent :'space -between
', alignItems :'center '}}>
237 <div className =" small">About / Notes </div >
238 <div className =" small"> Visualization is illustrative ;
for exact AES round states use a round - exposing AES
engine .</div >
239 </div >
240 <div style ={{ marginTop :8, color : '#9 fb7c0 ', fontSize :14}} >
241 This demo app simulates encryption , decryption and
hashing with easy export and examples . It is meant

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 IMPLEMENTATION OF EFFICIENT CRYPTOGRAPHIC ALGORITHM

for educational demonstration and prototype testing .

242 </div >
243 </div >
244

245 <div className =" footer ">

246 © Project — Implementation of Efficient Cryptographic
Algorithm — Demo
247 </div >
248 </div >
249 );
250 }

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