School of Engineering

EEET 1026
Introduction to Computer Systems

Tutorial 7

Digital Arithmetic Operations and Circuits

Addition of unsigned binary numbers
Basic operation of an arithmetic/logic unit (ALU)
Parallel binary adder and building blocks
2’s complement system of representing signed numbers
Addition and subtraction of signed binary numbers
Operation of a parallel adder/subtractor circuits

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Preparation
 You are expected to attempt each of the exercises in this handout before the
scheduled tutorial class.
 The questions and exercises in the handout are based on the materials
covered in the lectures. You can review the materials by revisiting the lecture
notes available in this web site.
 It is important that you read the relevant sections of the textbook (Digital
Systems: Principles and Applications) and look at the examples there to
enhance your understanding of the concepts.
Important note
 Tutorial classes are meant to be interactive. That is, you are expected to
actively take part in the discussion and problem solving. Don’t expect the
tutor to simply hand out solutions. Therefore, your preparation for the class
is essential.
Exercises:
6.1, 6.2, 6.3, 6.4, 6.5, 6.6, 6.7
6.8, 6.9, 6.10, 6.13
6.14, 6.15, 6.16
6.18, 6.19, 6.20
6.26, 6.27, 6.28, 6.29, 6.30, 6.33

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6-1. Perform the following addition or subtraction operations (as indicated) in binary. Check your
results by converting the numbers to decimal and doing the calculations in decimal.

(a) 1010 + 1011 (c) 1011.1101 + 11.1

(b) 1111 + 0011 (d) 0.1011 + 0.1111

(e) 100011011 + 100011101 (k) 101010 – 100101

(f) 1010.01 + 10.111 (l) 1111.010 – 1000.001

(g) 10001111 + 01010001 (m) 10011 – 00110

(h) 11001100 + 00110111 (n) 11100010 – 01010001

(i) 110010100011 + 011101111001 (o) 100010.1001 -001111.0010

(j) 1010 – 0111 (p) 1011000110 - 1001110100

6-2. Represent each of the following signed decimal numbers in the 2’s-complement system. Use a
total of eight bits, including the sign bit.

(a) +32 (e) +127 (i) -1 (m) +84

(b) -14 (f) -127 (j) -128 (n) +3

(c) +63 (g) +89 (k) +169 (o) -3

(d) -104 (h) -55 (l) 0 (p) -190

6-3. Each of the following numbers represents a signed decimal number in the 2'scomplement
system. Determine the decimal value in each case. (Hint: Use negation to convert negative numbers
to positive.)

(a) 01101 (c) 01111011

(b) 11101 (d) 10011001

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(e) 01111111 (h) 10000001

(f) 10000000 (i) 01100011

(g) 11111111 (j) 11011001

6-4.
(a) What range of signed decimal values can be represented using 12 bits including the sign bit?

(b) How many bits are required to represent the decimal numbers from ‒32,768 to +32,767?

6-5. List, in order, all of the signed decimal numbers that can be represented in five bits using the
2's-complement system.

6-6. Represent each of the following decimal values as an 8-bit signed binary number. Then negate
each one.
(a) +73 (b) ‒12 (c) +15 (d) ‒1 (e) ‒128 (f) +127

6-7. (a) What is the range of unsigned decimal values that can be represented in 10 bits? What is
the range of signed decimal values using the same number of bits?

(b) Repeat both problems using eight bits.

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6-8. The reason why the sign-magnitude method for representing signed numbers is not used in
most computers can readily be illustrated by performing the following.

(a) Represent +12 in eight bits using the sign-magnitude form.

(b) Represent ‒12 in eight bits using the sign-magnitude form.

(c) Add the two binary numbers and note that the sum does not look anything like zero.

6-9. Perform the following operations in the 2's-complement system. Use eight bits (including the
sign bit) for each number. Check your results by converting the binary result back to decimal.

(a) Add +9 to +6. (f) Subtract +21 from ‒13.

(b) Add +14 to ‒17. (g) Subtract +47 from +47.

(c) Add +19 to ‒24. (h) Subtract ‒36 from ‒15.

(d) Add ‒48 to ‒80. (i) Add +17 to ‒17.

(e) Subtract +16 from +17. (j) Subtract ‒17 from ‒17.

6-10. Repeat Problem 6-9 for the following cases, and show that overflow occurs in each case.
(a) Add +37 to +95. (b) Subtract +37 from ‒95.

(c) Add ‒37 to ‒95. (d) Subtract ‒37 from +95

6-13. Add the following decimal numbers after converting each to its BCD code.
(a) 74 + 23 (e) 998 + 003

(b) 58 + 37 (f) 623 + 599

(c) 147 + 380 (g) 555 + 274

(d) 385 + 118 (h) 487 + 116

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6-14. Find the sum of each of the following pairs of hex numbers.
(a) 3E91 + 2F93 (e) FFF + OFF

(b) 9lB + 6F2 (f) D191 + AAAB

(c) ABC + DEF (g) 5C74 + 22BA

(d) 2FFE + 0002 (h) 39F0 + 411F

6-15. Perform the following subtractions on the pairs of hex numbers.

(a) 3E91 - 2F93 (e) F000 – EFFF

(b) 9lB - 6F2 (f) 2F00- 4000

(c) 0300 - 005A (g) 5AE5 – C01D

(d) 0200 – 0003 (h) 4321 – F165

6-16. The owner's manual for a small microcomputer states that the computer has usable memory
locations at the following hex addresses: 0200 through 03FF, and 4000 through 7FDO. What is the
total number of available memory locations?

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6-19. Write the function table (truth table) for a half adder (inputs A and B; outputs SUM and
CARRY). From the function table, design a logic circuit that will act as a half adder.

6-20. A full adder can be implemented in many different ways. Figure 6-27 shows how one may be
constructed from two half adders. Construct a function table (truth table) for this arrangement, and
verify that it operates as a FA.

Figure 6-27

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6-26. Show the logic levels at each input and output of Figure 6-11(b) when EC16 is added to 4316.

Figure 6-11(b)

6-27. For the circuit of Figure 6-14, determine the sum outputs for the following cases.

Figure 6-14

(a) A register = 0101 (+5), B register = 1110 (-2); SUB = 1, ADD = 0

(b) A register = 1100 (-4), B register = 1110 (-2); SUB = 0, ADD = 1

(c) Repeat (b) with ADD = SUB = 0.

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6-28. For the circuit of Figure 6-14, determine the sum outputs for the following cases.
(a) A register = 1101 (-3), B register = 0011 (+3); SUB = 1, ADD = 0

(b) A register = 1100 (-4), B register = 0010 (+2); SUB = 0, ADD = 1

(c) A register = 1011 (-5), B register = 0100 (+4); SUB = 1, ADD = 0

6-29. For each of the calculations of Problem 6-27, determine if overflow has occurred.

6-30. For each of the calculations of Problem 6-28, determine if overflow has occurred.

6-33. Determine the F, CN+ 4 , and OVR outputs for each of the following sets of inputs applied to a
74LS382 IC.

(a) [S] = 011, [A] = 0110, [B] = 0011, CN = 0

(b) [S] = 001, [A] = 0110, [B] = 0011, CN = 1

(c) [S] = 010, [A] = 0110, [B] = 0011, CN = 1