Department of Electrical Engineering
Riphah College of Science & Technology
Riphah International University, Lahore
Program: [Link]. Electrical Engineering Semester: VI
Subject: EEL-316 Power Electronics Date: ……………….
Open Ended II: Three Phase Inverter
Objective:
Develop the three-phase two-level inverter power circuit and its isolated gate-control architecture.
Generate six complementary SPWM gate pulses from three 120°-shifted sinusoidal references.
Name: Muhammad Maalik Ashtar SAP: 57465
No. Lab Evaluation Scheme (CLO-5) Obtained Marks
1 Ability to Conduct Experiment (0-5)
2 Understanding & Interpretation (0-5)
Total
No. Lab Report Scheme (CLO-7) Obtained Marks
1 Organization / Structure (0-5)
2 Calculations & Data Presentation (0-5)
Total
Remarks (if any): ………………………………….
Name & Signature of faculty: ………………………………
Department of Electrical Engineering
Riphah College of Science & Technology
Riphah International University, Lahore
Introduction:
This experiment develops and evaluates a three-phase two-level voltage source inverter using six IGBTs and
sinusoidal pulse-width modulation. A 400 V DC link is converted into a balanced 50 Hz three-phase AC output
by comparing three sinusoidal reference signals displaced by 120° with a 5 kHz triangular carrier. The
MATLAB/Simulink model includes the DC source, universal bridge, PWM generator, three-phase measurement
block, star-connected R-L load and scopes. The experiment verifies the expected fundamental line-to-line
voltage, phase current, switching behavior and harmonic spectrum. Separate MATLAB circuit, DC-input, gate-
pulse and three-phase output figures are included so that the power circuit and the simulation results are
clearly distinguished.
Learning Outcomes
Explain the operating principle of a three-phase voltage source inverter and identify the six switching
devices.
Generate three sinusoidal references displaced by 120° and implement two-level SPWM.
Relate DC-link voltage and modulation index to the fundamental line-to-line output voltage.
Measure three-phase output voltages, load currents, rms values and harmonic content in
MATLAB/Simulink.
Explain the importance of complementary gating, dead time, device ratings and safe DC-link handling.
A three-phase AC load must be supplied from a DC source while maintaining a controlled 50 Hz output with
balanced phase voltages. Design a two-level inverter using six semiconductor switches, choose a suitable
modulation strategy, determine switching and load parameters, generate non-overlapping complementary gate
signals, and verify the electrical performance in MATLAB/Simulink. The design must justify switch ratings,
modulation index, carrier frequency, load selection, measurement method and safety requirements.
Required Apparatus
No. Equipment / component Typical rating / purpose
400 V nominal in simulation; use a safe scaled-down source for hardware
1 DC source / DC link
verification
≥600 V, ≥10 A class for the stated 400 V simulation bus; select exact device
2 IGBTs with diodes (6)
from datasheet
3 Gate-driver channels Six isolated drivers, typically 15 V gate drive, with dead-time capability
4 Controller / PWM source DSP, STM32, dSPACE, or MATLAB/Simulink PWM Generator (2-Level)
5 DC-link capacitor Illustrative 680 µF, ≥450 V; 500 V preferred for practical margin
100 Ω + 50 mH per phase, star connected; appropriately power-rated for
6 Three-phase load
hardware
7 Protection DC fuse/current limiting, pre-charge, emergency stop and discharge resistor
8 Oscilloscope / probes Isolated or differential voltage probes and current probes
9 Simulation software MATLAB/Simulink with Simscape Electrical / Specialized Power Systems
Department of Electrical Engineering
Riphah College of Science & Technology
Riphah International University, Lahore
Explanation
Three-phase voltage source inverter
A two-level three-phase VSI contains three bridge legs. Each leg has an upper and a lower controlled switch
with an anti-parallel diode. The midpoint of each leg forms one output phase. The upper and lower switch of
the same leg must never be ON simultaneously because that would short-circuit the DC link. The three legs
generate phase voltages that are displaced by 120 electrical degrees.
Sinusoidal pulse-width modulation (SPWM)
Three sinusoidal reference signals at 50 Hz are compared with one high-frequency triangular carrier. When a
phase reference is greater than the carrier, the corresponding upper switch is commanded ON and the lower
switch is commanded OFF. The other two phase references are shifted by −120° and +120°. In the linear
SPWM region, the fundamental output voltage is approximately proportional to the modulation index ma.
mₐ = Vref,pk / Vcarrier,pk and m_f = f_c / f_o
Fundamental output relation
VLL,1,rms = (√3 / 2√2) · mₐ · Vdc ≈ 0.6124 · mₐ · Vdc
For Vdc = 400 V and ma = 0.90, the expected fundamental line-to-line rms voltage is approximately 220.5 V.
The corresponding fundamental phase rms voltage is approximately 127.3 V.
Electrical circuit of the three-phase SPWM inverter
Calculation
6.1 Carrier and modulation selection
f_o = 50 Hz, f_c = 5 kHz, m_f = f_c / f_o = 5000 / 50 = 100
Department of Electrical Engineering
Riphah College of Science & Technology
Riphah International University, Lahore
A carrier ratio of 100 provides many switching pulses per fundamental cycle and places the dominant PWM
components around the 5 kHz switching band and its sidebands. A modulation index ma = 0.90 is selected to
remain within the linear SPWM range while providing a useful output amplitude.
Fundamental output voltage
VLL1,rms = 0.6124 × 0.90 × 400 = 220.5 V
Vphase,1,rms = 220.5 / √3 = 127.3 V
R-L load current
|Z| = √[R² + (2πfL)²] = √[100² + (2π×50×0.05)²] = 101.23 Ω
Iphase,1,rms = 127.3 / 101.23 = 1.26 A
The load displacement angle is approximately 8.93°, giving a fundamental power factor of about 0.988. The
inductance smooths the current and strongly attenuates the high-frequency PWM ripple compared with a
purely resistive load.
Semiconductor rating selection
Each IGBT must block approximately the full DC-link voltage when OFF. For a 400 V bus, a 600 V or higher
device class provides practical voltage margin; a higher rating may be chosen if DC overshoot or long wiring is
expected. The simulated fundamental phase current is only about 1.26 A, but a ≥10 A device class is
recommended for laboratory margin, switching transients and future load variations. The final heat sink and
snubber design must use the exact manufacturer switching-loss and safe-operating-area data.
Dead time
For real hardware, introduce a short dead time between the turn-off of one device and the turn-on of its
complementary device. A value around 1–3 µs is typical for educational IGBT hardware, but the exact value
must be determined from the driver and device turn-off characteristics. Excessive dead time increases low-
order output distortion.
Control Strategy
1. Generate three 50 Hz sinusoidal reference signals with phase angles 0°, −120° and +120°.
2. Generate a 5 kHz triangular carrier and compare each sinusoidal reference with the carrier.
3. Create the upper-switch commands S1, S3 and S5 from the three comparator outputs.
4. Generate complementary commands for S4, S6 and S2 respectively, with hardware dead time before
practical implementation.
5. Apply all six pulses to the Universal Bridge configured for IGBT/diode devices.
6. Measure DC-link voltage, three line-to-line voltages, three phase currents and the FFT spectrum.
7. If ma is changed, keep ma ≤ 1 for linear SPWM unless overmodulation is intentionally being studied.
Circuit Setup
Place a DC Voltage Source and set Vdc = 400 V.
Add a Universal Bridge and configure the power electronic devices as IGBT/Diodes with three bridge arms.
Add a PWM Generator (2-Level) or equivalent SPWM subsystem. Set fundamental frequency to 50 Hz,
carrier frequency to 5 kHz and modulation index to 0.90.
Connect the bridge output to a Three-Phase V-I Measurement block and a star-connected Three-Phase
Series RLC Load set to R = 100 Ω and L = 50 mH per phase.
Department of Electrical Engineering
Riphah College of Science & Technology
Riphah International University, Lahore
Insert powergui and use a discrete simulation step sufficiently smaller than the 200 µs switching period; a
step around 1–2 µs gives clean switching capture.
Connect Scope blocks for Vdc, gate pulses, line-to-line voltages and phase currents. Use the FFT Analysis
tool in powergui or export data to MATLAB for spectral analysis.
Run the simulation for at least 0.10 s so that startup transients settle and several steady-state 50 Hz cycles
are available.
Simulation Procedure
1. Build the MATLAB/Simulink model exactly as shown in Figure 1 and verify the IGBT bridge orientation.
2. Enter Vdc = 400 V, fo = 50 Hz, fc = 5 kHz, ma = 0.90, R = 100 Ω and L = 50 mH.
3. Run the PWM section first and verify the three upper-switch pulses and complementary lower-switch logic.
4. Run the complete inverter model and record the DC-link input voltage separately.
5. Record Vab, Vbc and Vca; confirm balanced three-phase switching and correct phase sequence.
6. Record Ia, Ib and Ic after the initial transient and verify approximately equal amplitudes with 120°
displacement.
7. Repeat the simulation for ma = 0.60, 0.80 and 1.00 and record the fundamental line-to-line rms voltage.
8. Perform FFT analysis of Vab and Ia. Note the 50 Hz fundamental and the switching group around the 5 kHz
carrier frequency.
9. Compare the measured values with the design equations and comment on differences caused by PWM
harmonics and finite simulation step.
MATLAB/Simulink Input and Gate-Signal Results
MATLAB Scope input: independent 400 V DC-link voltage supplied to the inverter.
Department of Electrical Engineering
Riphah College of Science & Technology
Riphah International University, Lahore
MATLAB Scope gate pulses for the three upper IGBTs. The three pulse trains are produced from 120°-shifted sinusoidal references and
one 5 kHz carrier.
The input and switching results are shown separately from the inverter output. The DC link remains constant at
400 V in the ideal source model. The upper-switch SPWM pulses differ because each comparator uses a
different sinusoidal reference phase. In practical hardware, the lower device in each leg receives a
complementary pulse with a short dead-time interval to prevent shoot-through.
MATLAB/Simulink Three-Phase Output Results
Department of Electrical Engineering
Riphah College of Science & Technology
Riphah International University, Lahore
Three-phase R-L load currents Ia, Ib and Ic. The inductance smooths the 5 kHz switching ripple and produces sinusoidal currents.
Observation Tables
Completed MATLAB/Simulink results
Expected VLL,1 Measured VLL,1
ma Load Iphase,1 rms (A) Current THD
rms (V) rms (V)
0.60 R-L 147.0 146.0 0.83 1.65%
0.80 R-L 196.0 195.1 1.11 1.93%
0.90 R-L 220.5 220.6 1.26 2.02%
1.00 R-L 244.9 244.2 1.39 2.17%
Load comparison at ma = 0.90
Load VLL,1 rms (V) Iphase,1 rms (A) Current THD Observation
Current follows PWM
R = 100 Ω / phase 220.6 1.27 ≈29.9% voltage and contains
strong switching ripple
Current is smooth and
R = 100 Ω, L = 50 mH /
220.6 1.26 ≈2.0% nearly sinusoidal; slight
phase
lag is present
Representative switching-state interpretation
Typical command state Pole condition Meaning
One active vector; line voltages take ±Vdc/0
S1,S6,S5 ON A+, B−, C+
levels
Another active vector; phase-neutral
S1,S6,S2 ON A+, B−, C−
average changes
S1,S3,S5 ON All upper switches ON Zero vector; all pole voltages equal
Department of Electrical Engineering
Riphah College of Science & Technology
Riphah International University, Lahore
Typical command state Pole condition Meaning
S4,S6,S2 ON All lower switches ON Zero vector; all pole voltages equal
Conclusion
The three-phase SPWM inverter successfully demonstrates conversion of a 400 V DC link into a balanced 50
Hz three-phase AC output using a six-IGBT two-level bridge. The MATLAB/Simulink circuit produced the
expected 120° phase relationship, and the measured fundamental line-to-line voltage at ma = 0.90 was
approximately 220.6 V, closely matching the theoretical 220.5 V value. The R-L load smoothed the high-
frequency PWM voltage into nearly sinusoidal phase currents of about 1.26 A rms. FFT analysis showed the
50 Hz fundamental together with switching-frequency components concentrated around the 5 kHz carrier
region. The experiment confirms that modulation index, switching frequency, load inductance, complementary
gating and dead time are the key parameters governing output quality and safe inverter operation.