EEE 313 — Solved Exercise Problems

Neamen, Semiconductor Physics and Devices, 4th Edition

Chapter 4 · Chapter 9 · Chapter 10

Ei PDF e ki ache:
34 ta selected problem — boi er exercise theke, shudhu exam-relevant gula
Proti ta step-by-step, intermediate value soho
Proti ta er sheshe physical interpretation (exam e ei line gula marks dey)
Star rating: ★★★ = ager paper e eshechilo / ashar chance shobcheye beshi
Constants (Neamen, Si @ 300 K):
ni = 1.5×1010 · Nc = 2.8×1019 · Nv = 1.04×1019 · kT/e = 0.0259 V
εs = 1.035×10−12 F/cm · εox = 3.45×10−13 F/cm · Eg = 1.12 eV · A* = 120 A/K2cm2
χ(Si) = 4.01 V · φm: Al 4.28, W 4.55, Au 5.1, Pt 5.65
PART 1 — CHAPTER 4: The Semiconductor in Equilibrium
Problem 4.3 — Maximum operating temperature ★★★
Given: Si device e ni ke (a) 5×1011 cm−3, (b) 5×1012 cm−3 er beshi hote deya jabe na. Eg = 1.12 eV. Find:
maximum temperature.

Step 1 — Temperature-dependent ni likho. Nc ar Nv doitai T3/2 e vary kore, tai product ta T3:

ni2(T) = Nc0Nv0 (T/300)3 exp(−Eg/kT)

Nc0Nv0 = (2.8×1019)(1.04×1019) = 2.912×1038

Step 2 — ln nao, ekta transcendental equation pabe:

3 ln(T/300) − 12993/T = ln[ ni2 / 2.912×1038 ]

ekhane Eg/k = 1.12 / 8.62×10−5 = 12993 K (mukhosto rakho)

Step 3 — Trial & error. (a) ni = 5×1011 → RHS = ln(2.5×1023/2.912×1038) = −34.69

Trial T 3 ln(T/300) −12993/T LHS Verdict

350 K 0.4626 −37.12 −36.66 onek chhoto → T barao

370 K 0.6293 −35.12 −34.49 ektu boro → komao

368 K 0.6130 −35.31 −34.69 ✓ mile gelo

(a) Tmax = 368 K (≈ 95°C) | (b) Tmax = 418 K (≈ 145°C)

Interpretation: Ei temperature er upore ni doping ke dominate kore — device extrinsic character hariye
intrinsic hoye jay, junction kaj kora bondho kore. ni limit 10× barano hole T matro 50 K bare — karon ni er T-
dependence exponential, tai ekta chhoto temperature window-i onek boro ni change ane. Ei jonnoi high-
temperature electronics e wide-bandgap material (SiC Eg=3.2, GaN 3.4 eV) lage — boro Eg mane exp(−Eg/kT)
khub chhoto, ni chhoto thake.
 Problem 4.4 — Nc0Nv0 ar Eg ber koro (reverse problem) ★★

Given: ni = 1.40×102 cm−3 @ 200 K, ni = 7.70×1010 cm−3 @ 400 K. Find: Nc0Nv0 product ar Eg.

Step 1 — Duita equation likho, tarpor RATIO nao (ei trick ta unknown Nc0Nv0 ke bad diye dey):

ni2(400) / ni2(200) = (400/200)3 · exp[ (Eg/k)(1/200 − 1/400) ]

(7.70×1010)2 / (1.40×102)2 = 5.929×1021 / 1.96×104 = 3.025×1017

Step 2 — Eg solve koro:

3.025×1017 / 8 = exp[ Eg / (8.62×10−5 × 400) ]

ln(3.781×1016) = 38.17 = Eg × 29.00 → Eg = 1.316 eV

Step 3 — Ekta equation e phire giye Nc0Nv0 ber koro (T = 200 K use kori):

1.96×104 = A × (200/300)3 × exp(−1.316/(8.62×10−5×200))

1.96×104 = A × 0.2963 × 6.99×10−34

Eg = 1.316 eV | Nc0Nv0 = 9.46×1037 cm−6

Kaje lagbe: Ei "duita measurement theke ratio nao" technique ta general — ekta unknown ke eliminate kore.
Eg = 1.316 eV Si (1.12) er cheye boro, GaAs (1.42) er kachakachi — mane eta ekta wide-gap material.

Problem 4.17 — Basic n-type chain ★★

Given: Si @ 300 K, arsenic doped, n0 = 7×1015 cm−3.

(a) Ec − EF = kT ln(Nc/n0) = 0.0259 × ln(2.8×1019/7×1015) = 0.0259 × ln(4000) = 0.0259 × 8.294

(b) EF − Ev = Eg − (Ec−EF) = 1.12 − 0.2148
(c) p0 = ni2/n0 = (1.5×1010)2/7×1015 = 2.25×1020/7×1015
(e) EF − EFi = kT ln(n0/ni) = 0.0259 × ln(4.667×105) = 0.0259 × 13.05

(a) 0.2148 eV | (b) 0.9052 eV | (c) p0 = 3.21×104 cm−3 | (d) hole minority | (e) 0.338 eV

Sanity check: n-type e EF obosshoi EFi er upore thakbe (0.338 eV upore ✓), ar Ec er kachakachi (0.215 eV
niche ✓). Duita answer 0.2148 + 0.9052 = 1.12 = Eg ✓ — ei check ta proti bar koro.
 Problem 4.34 — Compensated semiconductor, 5 cases ★★★
Master formula:

n-type (Nd>Na): n0 = (Nd−Na)/2 + √[ ((Nd−Na)/2)2 + ni2 ] , p0 = ni2/n0

p-type (Na>Nd): p0 = (Na−Nd)/2 + √[ ((Na−Nd)/2)2 + ni2 ] , n0 = ni2/p0

Case T ni(T) Type n0 (cm−3) p0 (cm−3)

(a) Nd=1015, Na=4×1015 300 K 1.5×1010 p 7.5×104 3.0×1015

(b) Nd=3×1016, Na=0 300 K 1.5×1010 n 3.0×1016 7.5×103

(c) Nd=Na=2×1015 300 K 1.5×1010 intrinsic 1.5×1010 1.5×1010

(d) Nd=0, Na=4×1015 375 K 7.14×1011 p 1.28×108 4.0×1015

(e) Nd=1014, Na=0 450 K 1.68×1013 n 1.03×1014 2.76×1012

Case (e) er detail (ekhane-i asol shikkha):

ni(450) = √[2.912×1038 × (450/300)3 × exp(−12993/450)] = 1.68×1013

Nd/2 = 5×1013
n0 = 5×1013 + √[(5×1013)2 + (1.68×1013)2] = 5×1013 + 5.28×1013 = 1.03×1014

Ei ta-i exam er trap: Case (a)–(d) te ni << |Nd−Na|, tai shortcut n0 ≈ Nd−Na khate. Kintu case (e) te ni =
1.68×1013 ar Nd = 1014 — eki order! Shortcut nile 1014 pete, asol uttor 1.03×1014 — 3% bhul. Ar
temperature aro barle bhul aro barbe. Rule: high T ba low doping hole full formula use koro. Case (c): fully
compensated → material intrinsic er moto behave kore.

Problem 4.37 — Occupation probability ★★★

Given: n-Si @ 300 K. EF conduction band er 245 meV niche, ar donor level er 200 meV niche. Mane Ec−EF =
0.245 eV, Ed−EF = 0.200 eV. (Check: Ec−Ed = 45 meV ✓ Si donor er standard value)

(a) Donor level e electron thakar probability — degeneracy factor g = 2, tai formula te 1/2:
nd/Nd = 1 / [ 1 + (1/2)·exp((Ed−EF)/kT) ]
= 1 / [ 1 + 0.5 × exp(0.200/0.0259) ]
= 1 / [ 1 + 0.5 × exp(7.722) ] = 1 / [1 + 0.5 × 2256] = 1/1129

(b) Conduction band e kT upore ekta state e electron thakar probability — ei ta plain Fermi-Dirac, kono
degeneracy factor NA:

E − EF = 0.245 + 0.0259 = 0.2709 eV

fF(E) = 1/[1 + exp(0.2709/0.0259)] ≈ exp(−10.46)

(a) nd/Nd = 8.85×10−4 | (b) fF = 2.87×10−5

Interpretation: Matro 0.0885% donor un-ionized — mane 99.91% ionized, tai "complete ionization"
assumption room temperature e purro justified. Karon kT = 25.9 meV ar donor binding energy 45 meV — eki
order, tai thermal energy prai shob donor ke ionize kore dey.
Kintu T = 50 K e: kT = 4.3 meV, exponent 45/4.3 = 10.5 hoye jay → nd/Nd prai 1 → freeze-out, carrier prai nei.

Duita formula guliye felo na: Donor state → 1/2·exp((Ed−EF)/kT) | Acceptor state → 1/4·exp((EF−Ea)/kT) |
Normal band state → kono factor nei.
 Problem 4.45 — ni ber koro (reverse) ★★

Given: Nd = 2×1014, Na = 1.2×1014, n0 = 1.1×1014 cm−3. Find: ni ar p0.

(Nd−Na)/2 = (2×1014 − 1.2×1014)/2 = 4×1013

1.1×1014 = 4×1013 + √[(4×1013)2 + ni2]

7×1013 = √[1.6×1027 + ni2]
4.9×1027 = 1.6×1027 + ni2 → ni2 = 3.3×1027

ni = 5.74×1013 cm−3 | p0 = ni2/n0 = 3.0×1013 cm−3

Interpretation: ni = 5.74×1013 — Si (1.5×1010) er cheye 4000× boro, Ge (2.4×1013) er kachakachi. Mane eta
narrow-bandgap material ba high temperature. Ar dekho p0 (3×1013) n0 (1.1×1014) er cheye matro 3.7×
chhoto — minority carrier negligible na, material prai intrinsic er dike.

Problem 4.47 — Type identify + Nd ber koro ★★

Given: Si @ 300 K, Na = 7×1015, p0 = 2×104 cm−3.

(a) p0 = 2×104 << ni = 1.5×1010 — hole ekdom kom, tai hole minority. → material n-type.
(b) n0 = ni2/p0 = 2.25×1020/2×104
(c) Charge neutrality: n0 − p0 = Nd − Na

Nd = n0 − p0 + Na = 1.125×1016 − 2×104 + 7×1015

(a) n-type | (b) n0 = 1.125×1016, p0 = 2×104 | (c) Nd = 1.83×1016 cm−3

Logic ta mone rakho: Na deya thakleo material n-type hote pare — jodi Nd boro hoy. Type ta doping compare
kore na, carrier concentration dekhe bolo. p0 < ni mane n-type, p0 > ni mane p-type.
 Problem 4.50 — Max operating temp (5% rule) ★★★ — Q3(a) er EXACT type
Given: Si, Nd = 1015 cm−3. Intrinsic carrier gulo total electron concentration er 5% er beshi contribute korte
parbe na.

Step 1 — Criterion ke equation e convert koro. n0 = Nd + (intrinsic contribution). Condition: intrinsic part ≤
0.05·n0, mane Nd ≥ 0.95·n0:

n0 = Nd/0.95 = 1015/0.95 = 1.0526×1015 cm−3

Step 2 — p0 ber koro charge neutrality theke, tarpor ni:

p0 = n0 − Nd = 1.0526×1015 − 1015 = 5.26×1013

ni2 = n0·p0 = (1.0526×1015)(5.26×1013) = 5.54×1028
ni = 2.354×1014 cm−3

Step 3 — Ei ni kon T te hoy? Trial & error:

(T/300)3 exp(−12993/T) = ni2/2.912×1038 = 1.902×10−10

Trial T LHS Verdict

500 K 2.75×10−11 chhoto → T barao

550 K 2.86×10−10 boro → komao

538 K 1.90×10−10 ✓

(a) Tmax = 538 K (≈ 265°C)

(b) Ec − EF er change:

@300 K: Ec−EF = 0.0259 ln(2.8×1019/1015) = 0.0259 × 10.24 = 0.265 eV

19 1.5 19
@538 K: Nc(538) = 2.8×10 (538/300) = 6.73×10 , kT = 0.0464 eV
19 15
Ec−EF = 0.0464 × ln(6.73×10 /1.0526×10 ) = 0.0464 × 11.07 = 0.514 eV
Change = 0.514 − 0.265 = +0.249 eV
(c) Eg/2 = 0.56 eV. 300 K te EF midgap theke 0.56−0.265 = 0.295 eV upore. 538 K te 0.56−0.514 = 0.046
eV upore.

(c) EF onek beshi kache chole eshechhe intrinsic level er — 0.295 eV theke 0.046 eV

Interpretation: Temperature barle ni bare, ar EF midgap er dike shore — material er extrinsic character durbol
hoye jay. 538 K er upore doping ar carrier concentration control kore na, thermal generation kore.
 Problem 4.54 — Design: Nd add koro given EF er jonno ★★

Given: Si @ 300 K e already Na = 5×1015. Donor add kore n-type compensated banate hobe, jate EF
conduction band er 0.215 eV niche thake. Find: Nd.

Step 1 — EF position theke n0 ber koro (ulta direction):

n0 = Nc exp[−(Ec−EF)/kT] = 2.8×1019 × exp(−0.215/0.0259)

= 2.8×1019 × exp(−8.301) = 2.8×1019 × 2.478×10−4 = 6.94×1015
Step 2 — n0 >> ni, tai n0 ≈ Nd − Na:

Nd = n0 + Na = 6.94×1015 + 5×1015

Nd = 1.19×1016 cm−3

Kaje lagbe: Compensated semiconductor diye specific Fermi level "design" kora jay — ei principle IC te
threshold voltage adjust korte use hoy.

Problem 4.61 — Minimum bandgap design ★★★

Given: Notun p-type material, Na = 5×1015, Nd = 0. Nc = 1.2×1019, Nv = 1.8×1019 @ 300 K, ar T2 e vary
kore (Si er moto T3/2 na!). Requirement: 350 K e p0 ≤ 5.08×1015. Find: minimum Eg.

Step 1 — p0 limit theke ni ber koro (ulta kore):

p0 = Na/2 + √[(Na/2)2 + ni2]

5.08×1015 = 2.5×1015 + √[(2.5×1015)2 + ni2]
2.58×1015 = √[6.25×1030 + ni2]
6.6564×1030 = 6.25×1030 + ni2 → ni2 = 4.064×1029, ni = 6.375×1014

Step 2 — NcNv at 350 K. Duitai T2 e vary kore, tai product T4 e:

NcNv(350) = (1.2×1019)(1.8×1019) × (350/300)4 = 2.16×1038 × 1.852 = 4.00×1038

Step 3 — Eg solve koro:

ni2 = NcNv exp(−Eg/kT), kT(350) = 8.62×10−5×350 = 0.03017 eV

4.064×1029 = 4.00×1038 exp(−Eg/0.03017)
exp(−Eg/0.03017) = 1.016×10−9
Eg = 0.03017 × 20.71

Eg,min = 0.625 eV

Duita trap ekhane: (1) Nc, Nv T2 e vary korche, T3/2 e na — tai product T4, T3 na. Question ta bhalo kore poro.
(2) "minimum" bandgap — karon choto Eg mane boro ni. Eg ei value er niche gele ni bere jabe ar p0 limit
chariye jabe.

Interpretation: 0.625 eV Ge (0.66 eV) er kachakachi — mane ei spec ekta narrow-gap material diyeo meet
kora jay, kintu Ge er cheye kom gele hobe na.
PART 2 — CHAPTER 9: Metal–Semiconductor & Heterojunctions
Problem 9.3 — Schottky master chain (Au on n-Si) ★★★
Given: Au (φm = 5.1 V) on n-Si, Nd = 1016 cm−3, T = 300 K, ideal junction.

(a) φB0 = φm − χ = 5.1 − 4.01 = 1.09 V

(b) φn = (kT/e) ln(Nc/Nd) = 0.0259 × ln(2.8×1019/1016) = 0.0259 × 7.937 = 0.2056 V

Vbi = φB0 − φn = 1.09 − 0.2056 = 0.8844 V

(c) xn = √[ 2εs(Vbi+VR) / (eNd) ] , Emax = 2(Vbi+VR)/xn

Bias Vbi+VR xn (cm) Emax (V/cm)

VR = 0 0.884 V 3.38×10−5 5.23×104

VR = 1 V 1.884 V 4.94×10−5 7.63×104

VR = 5 V 5.884 V 8.73×10−5 1.35×105

VR = 1 V er detail:

xn = √[2(1.035×10−12)(1.884)/((1.6×10−19)(1016))]
= √[3.90×10−12/1.6×10−3] = √(2.438×10−9) = 4.94×10−5 cm
Emax = 2(1.884)/4.94×10−5 = 7.63×104 V/cm

Tinta bhul ekhane hoy: (1) φB0 e χ (electron affinity, 4.01) boshao, φs na. (2) Schottky te depletion shudhu
semiconductor side e — metal e x = 0, pn junction er moto duipashe bhag korba na. (3) VR barleo φB0 change
hoy na (barrier lowering chhara), tai JsT prai constant — ei jonnoi reverse current saturate kore.
 Problem 9.7 — 1/C′2 vs VR graph theke extraction ★★★

Given: n-GaAs Schottky diode, 1/C′2 vs VR plot deya ache (C′ = capacitance per cm2). Find: Vbi, Nd, φn, φB0.
(Nichey graph reading gulo example value — tomar paper er graph theke actual value nao, method ta eki
thakbe.)

Step 1 — Master equation:

C′j = εs/xn ⇒ 1/C′2 = 2(Vbi + VR) / (e εs Nd)

Ei ta ekta straight line: y = m·VR + c

slope m = 2/(e εs Nd)
x-intercept (jekhane 1/C′2 = 0): VR = −Vbi

Step 2 — Graph theke pora (example readings): line ta VR axis ke −0.80 V te cut kore, ar VR = 2 V te 1/C′2
= 3×1015 (F/cm2)−2.

Vbi = 0.80 V (x-intercept er magnitude)

slope = (3×1015 − 0) / (2 − (−0.80)) = 3×1015/2.80 = 1.071×1015

Nd = 2/(e εs × slope)
εs(GaAs) = 13.1 × 8.85×10−14 = 1.159×10−12 F/cm
Nd = 2/[(1.6×10−19)(1.159×10−12)(1.071×1015)] = 1.01×1016 cm−3

Step 3 — φn ar φB0: (GaAs: Nc = 4.7×1017)

φn = 0.0259 ln(4.7×1017/1.01×1016) = 0.0259 × 3.840 = 0.0995 V

φB0 = Vbi + φn = 0.80 + 0.0995 = 0.90 V

Follow-up question guaranteed: "Theoretical φB0 = φm − χ er shathe compare koro. Alada keno?"
Answer: Interface states. Semiconductor surface e allowed energy states thake jara Fermi level ke "pin" kore
dey. Duita limit:
• Dit → ∞ : φBn = (Eg − eφ0)/e — metal er kono bhumika-i nei (complete Fermi pinning)
• Dit → 0 : φBn = φm − χ (ideal)
Karon Dit predict kora jay na, barrier height experimentally-i determine korte hoy — ei ta-i ei question er
point.
 Problem 9.8 — Schottky barrier lowering (image force) ★★
Given: W–n-Si, Nd = 5×1015, Figure 9.5 theke experimental φBn ≈ 0.67 V.

φn = 0.0259 ln(2.8×1019/5×1015) = 0.0259 × 8.631 = 0.2235 V

Vbi = 0.67 − 0.2235 = 0.4465 V

VR xn (cm) Emax (V/cm) Δφ (V) xm (Å)

1V 6.12×10−5 4.73×104 0.0241 25.5

5V 1.19×10−4 9.18×104 0.0336 18.3

Barrier lowering formula ar VR = 1 V er calculation:

Δφ = √[ e·Emax / (4πεs) ]
= √[ (1.6×10−19)(4.73×104) / (4π × 1.035×10−12) ]
= √[ 7.57×10−15 / 1.301×10−11 ] = √(5.82×10−4) = 0.0241 V

xm = √[ e / (16πεsEmax) ]
= √[ 1.6×10−19 / (5.203×10−11 × 4.73×104) ] = 2.55×10−7 cm = 25.5 Å

Interpretation: VR barle Emax bare → Δφ bare (barrier aro kome) ar xm kome (peak junction er aro kache shore
ashe). Effective barrier φBn = φB0 − Δφ, ar JsT ∝ exp(+eΔφ/kT). Ei jonnoi Schottky diode er reverse current
puropuri saturate kore na — dhire dhire bare. Δφ matro 24–34 mV, kintu kT = 25.9 mV — eki order, tai current
e effect ta noteworthy (e1 ≈ 2.7×).

Problem 9.14 — Thermionic emission current ★★★

Given: Pt–n-Si @ 300 K, Nd = 5×1015, φBn = 0.89 V, A* = 120 A/K2cm2. Barrier lowering neglect.

(a) φn = 0.0259 ln(2.8×1019/5×1015) = 0.2235 V

(b) Vbi = 0.89 − 0.2235 = 0.6665 V

(c) JsT = A*T2 exp(−eφBn/kT)

= 120 × (300)2 × exp(−0.89/0.0259)
= 1.08×107 × exp(−34.36)
= 1.08×107 × 1.192×10−15 = 1.29×10−8 A/cm2

(d) J = JsT[exp(eVa/kT) − 1] = 5 A/cm2

Va = (kT/e) ln(J/JsT + 1) = 0.0259 × ln(5/1.29×10−8)
= 0.0259 × ln(3.88×108) = 0.0259 × 19.78 = 0.512 V

Interpretation: φBn = 0.89 V ta khub boro (Pt er work function 5.65 V, tai). Ei jonno JsT chhoto (1.29×10−8) ar
turn-on voltage prai 0.51 V — typical Schottky (0.3 V) er cheye beshi, pn junction (0.7 V) er kachakachi. Rule:
boro barrier = chhoto Js = boro turn-on voltage.
 Problem 9.20 — Schottky vs pn junction ★★★
Given: Js(pn) = 10−11 A/cm2, Js(Schottky) = 6×10−8 A/cm2. A(Schottky) = 10−4 cm2. Duita diode-eo current
0.80 mA. Forward voltage er difference 0.285 V. Find: (a) proti diode er voltage, (b) A(pn).

(a) Schottky: J = I/A = 0.8×10−3/10−4 = 8 A/cm2

Va(Schottky) = 0.0259 ln(8/6×10−8) = 0.0259 × ln(1.333×108)
= 0.0259 × 18.71 = 0.485 V
Va(pn) = 0.485 + 0.285 = 0.770 V

(b) J(pn) = Js[exp(Va/kT) − 1] = 10−11 × exp(0.770/0.0259)

= 10−11 × exp(29.71) = 10−11 × 8.01×1012 = 80.1 A/cm2
A(pn) = I/J = 0.8×10−3/80.1 = 9.98×10−6 cm2

Duita boro conclusion:

(1) Turn-on difference: Js 6000× alada howay same current pete pn junction e 0.285 V beshi lage. Formula: ΔV
= (kT/e) ln(Js,Schottky/Js,pn) = 0.0259 × ln(6000) = 0.225 V (area difference milale 0.285 V hoy).
(2) Area: pn junction er area Schottky er cheye 10× chhoto holeo same current bohon kore — karon tar
current density onek beshi. Same current er jonno pn junction chhoto banano jay.

Problem 9.25 & 9.27 — Specific contact resistance ★★★

9.25 Given: Rc = 10−4 Ω-cm2. Find: junction resistance for A = 10−3, 10−4, 10−5 cm2.

R = Rc/A
A = 10−3 cm2 → R = 0.1 Ω
−4 2
A = 10 cm → R = 1.0 Ω
A = 10−5 cm2 → R = 10 Ω

Ei ta-i scaling er boro problem: device chhoto hole contact area chhoto hoy, ar contact resistance barte thake.
Modern nanoscale transistor e contact resistance total resistance er ekta boro ongsho — ei jonnoi Rc komano
ekta major research area.

9.27 Given: Ohmic contact e (a) Rc = 5×10−5, (b) 5×10−6 Ω-cm2 paite koto φBn lagbe?

Low/moderate doping (thermionic emission dominant) er formula ulta koro:

Rc = (kT/e) · exp(+eφBn/kT) / (A*T2)

exp(φBn/kT) = Rc · A*T2 / (kT/e) = Rc × 1.08×107 / 0.0259

(a) = 5×10−5 × 4.17×108 = 2.085×104

φBn = 0.0259 × ln(2.085×104) = 0.0259 × 9.947 = 0.258 V

(b) = 5×10−6 × 4.17×108 = 2.085×103

φBn = 0.0259 × 7.645 = 0.198 V

Design conclusion (ei paragraph likhle full marks): Bhalo ohmic contact er jonno φBn ≈ 0.2 V lagbe — kintu
practically ei ta pawa jay na, karon Fermi level pinning er jonno φBn metal er upor prai nirbhor kore na (Si te
ekmatro control knob holo doping. Heavy doping (Nd > 1019) korle depletion width ≈
typically 0.6–0.8 V). Tai
kichu nm hoye jay ar tunneling dominate kore, jekhane Rc ∝ exp(φBn/√Nd) — Nd barle Rc exponentially kome.
Ei jonnoi IC er prottek contact er niche n+/p+ layer thake.
 Problem 9.28 — Ohmic contact design (flat band) ★★★ — Q1(a) er type
Given: Metal φm = 4.2 V, n-Si with χ = 4.0 V, Eg = 1.12 eV, no interface states, T = 300 K.
(a) Zero bias e kono space charge region na thakle band diagram sketch koro. (b) Oi condition er jonno Nd
ber koro. (c) Metal theke semiconductor e electron er barrier koto?

(a) Sketch er logic: Space charge region na thaka mane flat band — band bending zero. Eta tokhon-i hoy
jokhon φm = φs, mane contact er age duita material er Fermi level eki level e chilo, tai electron transfer
korar dorkar nei. Sketch e: Ec, Ev puropuri horizontal, EF continuous ar flat, metal side e EF eki uchchotay.

(b) φm = φs condition theke Nd:

φs = χ + φn ⇒ φn = φm − χ = 4.2 − 4.0 = 0.2 V

φn = (kT/e) ln(Nc/Nd)
0.2 = 0.0259 × ln(2.8×1019/Nd)
ln(2.8×1019/Nd) = 7.722 → 2.8×1019/Nd = 2256

Nd = 1.24×1016 cm−3 | (c) φBn = φm − χ = 0.2 V

Ei problem ta ki shekhay: Ekta ideal non-rectifying (ohmic) contact er condition. Metal theke semiconductor e
electron er barrier matro 0.2 V — khub chhoto, tai duidik theke-i electron shohoje jete pare → linear, low-
resistance, ohmic.
Kintu practically eta kaj kore na: surface states thakle band diagram change hoye jay ar contact rectifying
hoye jete pare. Neamen er nijer kotha: "we may not necessarily form a good ohmic contact." Ei jonnoi asol IC
te tunneling contact (n+ layer) use hoy, ideal non-rectifying barrier na.

Problem 9.33 — Heterojunction band offsets ★★

Given: Al0.3Ga0.7As–GaAs abrupt heterojunction. Eg(AlGaAs) = 1.85 eV, Eg(GaAs) = 1.42 eV. χ(GaAs) = 4.07,
χ(AlAs) = 3.5. Electron affinity rule use koro.

Step 1 — AlGaAs er electron affinity (linear interpolation):

χ(Al0.3Ga0.7As) = 0.3 × 3.5 + 0.7 × 4.07 = 1.05 + 2.849 = 3.899 V

Step 2 — Anderson's rule:

ΔEc = χ(GaAs) − χ(AlGaAs) = 4.07 − 3.899 = 0.171 eV

Step 3 — Baki ta valence band e:

ΔEg = 1.85 − 1.42 = 0.43 eV
ΔEv = ΔEg − ΔEc = 0.43 − 0.171 = 0.259 eV

Sanity check: ΔEc + ΔEv = 0.171 + 0.259 = 0.43 = ΔEg ✓ — ei check ta proti bar koro.
Keno ei system: GaAs–AlGaAs er lattice mismatch matro 0.14% — tai interface e dislocation prai nei, interface
states kom. Ei jonnoi ei system-i shobcheye beshi use hoy.
2-DEG: N+-AlGaAs / undoped GaAs banale electron wide-gap theke narrow-gap e chole ashe ar conduction
band er triangular notch e atke jay. Electron ar tader donor ion spatially separated → ionized impurity
scattering nei → khub high mobility → HEMT.
PART 3 — CHAPTER 10: MOS Capacitor & MOSFET
Problem 10.2 — xdT ar |Q′SD(max)| ★★

Given: p-Si substrate MOS capacitor @ 300 K. (i) Na = 7×1015, (ii) Na = 3×1016 cm−3.

φfp = Vt ln(Na/ni)
xdT = √[ 4εsφfp / (eNa) ]
|Q′SD(max)| = e Na xdT

Na (cm−3) φfp (V) xdT (cm) |Q′SD(max)| (C/cm2)

7×1015 0.3381 3.54×10−5 3.96×10−8

3×1016 0.3758 1.80×10−5 8.64×10−8

(i) er detail:

φfp = 0.0259 ln(7×1015/1.5×1010) = 0.0259 × 13.054 = 0.3381 V

xdT = √[4(1.035×10−12)(0.3381)/((1.6×10−19)(7×1015))]
= √[1.400×10−12/1.12×10−3] = √(1.250×10−9) = 3.54×10−5 cm
|Q′SD| = (1.6×10−19)(7×1015)(3.54×10−5) = 3.96×10−8 C/cm2

Trend bujho: Na 4.3× barle xdT 2× kome (karon xdT ∝ 1/√Na), kintu |Q′SD| 2.2× bare (karon Q = eNaxdT ∝
√Na). Consequence: heavy doping mane boro bulk charge, mane boro VT. Ei jonnoi VT adjust korte substrate
doping change kora hoy.

Problem 10.4 — φms tinta gate er jonno ★★

Given: p-Si substrate, Na = 6×1015 cm−3. Gate: (a) Al, (b) n+ poly, (c) p+ poly.

φfp = 0.0259 ln(6×1015/1.5×1010) = 0.0259 × 12.899 = 0.3341 V

(a) Al → Figure 10.16 theke read koro: φms ≈ −0.85 V

+
(b) n poly → φms = −(Eg/2e + φfp) = −(0.56 + 0.3341) = −0.894 V
+
(c) p poly → φms = +(Eg/2e − φfp) = +(0.56 − 0.3341) = +0.226 V

Ei duita formula mukhosto koro — ei duita chhara VT er kono question hoy na:
n+ poly: φms = −(Eg/2e + φfp) | p+ poly: φms = +(Eg/2e − φfp)
Si te Eg/2e = 0.56 V — ei number ta mukhosto rakho.

Interpretation: n+ ar p+ gate er moddhe φms difference prai 1.12 V = Eg — mane gate material change korei
VT ke 1.1 V shorano jay. Ei jonnoi CMOS e n-channel e n+ gate ar p-channel e p+ gate use hoy (dual-gate
technology) — duitai surface-channel enhancement device banate.
 Problem 10.9 — VFB theke Q′ss (reverse) ★★

Given: Al gate–SiO2–p-Si, tox = 450 Å, Na = 2×1016, measured VFB = −1.0 V. Figure 10.16 theke φms(Al) ≈
−0.90 V. Find: Q′ss.

Cox = εox/tox = 3.45×10−13/(450×10−8) = 7.667×10−8 F/cm2

VFB = φms − Q′ss/Cox

−1.0 = −0.90 − Q′ss/(7.667×10−8)
Q′ss/Cox = 0.10 V
Q′ss = 0.10 × 7.667×10−8 = 7.67×10−9 C/cm2

Q′ss = 7.67×10−9 C/cm2 = 4.79×1010 charges/cm2

Interpretation: Q′ss positive asha expected — SiO2–Si interface e fixed oxide charge prai shobshomoy positive
hoy (incomplete oxidation er jonno). Ar positive Q′ss VFB ke negative dike thele (−0.90 → −1.0) — ei ta n-
channel ar p-channel duitatei true. 4.79×1010 cm−2 ekta typical modern process value (1010–1011).

Problem 10.10 — VT full chain, tinta gate ★★★

Given: p-Si, Na = 2×1016, tox = 150 Å, Q′ss = 7×1010 cm−2. Gate: (a) n+ poly, (b) p+ poly, (c) Al (φms ≈
−0.90).

Step 1–4 — Gate-independent part (ekbar korle tin case e-i khatbe):

φfp = 0.0259 ln(2×1016/1.5×1010) = 0.0259 × 14.103 = 0.3653 V

xdT = √[4(1.035×10 −12
)(0.3653)/((1.6×10 −19
)(2×10 16
))] = 2.174×10−5 cm
|Q′SD| = (1.6×10−19)(2×1016)(2.174×10−5) = 6.956×10−8 C/cm2
Cox = 3.45×10−13/150×10−8 = 2.300×10−7 F/cm2
Q′ss(charge) = 7×1010 × 1.6×10−19 = 1.12×10−8 C/cm2

(|Q′SD| − Q′ss)/Cox = (6.956−1.12)×10−8/2.300×10−7 = 0.2538 V

2φfp = 0.7306 V

Step 5 — VTN = 0.2538 + φms + 0.7306:

Gate φms (V) VTN (V) Mode

(a) n+ poly −(0.56+0.3653) = −0.925 +0.059 enhancement (khub kom VT)

(b) p+ poly +(0.56−0.3653) = +0.195 +1.179 enhancement (boro VT)

(c) Al −0.900 +0.084 enhancement

Interpretation: Gate material change korei VT 0.059 V theke 1.179 V — prai 1.12 V = Eg er difference. Ei ta-i
CMOS design er main lever. n+ poly er VT khub kom (0.059 V) — noise margin er jonno eta bipodjonok, tai
practical device e substrate doping ba threshold-adjust implant diye VT ke 0.3–0.7 V e ana hoy.
Problem 10.23 — C–V er shob capacitance ★★★
Given: Ideal MOS capacitor (Q′ss = 0), n+ poly gate, tox = 120 Å, p-Si Na = 1016 cm−3. Find: Cox, C′FB, C′min,
C′(inv) @ 1 Hz ar 1 MHz; VFB, VT.

φfp = 0.0259 ln(1016/1.5×1010) = 0.3473 V

xdT = √[4(1.035×10−12)(0.3473)/((1.6×10−19)(1016))] = 2.998×10−5 cm
Cox = 3.45×10−13/120×10−8 = 2.875×10−7 F/cm2

C′min = εox / [ tox + (εox/εs)·xdT ]

= 3.45×10−13 / [1.2×10−6 + 0.3333×2.998×10−5]
= 3.45×10−13 / 1.119×10−5 = 3.082×10−8 F/cm2

Debye length: LD = √[εskT/(e2Na)] = √[2.681×10−14/1.6×10−3] = 4.093×10−6 cm

C′FB = εox/[tox + (ε /ε )L ] = 1.345×10−7 F/cm2
ox s D

Frequency Accumulation Flat band Inversion

(a) f = 1 Hz (LF) 2.875×10−7 1.345×10−7 2.875×10−7 (= Cox)

(b) f = 1 MHz (HF) 2.875×10−7 1.345×10−7 3.082×10−8 (= Cmin)

(c) φms = −(0.56 + 0.3473) = −0.9073 V ; Q′ss = 0 ⇒ VFB = φms = −0.907 V

−19 16 −5 −8
|Q′SD| = (1.6×10 )(10 )(2.998×10 ) = 4.797×10
VT = VFB + 2φfp + |Q′SD|/Cox = −0.907 + 0.695 + 0.167 = −0.046 V

(d) Sketch er guide: C′/Cox vs VG

• Negative VG (accumulation): ratio = 1.0
• Flat band (VG = −0.907 V): ratio = 1.345×10−7/2.875×10−7 = 0.468
• Threshold (VG = −0.046 V) er pore: LF curve abar 1.0 e uthe jay; HF curve 0.107 e flat thake
• Deep depletion (fast ramp): 0.107 er-o niche neme jay
Keno LF te C abar bare: minority carrier (electron) signal follow korte pare — generation-recombination time
er cheye signal slow, tai inversion charge dole ar capacitance abar Cox hoye jay. HF te pare na, shudhu
depletion edge dole.
VT negative mane ei device depletion mode — VG = 0 tei channel ache.
 Problem 10.30 — HF C–V graph theke extraction ★★★ — Q2(a) er EXACT type
Given: Graph theke Cmax = 200 pF, Cmin = 20 pF, VFB = −0.8 V. Area A = 2×10−3 cm2, φms = −0.50 V,
doping 2×1016 cm−3, SiO2/Si.

(a) Type identify: Curve ta negative VG te high (200 pF) ar positive VG te low (20 pF). Negative gate voltage
e accumulation howa mane majority carrier hole → substrate p-type.
(b) tox:

C′ox = Cox/A = 200×10−12/2×10−3 = 1.00×10−7 F/cm2

tox = εox/C′ox = 3.45×10−13/1.00×10−7 = 3.45×10−6 cm = 345 Å

(c) Q′ss:
VFB = φms − Q′ss/C′ox
−0.8 = −0.50 − Q′ss/(1.00×10−7)
Q′ss = 0.30 × 1.00×10−7 = 3.00×10−8 C/cm2 = 1.88×1011 cm−2

(d) Flat-band capacitance:

LD = √[εskT/(e2Na)] = √[(1.035×10−12)(0.0259)/((1.6×10−19)(2×1016))]
= √[2.681×10−14/3.2×10−3] = 2.894×10−6 cm

C′FB = εox/[tox + (εox/εs)LD]

= 3.45×10−13/[3.45×10−6 + 0.3333×2.894×10−6]
= 3.45×10−13/4.415×10−6 = 7.815×10−8 F/cm2
CFB = 7.815×10−8 × 2×10−3 = 156 pF

(a) p-type | (b) tox = 345 Å | (c) Q′ss = 1.88×1011 cm−2 | (d) CFB = 156 pF

Jodi Na deya na thake (ar shudhu Cmin deya thake), tahole ei extra step:
1/C′min = 1/C′ox + xdT/εs → xdT ber koro
Tarpor xdT = √[4εsφfp/(eNa)] ar φfp = Vtln(Na/ni) — duita equation, ek unknown → ITERATE koro (Na guess →
φfp → xdT check → adjust; 2–3 bar e mele)

Q′ss vs interface states — ei difference ta question e ashe:

• Fixed oxide charge Q′ss: curve ta shomantoral bhabe shore jay (parallel shift), shape change hoy na
• Interface states Dit: curve "stretch-out" hoy, distort kore — karon interface state gulo charge nite/dite pare,
tai gate voltage er ekta ongsho oder charge korte kharoch hoy
Mane: shift = fixed charge, stretch-out = interface states.
Problem 10.33 & 10.35 — MOSFET I–V, region determination ★★★
10.33 Given: n-channel, k′n = 0.18 mA/V2, W/L = 8, VT = 0.4 V.

Kn = (k′n/2)(W/L) = 0.09 × 8 = 0.72 mA/V2

AGE REGION DECIDE KORO:

VDS < VGS−VT → nonsaturation: ID = Kn[2(VGS−VT)VDS − VDS2]
VDS ≥ VGS−VT → saturation: ID = Kn(VGS−VT)2

Case VGS−VT VDS Region ID

(a) VGS=0.8, VDS=0.2 0.4 0.2 nonsat 0.72[2(0.4)(0.2)−0.04] = 0.0864 mA
(b) VGS=0.8, VDS=1.2 0.4 1.2 sat 0.72(0.4)2 = 0.115 mA
(c) VGS=0.8, VDS=2.5 0.4 2.5 sat 0.115 mA (same!)
(d) VGS=1.2, VDS=2.5 0.8 2.5 sat 0.72(0.8)2 = 0.461 mA

(b) ar (c) same — ei ta-i saturation er definition: VDS barleo ID change hoy na (ideal case e). Ar (d) te VGS−VT
2× barle ID 4× bare — square law.

10.35 Given: k′n = 0.6 mA/V2, VT = 0.8 V. ID = 1 mA @ VGS = 1.4, VDS = 4 V.

(a) VGS−VT = 0.6, VDS = 4 > 0.6 → saturation

1 = (0.6/2)(W/L)(0.6)2 = 0.3 × 0.36 × (W/L) = 0.108(W/L)
W/L = 9.26, ar Kn = 0.3 × 9.26 = 2.778 mA/V2

(b) VGS=1.85 → VGS−VT = 1.05, VDS=6 > 1.05 → sat

ID = 2.778 × (1.05)2 = 3.06 mA

(c) VGS=1.2 → VGS−VT = 0.4, VDS=0.15 < 0.4 → nonsat

2
ID = 2.778[2(0.4)(0.15) − (0.15) ] = 2.778[0.12 − 0.0225] = 0.271 mA

Shobcheye common bhul: region check na kore direct saturation formula boshano. Proti bar VDS ar (VGS−VT)
compare koro age — ei ekta step 10 marks bachay.
Problem 10.47 — Process conduction parameter ar W/L ★★
Given: (a) n-channel: tox = 180 Å, μn = 450, VT = 0.4 V, ID(sat) = 0.8 mA @ VGS = 2.0 V. (b) p-channel: same
tox, μp = 210, VT = −0.4 V, ID(sat) = 0.8 mA @ VSG = 2.0 V.

Cox = 3.45×10−13/180×10−8 = 1.917×10−7 F/cm2

(a)(i) k′n = μnCox = 450 × 1.917×10−7 = 8.63×10−5 A/V2 = 86.3 μA/V2

(ii) 0.8×10−3 = (k′n/2)(W/L)(2.0−0.4)2 = (4.31×10−5)(2.56)(W/L)
W/L = 7.25

(b)(i) k′p = 210 × 1.917×10−7 = 40.3 μA/V2

(ii) 0.8×10−3 = (2.01×10−5)(2.56)(W/L) → W/L = 15.5

Ei ta CMOS design er core insight: Same current pete p-channel er W/L 2.14× boro lagbe — karon μp/μn =
210/450 = 0.467, ar 1/0.467 = 2.14. Ei jonnoi CMOS inverter e PMOS transistor ta NMOS er cheye 2–3×
choura banano hoy — symmetric switching pete.

Problem 10.50 — Body effect coefficient ar VT shift ★★★

Given: n-channel, Na = 5×1016, tox = 150 Å, μn = 450, VFB = −0.5 V, L = 1.2 μm, W = 8 μm.

(a) Cox = 3.45×10−13/150×10−8 = 2.300×10−7 F/cm2

γ = √(2eεsNa) / Cox
= √[2(1.6×10−19)(1.035×10−12)(5×1016)] / 2.300×10−7
= √(1.656×10−14) / 2.300×10−7 = 1.287×10−7/2.300×10−7
= 0.560 V1/2

(c) φfp = 0.0259 ln(5×1016/1.5×1010) = 0.389 V , 2φfp = 0.778 V

xdT = 1.419×10−5 cm , |Q′SD| = 1.135×10−7 C/cm2
VT(VSB=0) = VFB + 2φfp + |Q′SD|/Cox = −0.5 + 0.778 + 0.494 = 0.772 V

ΔVT = γ[ √(2φfp + VSB) − √(2φfp) ]

VSB √(0.778+VSB) ΔVT (V) VT (V)

0 0.882 0 0.772
1V 1.333 0.253 1.024
2V 1.667 0.439 1.211
4V 2.186 0.730 1.501

Physics (ei paragraph likho): VSB positive dile source–body junction reverse biased hoy → depletion region
choura hoy → |Q′SD| bare → oi extra bulk charge balance korte gate ke aro voltage dite hoy → VT bare. Band
diagram e: VSB=0 e inversion e φs = 2φfp; VSB>0 hole φs = 2φfp + VSB.
Circuit consequence: VSB = 4 V te VT prai dwigun (0.772 → 1.501). Series-stacked NMOS (NAND gate er moto)
e upoler transistor er source ground e nei, tai tar VSB > 0 — oi transistor durbol hoye jay. Ei jonnoi stacked
logic dhire chole. Solution: kom doping (γ ∝ √Na) ba patla oxide (γ ∝ tox) — ba SOI, jekhane body float kore.
Problem 10.51 & 10.52 — Body effect, reverse problems ★★★ — Q1(b) er EXACT type
10.51 Given: n-channel, Na = 1016, γ = 0.12 V1/2. VT = 0.5 V @ VSB = 2.5 V. Find: VT @ VSB = 0.

φfp = 0.0259 ln(1016/1.5×1010) = 0.3473 V , 2φfp = 0.6946 V

ΔVT = 0.12[√(0.6946+2.5) − √0.6946] = 0.12[1.7873 − 0.8334] = 0.12 × 0.9539 = 0.1145 V

VT(VSB=0) = VT(VSB=2.5) − ΔVT = 0.5 − 0.1145 = 0.386 V

10.52 Given: p-channel, tox = 200 Å, Nd = 5×1015. (a) γ ber koro. (b) ΔVT = −0.22 V pete VBS koto lagbe?

(a) Cox = 3.45×10−13/200×10−8 = 1.725×10−7 F/cm2

γ = √(2eεsNd)/Cox = √(1.656×10−15)/1.725×10−7
= 4.069×10−8/1.725×10−7 = 0.236 V1/2

(b) φfn = 0.0259 ln(5×1015/1.5×1010) = 0.329 V , 2φfn = 0.659 V

|ΔVT| = γ[√(2φfn + VBS) − √(2φfn)]

0.22 / 0.236 = 0.9326 = √(0.659 + VBS) − 0.812
√(0.659 + VBS) = 1.744
0.659 + VBS = 3.043

10.51: VT(0) = 0.386 V | 10.52: γ = 0.236 V1/2, VBS = 2.38 V

p-channel er sign (ekhane shobai bhul kore): p-channel e Nd ar φfn use koro (Na, φfp na). Body-to-source
voltage VBS positive dile VTP aro negative hoy (ΔVT = −0.22 V) — mane channel toiri korte aro boro negative
gate voltage lagbe. Physics eki, shudhu sign ulta.
Problem 10.53 — Depletion mode + VSB diye VT = 0 ★★

Given: NMOS, n+ poly gate, tox = 400 Å, Na = 1015, Q′ss = 5×1010 cm−2.

(a) φfp = 0.0259 ln(1015/1.5×1010) = 0.2877 V , 2φfp = 0.5754 V

−5 −8
xdT = 8.628×10 cm , |Q′SD| = 1.380×10 C/cm2
Cox = 3.45×10−13/400×10−8 = 8.625×10−8 F/cm2
φms = −(0.56 + 0.2877) = −0.8477 V
Q′ss(charge) = 5×1010 × 1.6×10−19 = 8.0×10−9 C/cm2

VT = (1.380×10−8 − 8.0×10−9)/8.625×10−8 − 0.8477 + 0.5754

= 0.0673 − 0.8477 + 0.5754 = −0.205 V

(b) VT = 0 pete ΔVT = +0.205 V dorkar

γ = √(2eεsNa)/Cox = 1.820×10−8/8.625×10−8 = 0.211 V1/2
0.205/0.211 = 0.972 = √(0.5754+VSB) − 0.7586
√(0.5754+VSB) = 1.731 → 0.5754 + VSB = 2.995

(a) VT = −0.205 V (depletion mode) | (b) Hae, VSB = 2.42 V

Interpretation: VT negative mane VG = 0 tei channel ache — depletion mode device. Ei ta hoyeche tinta
karone ekshathe: (1) doping khub kom (1015) tai |Q′SD|/Cox chhoto, (2) n+ poly gate er φms boro negative, (3)
positive Q′ss VT ke aro negative dike thele.
Ar (b) ta khub practical: body bias diye ekta depletion device ke enhancement e convert kora jay —
fabrication er por-o VT tune korar rasta.
Problem 10.56 — Cutoff frequency (ideal vs real) ★★
Given: μn = 400, tox = 500 Å, L = 2 μm, W = 20 μm, VT = 0.75 V, saturation @ VGS = 4 V. (b) gate oxide
source ar drain duitar shathe 0.75 μm overlap kore, RL = 10 kΩ.

(a) IDEAL (overlap nei):

fT = μn(VGS−VT) / (2πL2) = 400 × 3.25 / (2π × (2×10−4)2)
= 1300 / (2π × 4×10−8) = 1300/2.513×10−7 = 5.17 GHz

(b) OVERLAP soho:

Cox = 3.45×10−13/500×10−8 = 6.90×10−8 F/cm2
Cgs(channel) = Cox·W·L = 6.90×10−8 × 20×10−4 × 2×10−4 = 2.76×10−14 F
Coverlap = Cox·W·(0.75 μm) = 6.90×10−8 × 20×10−4 × 0.75×10−4 = 1.035×10−14 F

gms = (WμnCox/L)(VGS−VT) = (20×10−4 × 400 × 6.90×10−8/2×10−4) × 3.25

= 2.76×10−4 × 3.25 = 8.97×10−4 S

MILLER: CM = Cgd(1 + gmRL) = 1.035×10−14(1 + 8.97×10−4×104)

= 1.035×10−14 × 9.97 = 1.032×10−13 F

fT = gm / [2π(CgsT + CM)] = 8.97×10−4/[2π(3.795×10−14 + 1.032×10−13)]

= 8.97×10−4/8.87×10−13 = 1.01 GHz

(a) fT(ideal) = 5.17 GHz | (b) fT(real) = 1.01 GHz — 5× kome gelo

Duita boro lesson:

(1) fT ∝ 1/L2 — ei jonnoi scaling. L ordhek korle fT 4× bare.
(2) Overlap capacitance ta killer. Saturation e intrinsic Cgd ≈ 0, kintu overlap er Cgd thake ar Miller effect er
jonno (1 + gmRL) = 9.97 gun hoye jay — ekai total capacitance er 73%. Ei jonnoi self-aligned gate process
(gate ke mask hishebe use kore source/drain implant kora) develop kora hoyeche — overlap minimum korte.
APPENDIX — Quick Answer Sheet
Problem Answer
4.3 (a) 368 K (b) 418 K

4.4 Eg = 1.316 eV, Nc0Nv0 = 9.46×1037 cm−6

4.17 0.2148 eV; 0.9052 eV; p0=3.21×104; hole minority; 0.338 eV

(a) 7.5×104, 3×1015 (b) 3×1016, 7.5×103 (c) 1.5×1010 both (d) 1.28×108, 4×1015 (e)
4.34
1.03×1014, 2.76×1012

4.37 (a) 8.85×10−4 (b) 2.87×10−5

4.45 ni = 5.74×1013, p0 = 3.0×1013

4.47 n-type; n0=1.125×1016, p0=2×104; Nd=1.83×1016

4.50 (a) 538 K (b) 0.265 → 0.514 eV (Δ=+0.249) (c) intrinsic er kache

4.54 Nd = 1.19×1016 cm−3

4.61 Eg,min = 0.625 eV

9.3 φB0=1.09 V, Vbi=0.884 V; xn=4.94/8.73×10−5 cm, Emax=7.63×104/1.35×105 V/cm

9.7 Method: slope→Nd, x-intercept→Vbi, φB0=Vbi+φn

9.8 Vbi=0.447 V; Δφ=0.0241/0.0336 V, xm=25.5/18.3 Å

9.14 φn=0.224, Vbi=0.667 V, JsT=1.29×10−8 A/cm2, Va=0.512 V

9.20 0.485 V / 0.770 V; Apn = 9.98×10−6 cm2

9.25 / 9.27 0.1 / 1.0 / 10 Ω | φBn = 0.258 V / 0.198 V

9.28 Nd = 1.24×1016 cm−3, φBn = 0.2 V

9.33 ΔEc = 0.171 eV, ΔEv = 0.259 eV

10.2 3.54×10−5 cm / 3.96×10−8 | 1.80×10−5 cm / 8.64×10−8

10.4 Al −0.85, n+ −0.894, p+ +0.226 V

10.9 Q′ss = 7.67×10−9 C/cm2 = 4.79×1010 cm−2

10.10 n+: +0.059 V | p+: +1.179 V | Al: +0.084 V

10.23 Cox=2.875×10−7, CFB=1.345×10−7, Cmin=3.082×10−8; VFB=−0.907, VT=−0.046 V

10.30 p-type; 345 Å; 1.88×1011 cm−2; CFB = 156 pF

10.33 0.0864 / 0.115 / 0.115 / 0.461 mA

10.35 W/L = 9.26; 3.06 mA; 0.271 mA

10.47 n: 86.3 μA/V2, W/L=7.25 | p: 40.3 μA/V2, W/L=15.5

10.50 γ=0.560 V1/2; VT = 0.772 / 1.024 / 1.211 / 1.501 V

10.51 /
VT(0)=0.386 V | γ=0.236 V1/2, VBS=2.38 V
10.52

10.53 VT = −0.205 V (depletion); VSB = 2.42 V

10.56 5.17 GHz (ideal) → 1.01 GHz (with overlap)

Exam hall er 6 ta rule
# Rule
1 Shob cm e convert koro age. 1 μm = 10−4 cm, 1 nm = 10−7 cm, 1 Å = 10−8 cm
2 MOSFET e region check age: VDS vs (VGS−VT) compare na kore formula boshio na
3 Chain question e prottek intermediate value likho — final bhul holeo step marks pabe
4 Section A te ni = 1.5×1010, Nv = 1.04×1019 (Neamen)। Section B te del Alamo er alada value
5 "Quantitatively sketch" mane number chai — axis e label + value dao
6 Prottek answer er sheshe 1 line physical interpretation — ekhane free marks ache

Mukhosto rakhar number

Eg/k = 12993 K (Si) Eg/2e = 0.56 V (Si)
kT = 0.0259 V 3kT = 78 meV (degenerate limit)
38 2
NcNv = 2.912×10 (Si) ni = 2.25×1020 (Si)
εox/εs = 1/3 χ(Si) = 4.01 V
A*T2 = 1.08×107 (Si, 300K) φm: Al 4.28, W 4.55, Au 5.1, Pt 5.65