Computer Organization

& Architecture
UTER
MODULE 1 · BASIC STRUCTURE OF COMP

✦ Handwritten Master Notes ✦

Beginner ➔ Exam Level

★ Based on IPS Academy (RGPV Autonomous) Syllabus

✎ Style: Hinglish · Professor to Weak-Student Explanation

★ References: Morris Mano · William Stallings · Alan Clements ·

Subrata Ghosal · Usha & Shrikant · P. Pal Chaudhuri
► Covers: Theory + Diagrams + RTL + Numericals + PYQs + Viva

· A + re a dy
T ER EXA M
ES
FOR SEM

COA MODULE 1 | Page 2 of 103

 ✎ Table of Contents
1. Chapter 1 — What is Computer Organization & Architecture

2. Chapter 2 — Structure of a Desktop Computer & Block Diagram

3. Chapter 3 — Input Unit, Output Unit, Memory, Storage & Power Supply

4. Chapter 4 — Motherboard: Layout & Components

5. Chapter 5 — CPU Organization: Internal Structure & Working

6. Chapter 6 — CPU Registers (PC, IR, MAR, MDR, ACC, SR, GPRs, Flags)

7. Chapter 7 — Stack Organization (PUSH, POP, CALL, RETURN, INTERRUPT)

8. Chapter 8 — ALU: Arithmetic, Logical, Shift & Compare Operations

9. Chapter 9 — Instruction & Instruction Cycle

10. Chapter 10 — Instruction Formats (0, 1, 2, 3-address, R/I/J-type)

11. Chapter 11 — Bus Organization (Address / Data / Control / System)

12. Chapter 12 — Register Transfer Language (RTL) & Micro-operations

13. Chapter 13 — Addressing Modes (9 modes with examples)

14. Chapter 14 — Control Unit: Hardwired vs Microprogrammed

15. Chapter 15 — 30+ Solved Numericals & RTL Problems

16. Chapter 16 — Exam Corner: 2 · 5 · 10 · 15 Mark Questions & PYQs

17. Chapter 17 — Viva & Interview Question Bank (60+ Qs)

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18. Chapter 18 — Common Mistakes & Exam Traps

19. Chapter 19 — Memory Tricks, Formula Sheet & Cheat Sheet

20. Chapter 20 — One-Page Revision Notes & One-Hour Revision

COA MODULE 1 | Page 4 of 103

Chapter 1 — What is Computer
Organization & Architecture?

1.1 Let's Start From Zero

Beta, chalo bilkul basic se shuru karte hain. Ek computer ek machine hai jo
data ko input ke roop mein leta hai, usse process karta hai aur output deta
hai. Bas itni si baat hai — lekin andar itna sara circuitry hai ki poori ek
subject ban gayi: Computer Organization & Architecture (COA).
Isliye pehle do words ka meaning samajhte hain:
• Architecture = "KYA (what)" — programmer ko kya dikhta hai
(instruction set, registers, addressing modes)
• Organization = "KAISE (how)" — hardware physically kaise banaya jaata
hai (buses, control signals, memory chips)

★ DEFINITION
Computer Architecture: Vo attributes jo programmer ko visible hote hain
aur program ki logical execution par direct effect daalte hain. Jaise —
instruction set, data types, addressing modes, register organization, I/O
mechanism.
Computer Organization: Vo attributes jo programmer ko visible nahi hote
— sirf hardware designer ke liye important hain. Jaise — control signals,
memory technology (SRAM/DRAM), bus width, interface between CPU aur
peripherals.

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 — Reference: William Stallings, Chapter 1

Real-Life Analogy — Car Wala Example (car)

◆ REAL-LIFE ANALOGY
Architecture = Car ka steering wheel, gear, brake pedal, speedometer.
Driver (programmer) ko yehi sab dikhta hai aur usse hi car chalata hai.
Organization = Engine ke andar piston kaise move karta hai, radiator
kaise cool karta hai, transmission gear kaise shift hoti hai — driver ko
farak nahi padta, lekin mechanic (hardware designer) ke liye critical hai.
Punch line: Do alag-alag cars (say Maruti Swift & Baleno) same
architecture rakh sakti hain (same steering, gears — same driving
experience) but organization alag ho sakti hai (engine size, fuel injection
type). Similarly, Intel i3 aur i7 ka architecture x86-64 same hai, but
organization (cache size, cores, pipeline depth) alag hai.

Why We Need Both

Sochein ki aap sirf architecture jaante ho — to aap program likh sakte ho but
hardware nahi bana sakte. Aur agar sirf organization jaante ho — to hardware
bana sakte ho but programmer ko manual likh ke nahi de sakte. Isliye
Engineering student ko dono aana chahiye. Aur RGPV isliye COA subject 3rd
semester mein compulsory karta hai. :)

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 1.2 Detailed Difference Table (VERY
IMPORTANT for exam)
Yeh table exam mein 5-mark question ke roop mein direct aata hai. Isko rat
lo, minimum 6 points chahiye. IPS Academy vale kaafi baar puchte hain.

# Feature Computer Architecture Computer Organization

1 Focus Logical / functional view Physical / structural view

2 Answers WHAT the computer does HOW it does

3 Visible to Programmer / compiler Hardware designer / engineer

writer

4 Examples ISA, addressing modes, Control signals, bus width,

register set, data types memory technology

5 Decided First (design phase) After architecture

(implementation)

6 Changes Rarely (stable across Frequently (each new chip)

generations)

7 Concerned Attributes visible to Operational units and

with programmer interconnections

8 Example Intel x86 ISA (same for i3, Different die sizes and cache
device i5, i7, i9) in i3 vs i9

❖ MEMORY TRICK
Mnemonic — "PAWA":
• Programmer sees → Architecture

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• Architect designs → What (spec)
• Worker builds → Attributes (organization = hardware)
Yaad rakho: "A for API/Architecture, O for Organs/Organization".

✎ PYQ / EXAM QUESTION

Q. (RGPV 2019 · 5 marks) Differentiate between Computer Architecture
and Computer Organization. Give one example of each. [Solution hint: use
above table + 2-line examples]
Q. (RGPV 2022 · 2 marks) Define Computer Organization.

♪ VIVA / INTERVIEW
Q1: Kya alag machines same architecture ho sakti hain?
Ans: Haan — Intel i3 aur i7 ka architecture (x86-64 ISA) same hai but
organization alag.
Q2: Jab compiler design karte hain to architecture yaad rakhna zaroori
kyun?
Ans: Kyunki compiler ne jo assembly output diya wo target machine ke
ISA (architecture) ke hisaab se hona chahiye — organization se compiler
ko farak nahi padta.

⚠ COMMON MISTAKE
× Students often swap the two terms — "control signals" ko architecture
bol dete hain. Yaad rakho: control signals hardware detail hai, so
Organization.

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Chapter 2 — Structure of a Desktop
Computer & Block Diagram

2.1 Real Life se Concept Samjhein

Ek desktop PC apke saamne rakha hai. Uske andar jo cheezein hain, unhe main
5 functional units mein baant sakte hain. Har unit ka ek specific kaam hai,
aur ye sab ek "bus" (a group of wires) ke through ek dusre se baat karte hain.

◆ REAL-LIFE ANALOGY
Analogy — Restaurant Kitchen (kitchen)
• Input Unit = Waiter jo customer ka order (data) le ke aata hai
(keyboard/mouse)
• Memory = Fridge + shelves jahan ingredients (data + recipes) rakhe
hain
• CPU = Head chef jo actually khaana banata hai
○ ALU = Chef ke haath (cutting, mixing, cooking)
○ Control Unit = Chef ka dimaag (kis order mein banana hai, kaunsa
ingredient uthana hai)
○ Registers = Chef ke saamne rakhi small plates (turant use hone wala
data)
• Output Unit = Waiter jo customer ko dish serve karta hai (monitor/
printer)
• Bus = Kitchen ke andar walking path — jinse waiter ingredients laate,
orders bhejte hain

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 2.2 The Famous "5 Functional Units" Block
Diagram

Figure 2.1 — Von Neumann Style Block Diagram of a Computer

Kaam Kya Hai Har Unit Ka?

Unit Function (Kaam) Real Examples

Input User se data / instructions leta hai, Keyboard, Mouse, Scanner,

Unit binary mein convert karta hai, Webcam, Mic, Touchscreen
memory tak pahunchata hai

Memory Data + instructions ko store karta RAM (primary), Cache,

Unit hai — CPU jab chahe fetch kar sake ROM, HDD/SSD (secondary)

ALU

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 Actual computation — arithmetic (+, Adder circuits inside Intel
−,×,÷) + logical (AND, OR, XOR, Core i9, Ryzen 7
NOT) + shift + compare

Control Sab ko coordinate karta hai — CPU Hardwired CU (RISC) or

Unit ka traffic police. Control signals Microprogrammed CU
generate karta hai (CISC)

Output Processed result ko human-readable Monitor, Printer, Speaker,

Unit form mein bhejta hai Projector

► STICKY-NOTE TIP
Data (green arrows in diagram) aur Control signals (red dashed arrows)
alag-alag paths use karte hain. Isliye system bus ko hum 3 buses mein
tod dete hain: Data Bus, Address Bus, Control Bus (Chapter 11 mein
detail).

2.3 Von Neumann vs Harvard Architecture

Ye do main styles hain jinme computers banaye jaate hain. Concept 1945 mein
John von Neumann ne diya tha — that's why the name.

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 Figure 2.2 — Two Fundamental Architectures

Point Von Neumann Harvard

Memory Single memory for data + Separate memory for data &
instructions instructions

Buses Same bus for both Two buses (data + instruction)

Bottleneck Yes — famous "von No — parallel access possible

Neumann bottleneck"

Complexity / Simple, cheap Complex, costly

cost

Speed Slower Faster (parallel fetch)

Examples Most desktop PCs, IAS Microcontrollers (AVR, PIC),

machine DSPs, ARM Cortex-M

❖ MEMORY TRICK

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Trick: "Von Neumann → One memory · Harvard → Two memories". Ya phir
yaad karo: Harvard University = Har ek subject ke liye alag classroom =
alag memory. (*)

✎ PYQ / EXAM QUESTION

Q. (RGPV 2021 · 5 marks) Compare Von Neumann and Harvard
Architectures with suitable block diagrams.

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Chapter 3 — I/O Units, Memory &
Storage Devices

3.1 Input Unit — In Depth

★ DEFINITION
Input Unit vo hardware devices hain jo user ke raw data (text, image,
sound, motion) ko computer ke binary form (0s and 1s) mein convert
karke memory tak pahuchate hain.

Types of Input Devices:

1. Keyboard — Sabse common. Har key ka apna scan code hota hai jo
controller ASCII/Unicode mein map karta hai.
2. Pointing devices — Mouse, Trackball, Touchpad, Light pen, Joystick.
3. Scanners — Flatbed, handheld, barcode, OMR, MICR.
4. Voice / Audio — Microphone (uses ADC — Analog to Digital Converter).
5. Camera — Webcam, Digital camera (uses CCD/CMOS sensors).
6. Biometric — Fingerprint, retina, face-recognition sensor.
7. Sensors (embedded/IoT) — Temperature, pressure, gyro, GPS.

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 3.2 Output Unit
★ DEFINITION
Output Unit CPU ke processed binary data ko human-readable form
(text, image, sound, hardcopy) mein convert karta hai.

Category Devices Working Concept

Visual Monitor (CRT, LCD, LED, Pixels lit up using electron

(softcopy) OLED), Projector gun / backlight / self-emissive
diodes

Hardcopy Impact (Dot-matrix), Non- Print head or laser drum

impact (Inkjet, Laser, transfers ink/toner to paper
Thermal)

Audio Speaker, Headphones DAC → amplifier → diaphragm

vibration = sound

Tactile / VR Braille display, Haptic gloves, Actuators create pressure/

VR headset vibration

3.3 Memory Unit — Bird's Eye View

Detailed memory Module-4 mein karenge, yahaan sirf overview.

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 Figure 3.1 — Memory Hierarchy Pyramid

Golden Rule of the Pyramid: Upar jaate jaate → speed ⬆, cost/byte ⬆, size
⬇. Neeche jaate jaate → capacity ⬆, cheap ⬆, but slow ⬇.

Primary Memory (Main Memory)

• RAM (Random Access Memory) — Volatile. Power off → data gone. Types:
SRAM (fast, expensive, used in cache) & DRAM (slower, cheaper, used as
main memory).
• ROM (Read Only Memory) — Non-volatile. Firmware / BIOS store karta
hai. Types: Mask-ROM, PROM, EPROM (UV erasable), EEPROM (electrically
erasable), Flash.

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 • Cache Memory — Very fast SRAM, sits between CPU & RAM. Levels: L1
(inside core), L2 (inside CPU die), L3 (shared).
• Registers — Fastest, inside CPU. Sirf few KB total.

Secondary Memory (Storage Devices)

Device Technology Speed Capacity Use

HDD Magnetic disk + 5–10 ms 1–16 TB Bulk storage

moving head

SSD NAND flash (no 0.1 ms 256 GB–4 Fast boot,

moving parts) TB laptops

Optical (CD/ Laser + reflective slow 700 MB – Movies,

DVD/BD) disc 100 GB backups

Magnetic Tape Sequential access very slow PB+ Archival,

tape banks

Flash Drive NAND flash fast 4 GB–2 TB Portable

(USB) data

Cloud Remote server + network Unlimited Backup,

network limited (paid) sync

3.4 Power Supply Unit (PSU) & SMPS

★ DEFINITION
SMPS (Switched Mode Power Supply): A power supply that uses high-
frequency switching regulators to efficiently convert electrical power.

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 Desktop PC mein 230V AC (wall) → different DC voltages (+3.3V, +5V,
+12V, −12V) mein convert karta hai for motherboard/HDD/GPU.

Why SMPS instead of linear power supply?

✓ Advantages ✗ Disadvantages
• Efficiency 70–95% • Complex circuitry
• Small & light • Generates EMI
• Wide input range (electromagnetic noise)
• Multiple DC outputs • Costlier than linear at low
wattages

Common PSU wattages: 300 W (office PC) · 500–650 W (gaming) · 850–

1000 W (workstation with high-end GPU).

► STICKY-NOTE TIP
Kabhi bhi cheap PSU mat kharido — ye ek matlab wala component hai
jiska failure motherboard, RAM, GPU sabko fry kar sakta hai. 80+
Bronze / Gold / Platinum ratings dekhna zaruri hai.

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Chapter 4 — Motherboard: The PCB
That Binds Everything

4.1 Definition & Purpose

★ DEFINITION
Motherboard (Mainboard / MoBo): A large printed circuit board (PCB)
that acts as the central backbone of a computer, providing electrical &
data connections between the CPU, RAM, storage, power supply, GPU and
all peripherals.

◆ REAL-LIFE ANALOGY
Analogy: Motherboard is like the road-map of a city. CPU is the "city
center" (downtown), RAM slots are "shopping malls", storage is
"warehouse district", PSU is "power station", BIOS/CMOS is the "traffic
control office". Buses are the roads connecting them.

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 4.2 Simplified Motherboard Layout

Figure 4.1 — Typical Desktop Motherboard Layout

4.3 Component-by-Component Explanation

# Component Role (Kaam)

1 CPU Socket Physically mount the processor. LGA (pins on socket,

(LGA / PGA) Intel) or PGA (pins on chip, AMD).

2 RAM Slots Insert DDR3 / DDR4 / DDR5 memory modules.

(DIMM) Usually 2 or 4 slots supporting dual/quad channel.

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3 Chipset Route data between CPU, RAM, GPU (Northbridge)
(Northbridge + and slower devices like USB, SATA, PCI (Southbridge).
Southbridge) In modern Intel/AMD, Northbridge moved inside the
CPU.

4 BIOS / UEFI ROM Firmware chip. Boot-time hardware initialisation. UEFI

is the modern replacement of legacy BIOS.

5 CMOS Battery Keeps clock & BIOS settings alive when PC is powered
(CR2032) off.

6 PCI-e Slots Insert GPU, sound card, network card, NVMe adapters.
x1, x4, x8, x16 lane widths.

7 SATA Connectors Attach HDDs / SSDs / DVD drives.

8 M.2 Slot NVMe SSD or Wi-Fi card slot — very fast PCIe-based
storage.

9 24-pin ATX Power Main power connector from PSU. Additional 4/8-pin
CPU power.

10 Rear I/O Panel USB (Type-A, Type-C), HDMI, DisplayPort, Ethernet

(RJ45), audio jacks, PS/2.

11 Voltage Regulator Step-down PSU voltages to precise CPU/RAM voltages

Modules (VRM) (e.g., 1.2 V).

12 System Bus Copper tracks — physical wires that carry data,

(traces on PCB) address & control signals.

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 4.4 Form Factors
Motherboard sizes standardize kiye gaye hain taaki cabinets easily fit ho
sakein:
• ATX — 305 × 244 mm — full-size desktop
• Micro-ATX — 244 × 244 mm — compact desktop
• Mini-ITX — 170 × 170 mm — small form factor / HTPC
• E-ATX — 305 × 330 mm — workstations, dual CPU

♪ VIVA / INTERVIEW
Q: Northbridge aur Southbridge mein kya difference hai?
A: Northbridge fast components (CPU, RAM, GPU) ko handle karta hai.
Southbridge slow components (USB, SATA, PCI, LAN) ko handle karta
hai. Modern CPUs mein Northbridge functionality CPU ke andar aa gaya
hai — jise "System Agent" bola jaata hai.

✎ PYQ / EXAM QUESTION

Q. (RGPV 2020 · 5 marks) Draw the layout of a typical desktop
motherboard and label its important components.

◈ QUICK SUMMARY
Chapter 1–4 mein humne dekha: COA = Architecture (what) +
Organization (how). Computer 5 units (Input, Output, Memory, ALU,
CU) se bana hota hai. Von Neumann single memory use karta hai;
Harvard alag alag data & instruction memory use karta hai. Motherboard
sab components ko physically connect karta hai; PSU/SMPS power supply

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karta hai. Memory hierarchy fast+small (registers, cache) se lekar
bada+slow (HDD, tape) tak jaati hai.

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Chapter 5 — CPU Organization:
Internal Structure & Working

5.1 CPU Kya Hai?

★ DEFINITION
CPU (Central Processing Unit) aka Processor / Microprocessor, is the
"brain" of a computer. It performs three fundamental tasks: Fetch
(memory se instruction laao), Decode (samjho kya karna hai), Execute
(kar do). Modern CPUs also add Store/Write-back as a 4th stage.

◆ REAL-LIFE ANALOGY
Analogy — Cricket Match (cricket)
• Umpire (Control Unit) = kis over mein kaun bowl karega, kis batsman
ka number hai, ye sab coordinate karta hai
• Batsman/Bowler (ALU) = actual playing action perform karta hai
• Scoreboard (Registers) = current runs, wickets, over ki information hold
karta hai
• Pitch (CPU internal bus) = jahaan sab action hota hai
• Ground boundary (I/O ports) = bahar ke world se connection

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 5.2 CPU Ke Andar Kya Hai?

Figure 5.1 — Detailed Internal Architecture of a CPU

Modern CPU ke 4 main sub-systems:

1. Register File — Fast internal storage (few bytes to KB). Types explained
in Ch 6.
2. ALU (Arithmetic Logic Unit) — Actual calculation ka kaam (Ch 8).
3. Control Unit (CU) — Decode + control signals generate (Ch 14).
4. Bus Interface Unit (BIU) + Cache — External memory ke saath data
movement.

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 5.3 Working of the CPU — Step by Step
Isko humare cricket analogy se aage badhaate hain. Har clock cycle mein CPU
yeh kaam karta hai:
1. Fetch: PC (Program Counter) ka address MAR mein jaata hai, memory se
instruction MDR mein aati hai, IR mein transfer hoti hai. PC increment ho
jaata hai.
2. Decode: CU IR mein rakhi instruction ka opcode field padhta hai aur decide
karta hai kaun se control signals send karne hain.
3. Operand Fetch: Instruction ke operands (register/memory) se values read
hoti hain.
4. Execute: ALU actual operation karta hai (jaise ADD, SUB, AND).
5. Write-back: Result destination (register/memory) mein store hota hai.
Flags update hote hain.
Yeh cycle indefinitely repeat hoti hai jab tak HALT instruction ya interrupt aa
jaaye.

5.4 CPU Speed Aur Performance Metrics

∑ FORMULA / RULE
Clock Speed (Frequency): f = 1 / T
where T = clock period (seconds)
CPI (Cycles Per Instruction): average clock cycles ek
instruction complete karne ke liye
MIPS = (Clock rate) / (CPI × 10⁶) → Millions of Instructions
Per Second

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Execution Time = (Instruction Count × CPI) / Clock rate

▶ SOLVED EXAMPLE
Example 5.1: A CPU has clock rate 2 GHz aur CPI = 4. Program mein 10⁸
instructions hain. Execution time nikaalo aur MIPS nikaalo.
Solution:
Execution Time = (10⁸ × 4) / (2 × 10⁹) = 4 × 10⁸ / 2 × 10⁹ = 0.2 sec
MIPS = 2 × 10⁹ / (4 × 10⁶) = 500 MIPS

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Chapter 6 — CPU Registers
Explained

6.1 Register Kya Hai?

★ DEFINITION
Register = A very small, extremely fast storage location inside the CPU,
typically 8, 16, 32 or 64 bits wide, built out of D-flip-flops or SRAM cells.
Har register ka ek specific purpose hota hai.

Why so fast? Because registers are literally sitting next to the ALU inside the
CPU die. No bus travel needed. Access time is essentially zero clock cycles (or
1 cycle).

6.2 The Main Registers — Ek Ek Kar Ke

1. Program Counter (PC)
• Purpose: Hold the address of the next instruction to be fetched.
• Size: Same as address bus width (16 / 32 / 64-bit).
• Auto behaviour: After each instruction fetch, PC ← PC + 1 (or +4 in byte-
addressable 32-bit machines).
• Modified by: JMP, CALL, RET, branch, interrupts.

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2. Instruction Register (IR)
• Purpose: Hold the current instruction that CU is decoding.
• CU ke input jaate hain isi IR ke bits.

3. Memory Address Register (MAR)

• Purpose: Holds the address at which memory read/write will happen.
• MAR always sends its content on the Address Bus.

4. Memory Data Register (MDR) / Memory Buffer Register

(MBR)
• Purpose: Holds the data being sent to or received from memory.
• Data Bus se connect hota hai. Bidirectional.

► STICKY-NOTE TIP
Memory access pair — MAR + MDR:
Read : MDR ← M[MAR]
Write: M[MAR] ← MDR

5. Accumulator (ACC / A)
• Purpose: Default operand and destination for ALU. "Everything goes through
it" in accumulator-based CPUs (8085, 6502).
• ADD B → means A ← A + B

6. Status / Flag Register (SR / PSW)

Bits jinme ALU result ke bare mein extra info hoti hai — jaise "result zero hua
kya?", "carry aayi kya?" etc.

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 Flag Symbol Set When

Zero Z ALU result = 0

Carry C Unsigned overflow / carry out of MSB

Sign / S / N MSB of result = 1 (negative in signed)

Negative

Overflow V / O Signed overflow (two operands same sign, result

different sign)

Parity P Even number of 1s in result

Auxiliary Carry AC Carry from bit 3 to bit 4 (BCD)

Interrupt I Interrupts allowed

Enable

7. General Purpose Registers (GPRs)

• Purpose: Programmer ke liye scratch-pad. Kisi bhi purpose ke liye use ho
sakte hain.
• Naming: R0–R7 (8085/8086), R0–R15 (ARM), $0–$31 (MIPS), RAX–R15
(x86-64).
• Number: RISC CPUs mein 32+, CISC mein 8-16.

8. Stack Pointer (SP)

Points to the top of the stack in memory. Push/Pop ke saath auto-modify hota
hai.

9. Base / Index / Segment Registers

Address calculation ke liye special helpers. Jaise x86 mein CS, DS, ES, SS.

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10. Control Word Register
Microprogrammed CU mein current microinstruction hold karta hai; control
signals is register ke bits se derive hote hain (Ch 14 mein detail).

❖ MEMORY TRICK
Registers Mnemonic — "PIMMASF" ♪
P – Program Counter
I – Instruction Reg
M – MAR
M – MDR
A – Accumulator
S – Status/SR
F – Flags & GPRs
Yaad karo: "Padho Ise Mehnat se, Marks Aayenge Sahi Fatafat!"

✎ PYQ / EXAM QUESTION

Q. (RGPV 2018 · 10 marks) Explain in detail the functions of the
following registers with diagrams: PC, IR, MAR, MDR, ACC and Flag
register.

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Chapter 7 — Stack Organization:
PUSH · POP · CALL · RETURN

7.1 Stack Kya Hai?

★ DEFINITION
Stack: A special memory area (or set of registers) that operates on the
LIFO (Last-In-First-Out) principle. Jo cheez sabse last mein daali gayi,
wo sabse pehle nikalti hai.

◆ REAL-LIFE ANALOGY
Analogy — Plate stack in canteen (plate): Canteen mein plates ek
dusre ke upar rakhi hoti hain. Aap sabse upar wali plate hi utha sakte ho,
sabse neeche wali direct nahi. Aur naya plate hamesha sabse upar
rakhoge. Yehi LIFO hai.

7.2 Types of Stack

• Register Stack — Fixed set of internal CPU registers arranged as stack
(very fast, limited size).
• Memory Stack — A portion of main memory reserved as stack, tracked by
SP (Stack Pointer). Ye zyada common hai — desktop PCs mein.

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 7.3 Basic Stack Operations

Figure 7.1 — PUSH aur POP operation visualisation (stack grows upward)

PUSH (Insert)

∑ FORMULA / RULE
PUSH DATA
SP ← SP + 1
M[SP] ← DATA
if SP = FULL then STACK-FULL ← 1

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POP (Delete/Read)

∑ FORMULA / RULE
POP DATA
DATA ← M[SP]
SP ← SP − 1
if SP = EMPTY then STACK-EMPTY ← 1

► STICKY-NOTE TIP
Real machines mein stack usually downward grow karta hai (x86, ARM).
So PUSH → SP ← SP−4, POP → SP ← SP+4. Diagram mein upward
dikhaya humne, concept same hai.

7.4 CALL & RETURN Instructions

Function/procedure call ke time CPU ko yaad rakhna hota hai ki main function
pe kahaan wapas aana hai. Iske liye stack use hota hai.

∑ FORMULA / RULE
CALL <subroutine-address>
SP ← SP − 1
M[SP] ← PC // return address save
PC ← subroutine-address

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 RETURN
PC ← M[SP]
SP ← SP + 1

7.5 Interrupt Handling with Stack

Interrupt bhi ek "unexpected call" jaisa hi hai — jab peripheral CPU ka
attention chahta hai (keyboard press, timer tick), CPU:
1. Current instruction complete karta hai
2. PC + PSW (flags) ko stack pe push karta hai
3. Interrupt Service Routine (ISR) ke address pe jump
4. ISR execute karta hai
5. IRET (return-from-interrupt) → PC + PSW ko stack se pop → main
program continue

7.6 Reverse Polish Notation & Stack

Stack ka ek famous use — expression evaluate karna in postfix notation
(RPN).

▶ SOLVED EXAMPLE
Example 7.1: Evaluate the postfix expression 2 3 + 5 * using a stack.
Solution:
1. Push 2 → Stack: [2]
2. Push 3 → Stack: [2, 3]
3. See '+' → pop 3, 2 → push (2+3)=5 → Stack: [5]
4. Push 5 → Stack: [5, 5]

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5. See '*' → pop 5, 5 → push (5*5)=25 → Stack: [25]
Final answer = 25

✎ PYQ / EXAM QUESTION

Q. (RGPV 2019 · 5 marks) What is a stack? Explain PUSH and POP
operations with diagrams and register transfer statements.
Q. (RGPV 2022 · 5 marks) Evaluate the following expression using stack:
(A + B) * (C − D) / E

♪ VIVA / INTERVIEW
Q: Kya stack overflow real problem hai?
A: Haan — infinite recursion ya deep function nesting stack ko fill kar
deti hai. OS process ko crash kar deta hai. Programmers "tail-call
optimization" ya iterative approach se avoid karte hain.

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Chapter 8 — Arithmetic Logic Unit
(ALU)

8.1 Definition
★ DEFINITION
ALU: The combinational digital circuit inside the CPU that carries out
arithmetic (+, −, ×, ÷), logical (AND, OR, XOR, NOT), shift (SHL, SHR),
and compare (CMP) operations on binary data. Result output ke saath
status flags update karta hai.

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 Figure 8.1 — ALU Block Diagram

8.2 ALU Ke Inputs Aur Outputs

Signal Direction Purpose

Operand A (n bits) Input First operand

Operand B (n bits) Input Second operand

Function-select / Op-code (k bits) Input Which operation to perform

Carry-in Input Initial carry (for chained adder)

Result F (n bits) Output Answer of operation

Flags (Z, C, N, V, P) Output Extra info about result

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 8.3 Arithmetic Operations
Simplest ALU ka core = Adder. Sab kuch adder ke around banaya jaata hai:
• Addition: Full-adders chained → Ripple Carry Adder / CLA (Carry-
Lookahead Adder).
• Subtraction: A − B = A + (~B) + 1 = A + 2's-complement(B).
• Multiplication: Shift & add hardware (or Booth's Algorithm — Module 2
mein).
• Division: Restoring / Non-restoring algorithms (Module 2 mein).
• Increment / Decrement: A + 1, A − 1 (special hardware).

8.4 Logical Operations

Bit-wise operations. Har bit ke liye truth-table:

A B AND OR XOR NAND NOR XNOR

0 0 0 0 0 1 1 1

0 1 0 1 1 1 0 0

1 0 0 1 1 1 0 0

1 1 1 1 0 0 0 1

► STICKY-NOTE TIP
Real-life use of logical ops:
• AND → masking (specific bits ko 0 karna)
• OR → setting bits (specific bits ko 1 karna)

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• XOR → toggle bits, encryption, parity
• NOT → bit inversion, 1's complement

8.5 Shift Operations

Operation Symbol Meaning Special Use

Logical Shift SHL / All bits move left by 1; MSB Multiply by 2

Left LSL lost; LSB filled by 0

Logical Shift SHR / All bits move right; LSB lost; Divide by 2
Right LSR MSB filled by 0 (unsigned)

Arithmetic Shift ASR Right shift, MSB (sign bit) Divide by 2

Right replicated (signed)

Rotate Left / ROL / Circular shift — bits wrap Encryption, hash

Right ROR around

Rotate through RCL / Bits go via carry flag Multi-precision

Carry RCR arithmetic

▶ SOLVED EXAMPLE
Example 8.1: Perform SHL on 8-bit value 0101 1011 .
Answer: 1011 0110 . MSB (0) was shifted out; new LSB = 0.
Decimal check: 91 × 2 = 182 ✓

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 8.6 Compare (CMP)
CMP A, B is basically A − B but result is discarded. Only flags update hote
hain. Then a conditional branch (JZ, JC, JN, etc.) uses these flags.

8.7 Overflow & Carry

Yeh do concepts confusion cause karte hain — clear kar dete hain:

Carry Flag (C) Overflow Flag (V/O)

• Set when carry-out of MSB • Set when signed result exceeds
during unsigned addition (or n-bit signed range
borrow during subtraction) • Detection: Cin ⊕ Cout of MSB
• Meaningful for unsigned = 1
arithmetic • Or: Two operands same sign,
• Example: 1111 + 0001 = 10000 → result different sign
C=1 • Example (4-bit): 0111 + 0001 =
1000 → +7 + 1 ≠ −8 → V=1

⚠ COMMON MISTAKE
× Beginners often say "carry aa gayi to overflow ho gayi". Wrong! Ye do
alag concepts hain. Unsigned mein sirf Carry matter karta hai; Signed
mein sirf Overflow matter karta hai. Dono independently set/clear ho
sakte hain.

▶ SOLVED EXAMPLE

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Example 8.2 (4-bit): Add 0110 (+6) and 0101 (+5)
Result = 1011 → binary 11 → interpreted as signed = −5. Overflow
occurred!
Reason: +6 + +5 = +11, but 4-bit signed range is −8 to +7 → cannot
represent.
Cin to MSB = 1, Cout from MSB = 0 → 1 ⊕ 0 = 1 → V=1 ✓

✎ PYQ / EXAM QUESTION

Q. (RGPV 2020 · 5 marks) Draw the block diagram of ALU. Explain how
ALU performs arithmetic and logical operations. Distinguish between Carry
and Overflow.

♪ VIVA / INTERVIEW
Q: ALU is combinational or sequential?
A: Purely combinational — it has no memory. Registers (which feed
ALU) are sequential.

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Chapter 9 — Instruction &
Instruction Cycle

9.1 Instruction Kya Hoti Hai?

★ DEFINITION
Instruction: A binary encoded command that tells the CPU which
operation to perform on which operands. Ek instruction typically 16-64
bits ki hoti hai. Machine ka native language.

Har instruction 2 main parts se banti hai:

1. Opcode field — What to do (ADD, SUB, MOV, JMP...)
2. Operand field(s) — On what data (register / memory / immediate)

9.2 Types of Instructions

Category Examples Purpose

Data Transfer MOV, LOAD, STORE, PUSH, Move data between registers/
POP, XCHG memory

Arithmetic ADD, SUB, MUL, DIV, INC, Numeric operations

DEC, NEG

Logical

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 AND, OR, NOT, XOR, CMP, Bit-wise operations,
TEST comparisons

Shift / Rotate SHL, SHR, ROL, ROR, RCL, Bit shifting

RCR

Control Transfer JMP, CALL, RET, INT, IRET, Change flow of execution
LOOP

Conditional JZ, JC, JNE, JG, JL Flag-based branching

Branch

I/O IN, OUT Port-based I/O (isolated I/O)

Machine Control HLT, NOP, CLI, STI, WAIT CPU state control

9.3 The Instruction Cycle (Fetch-Decode-

Execute)
Ye COA ka heart hai — is topic ke bina COA khatam nahi ho sakti. Iski
flowchart bahut baar exam mein aati hai.

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COA MODULE 1 | Page 45 of 103
 Figure 9.1 — Complete Instruction Cycle Flowchart

Detailed Steps with RTL

Step 1 — FETCH

T0: MAR ← PC
T1: MDR ← M[MAR]; PC ← PC + 1
T2: IR ← MDR

Step 2 — DECODE

T3: Decoder analyzes IR[opcode field]

Control Unit generates control signals

Step 3 — OPERAND FETCH

Depends on addressing mode:

If immediate : operand already in IR
If direct : MAR ← IR[address]; MDR ← M[MAR]
If register : read from register file

Step 4 — EXECUTE

ALU performs operation:

ADD: ACC ← ACC + MDR
SUB: ACC ← ACC − MDR
AND: ACC ← ACC ∧ MDR
etc.
Update flag register

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Step 5 — STORE / WRITE-BACK

Result stored back to register or memory.

Then cycle repeats from FETCH.

► STICKY-NOTE TIP
Basic accumulator machine mein 5-7 T-states lagti hain per instruction.
Modern pipelined CPUs mein multiple instructions overlap ho jaate hain —
ek instruction average 1 cycle mein complete ho sakti hai (CPI ≈ 1 or
less).

Figure 9.2 — Fetch Phase Timing Diagram with RTL

✎ PYQ / EXAM QUESTION

Q. (RGPV 2021 · 10 marks) Draw the flowchart of Instruction Cycle.
Explain each step with proper Register Transfer statements.

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Chapter 10 — Instruction Formats

10.1 Definition
★ DEFINITION
Instruction Format: The layout of bits in a machine instruction,
specifying opcode, operand addresses, addressing mode, and other fields.

Different CPU designers alag-alag formats use karte hain. Common categories:

Figure 10.1 — Common Instruction Formats

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 10.2 Address-Field Based Classification
Three-Address Instruction

ADD R1, R2, R3 // R1 ← R2 + R3

Format: | OPCODE | DEST | SRC1 | SRC2 |

Pros: readable, no extra MOV needed. Cons: instruction size bada, memory
zyada.

Two-Address Instruction

ADD R1, R2 // R1 ← R1 + R2 (destination = one of sources)

Format: | OPCODE | DEST/SRC1 | SRC2 |

x86 uses this heavily. Compact than 3-address but destructive (overwrites
source).

One-Address Instruction (Accumulator-based)

ADD B // ACC ← ACC + B (ACC is implicit)

Format: | OPCODE | ADDRESS |

Old 8085, 6502 used this. Compact, but everything through ACC =
performance bottleneck.

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Zero-Address Instruction (Stack-based)

ADD // pop top-2 from stack, push result

Format: | OPCODE |

Used by Java Virtual Machine (JVM) & HP 3000. Very compact but slower.

10.3 Comparison Example — Evaluate Y = (A +

B) × (C − D)
Format Code Instr. Count

3-Address 3
ADD R1, A, B
SUB R2, C, D
MUL Y, R1, R2

2-Address 6
MOV R1, A
ADD R1, B
MOV R2, C
SUB R2, D
MUL R1, R2
MOV Y, R1

1-Address 7
LOAD A
ADD B
STORE T
LOAD C

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 SUB D
MUL T
STORE Y

0-Address (Stack) 8
PUSH A
PUSH B
ADD
PUSH C
PUSH D
SUB
MUL
POP Y

► STICKY-NOTE TIP
Trade-off: More addresses = fewer instructions but larger each. Less
addresses = smaller instructions but more of them. That's why RISC
prefers 3-address (fixed 32-bit) while stack machines minimise
instruction size.

10.4 MIPS R-Type, I-Type, J-Type (Modern

RISC Formats)
Type Layout (32-bit) Use

R- op(6) | rs(5) | rt(5) | rd(5) | Register-register ALU ops

Type shamt(5) | funct(6)

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I- op(6) | rs(5) | rt(5) | immediate(16) Immediate ALU, load/store,
Type branch

J- op(6) | address(26) Unconditional jump

Type

✎ PYQ / EXAM QUESTION

Q. (RGPV 2019 · 10 marks) Explain the different instruction formats with
suitable examples. Evaluate X = (A+B) * (C+D) using 0, 1, 2, and 3-
address instructions.

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Chapter 11 — Bus Organization

11.1 Bus Kya Hai?

★ DEFINITION
Bus: A shared set of parallel electrical wires (usually etched on the
motherboard or inside a chip) that carries information between two or
more devices. Ek "highway" analogy fit hoti hai.

◆ REAL-LIFE ANALOGY
Analogy — City Traffic (signal)
• Address Bus = "House number/pin-code" batata hai (kis address pe
bhejna hai)
• Data Bus = "Truck load" (actual data being transported)
• Control Bus = "Traffic signals + horn" (permission, direction, timing)

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 11.2 Three Kinds of Buses

Figure 11.1 — System Bus = Address + Data + Control

Bus Direction Width (typical) Signals

Address Uni-directional (CPU 16 / 32 / Address lines only

Bus → Memory/IO) 64-bit

Data Bus Bi-directional 8 / 16 / 32 / Actual data being read/

64-bit written

Control Bi-directional 10–20 lines READ, WRITE, MREQ,

Bus IORQ, INT, RESET, CLK,
etc.

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 11.3 Bus Width vs Performance
∑ FORMULA / RULE

Addressable Memory = 2n locations (where n = address bus

width)
Data Transfer Rate = Bus Width × Clock Frequency

▶ SOLVED EXAMPLE
Example 11.1: A CPU has 32-bit address bus. How much memory can it
address?
Ans: 2³² = 4,294,967,296 = 4 GB (byte-addressable)

▶ SOLVED EXAMPLE
Example 11.2: 64-bit data bus running at 800 MHz. What is the peak
transfer rate?
Ans: 64 bits × 800 × 10⁶ = 51,200 × 10⁶ bits/s = 6.4 GB/s

11.4 Types of System Bus Organization

1. Single-bus organization — All devices share one common bus. Simple,
cheap, but slow (only one transaction at a time).
2. Two-bus organization — Separate memory bus & I/O bus. Faster.
3. Three-bus organization — Additional dedicated bus (say, for DMA).
Complex, expensive.

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 11.5 Bus Timing — Synchronous vs
Asynchronous

Synchronous Bus Asynchronous Bus

• Uses a common clock signal • No common clock — uses
• All transactions in fixed clock handshake signals (REQ, ACK)
cycles • Works with devices of different
• Simple, fast (if all devices are speeds
same speed) • Complex, slightly slower
• Example: PCI, DDR • Example: USB, PCIe (partial)

11.6 Bus Arbitration

When multiple devices want to use the bus (e.g., CPU + DMA controller +
GPU), bus arbiter decides who gets access. Three schemes:
1. Daisy Chaining — Priority = physical position on chain.
2. Polling — Arbiter checks each device in turn.
3. Independent Request — Each device has separate REQ/GNT lines.

✎ PYQ / EXAM QUESTION

Q. (RGPV 2020 · 5 marks) What is a bus? Explain the three types of
buses. If a CPU has 20-bit address bus, calculate maximum memory it
can address.
Ans: 2²⁰ = 1,048,576 bytes = 1 MB

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Chapter 12 — Register Transfer
Language (RTL)

12.1 Definition
★ DEFINITION
RTL: A symbolic notation used to describe the flow of data between CPU
registers, memory and ALU during instruction execution. It's the "pseudo-
code" of hardware.

◆ REAL-LIFE ANALOGY
Analogy: RTL is like a musical score for a symphony. Just as sheet music
tells each instrument when to play what, RTL tells each register when to
load, and each bus when to carry data.

12.2 RTL Symbols & Syntax

Symbol Meaning Example

← Transfer (assignment) R1 ← R2

M[addr] Memory location at 'addr' MDR ← M[MAR]

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 : Conditional (control function) T0: R1 ← R2

, Parallel operation R1 ← R2, R3 ← R4

+ − × ÷ Arithmetic R1 ← R2 + R3

∧∨⊕ ~ Logical AND OR XOR NOT R1 ← R2 ∧ R3

shl / shr Shift left / right R1 ← shl(R1)

12.3 Micro-operations
Ek instruction ka execution multiple micro-operations mein tuta jaata hai.
Each micro-operation is one RTL statement executable in one clock cycle.

Types of Micro-operations
1. Register Transfer — R1 ← R2
2. Arithmetic — R1 ← R1 + R2
3. Logical — R1 ← R1 ∨ R2
4. Shift — R1 ← shl R1

12.4 Control Function

∑ FORMULA / RULE
General Form: P: R_dest ← f(R_src)
where P is a Boolean control condition that must be TRUE for
the transfer to happen in the current clock.

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Example: T2·q₁: R1 ← R2 means "if we are in time-state T2 AND q1 flag is 1,
then copy R2 into R1."

12.5 Complete Fetch Cycle in RTL

∑ FORMULA / RULE
Fetch phase:
T0: MAR ← PC
T1: MDR ← M[MAR], PC ← PC + 1
T2: IR ← MDR

12.6 Solved RTL Example — ADD Instruction

▶ SOLVED EXAMPLE
Q: Write RTL for the instruction ADD R1, R2 (i.e., R1 ← R1 + R2) in a
2-bus accumulator-based CPU.
Solution:
T0: MAR ← PC
T1: MDR ← M[MAR], PC ← PC + 1
T2: IR ← MDR
T3: DECODE(IR)
T4: Y ← R2 // second operand goes to ALU input latch Y
T5: Z ← R1 + Y // ALU output goes to Z
T6: R1 ← Z // write back

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✎ PYQ / EXAM QUESTION
Q. (RGPV 2018 · 10 marks) Write the Register Transfer sequence for
fetching and executing the following instructions:
(a) ADD R1, R2
(b) LDA 200 (load from memory address 200 into ACC)
(c) STA 300 (store ACC to memory address 300)

♪ VIVA / INTERVIEW
Q: RTL aur assembly language mein farak?
A: Assembly language programmer ke liye hai (readable). RTL hardware
designer ke liye hai — data path level pe describe karta hai.

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Chapter 13 — Addressing Modes

13.1 What & Why?

★ DEFINITION
Addressing Mode: The rule/technique used to specify where the actual
data (operand) is located for an instruction. Different modes give
programmers flexibility to write efficient code (loops, arrays, pointers,
etc.).

◆ REAL-LIFE ANALOGY
Analogy — Courier Delivery (pkg): Aap ek courier bhejna chahte ho, but
recipient ka address different tareeko se de sakte ho:
• "Package inside envelope" → Immediate
• "House number 500, Bhopal" → Direct
• "Look at diary; page says the real address" → Indirect
• "Give it to person X (already known)" → Register
• "Base + 100 meters east" → Indexed
Every mode has its own use-case.

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 13.2 Visual Summary

Figure 13.1 — The Nine Common Addressing Modes

13.3 Detailed Discussion of Each Mode

1. Immediate Addressing
• Operand is part of the instruction itself (embedded).
• Fastest — no memory / register access needed for operand.
• Syntax: MOV R1, #50 → R1 ← 50
• Use case: loading constants (initial values, counters).

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2. Direct (Absolute) Addressing
• Instruction contains the full memory address of the operand.
• Syntax: MOV R1, [500] → R1 ← M[500]
• One memory access needed. Simple but limited address range.

3. Indirect Addressing
• Instruction contains address of a pointer which holds the actual address.
• Syntax: MOV R1, [[500]] → R1 ← M[M[500]]
• Two memory accesses. Useful for pointer/tree traversal.

4. Register Addressing
• Operand is in a CPU register.
• Syntax: MOV R1, R2 → R1 ← R2
• Extremely fast — no memory access.

5. Register Indirect Addressing

• Register holds the address of the operand.
• Syntax: MOV R1, [R2] → R1 ← M[R2]
• Very common for pointers in C.

6. Indexed Addressing
• Effective Address (EA) = Base Address (in register/const) + Index
Register.
• Syntax: MOV R1, [R2 + 100] → R1 ← M[R2 + 100]
• Perfect for arrays: R2 = array base, index changes each loop iteration.

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7. Relative Addressing
• EA = PC + offset. Used by branches.
• Syntax: JMP +8 → PC ← PC + 8
• Makes code position-independent (relocatable).

8. Auto-Increment
• Like register indirect, but register auto-increments after use.
• Syntax: MOV R1, [R2]+ → R1 ← M[R2]; then R2 ← R2 + 1 (or +size).
• Ideal for sequential array traversal.

9. Auto-Decrement
• Register auto-decrements before use.
• Syntax: MOV R1, -[R2] → R2 ← R2 − 1; then R1 ← M[R2].
• Perfect for stack operations (grow downward).

13.4 Comparison Table (VERY Important —

likely 5/10-mark Q)
Effective
Mode Memory accesses Speed Best Use
Address (EA)

Immediate — 0 (operand in Fastest Constants

instruction)

Direct Address in 1 Fast Global variables

instruction

Indirect 2 Slow Pointers, tables

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 M[Address in
instr]

Register — 0 (register) Fastest Temporary

variables

Register Contents of 1 Fast C-style pointers

Indirect register

Indexed Base + Index 1 Fast Arrays, matrix

Relative PC + offset 0 (for jump) Fast Branch, position-

indep. code

Auto- Reg; then 1 Fast Sequential arrays

Increment Reg++

Auto- Reg--; then 1 Fast Stack, reverse

Decrement Reg traversal

13.5 Solved Numericals on Addressing Modes

▶ SOLVED EXAMPLE
Example 13.1: Suppose memory content:
M[500] = 800, M[800] = 1200, M[900] = 400
Register: R1 = 500, R2 = 100, PC = 200, Accumulator ACC = ?
Instruction: LOAD 500
Solutions for different addressing modes:

Mode EA ACC ←

Immediate — 500 (operand is 500 itself)

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 Direct 500 M[500] = 800

Indirect M[500] = 800 M[800] = 1200

Register (R1) — R1 = 500

Register Indirect (R1) R1 = 500 M[500] = 800

Indexed (500 + R2) 500 + 100 = 600 M[600] = (assume 250)

Relative (PC + 500) 200 + 500 = 700 M[700] = (assume 60)

▶ SOLVED EXAMPLE
Example 13.2 (RGPV 2019 PYQ style): A 2-byte instruction stored at
memory location 250 in the format: | opcode(1B) | offset(1B) |. Opcode
is LDA and offset = 40. PC = 252 (after fetch), R1 = 100.
Calculate EA in each mode:
(a) Immediate → operand = 40
(b) Direct → EA = 40 → operand = M[40]
(c) Register Indirect (via R1) → EA = 100 → operand = M[100]
(d) Relative → EA = PC + 40 = 252 + 40 = 292 → operand = M[292]
(e) Indexed (base 40, R1 as index) → EA = 40 + 100 = 140 → operand =
M[140]

✎ PYQ / EXAM QUESTION

Q. (RGPV 2021 · 10 marks) Explain any six addressing modes with
example. A memory-referenced instruction contains address 250. Register
R1 contains 400. Memory content M[250] = 500, M[400] = 700, M[500]

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= 800. Find effective address and operand for immediate, direct, indirect,
register, register indirect and indexed addressing modes.

❖ MEMORY TRICK
Memory Trick — "I DIRR IRAA":
I – Immediate
D – Direct
I – Indirect
R – Register
R – Register Indirect
I – Indexed
R – Relative
A – Auto-increment
A – Auto-decrement
Yaad kar lo: "I DIRR IRAA — 9 modes, easy A"

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Chapter 14 — Control Unit:
Hardwired vs Microprogrammed

14.1 Control Unit Kya Karta Hai?

★ DEFINITION
Control Unit (CU): The part of the CPU that directs the operation of the
processor. It fetches instructions, decodes them, and generates the
sequence of control signals needed for the datapath (ALU, registers,
buses, memory) to execute those instructions correctly.

◆ REAL-LIFE ANALOGY
Analogy — Orchestra Conductor (music): A symphony has violinists,
drummers, pianists (=ALU, registers, memory), but without a conductor
everyone plays randomly. The conductor's baton (=control signals) tells
each musician when to start, stop, and how loud to play. Similarly, CU
sends control signals at each clock tick to coordinate the CPU internals.

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 14.2 Two Design Approaches

Figure 14.1 — Hardwired vs Microprogrammed Control Unit

14.3 Hardwired Control Unit

★ DEFINITION
CU is implemented as a combinational logic circuit (gates, flip-flops,
decoders, counters) that directly generates control signals. Inputs:
instruction opcode + timing signal + flag bits. Output: fixed pattern of
control signals.

Components of Hardwired CU
• Instruction Register (IR) — Holds current instruction
• Instruction Decoder — Decodes opcode
• State (Timing) Counter — Generates T0, T1, T2, … time states

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 • Combinational Circuit — Boolean equations mapping (opcode + T-state)
→ control signals

Working (Step by Step)

1. Instruction fetched into IR.
2. Decoder decodes the opcode into a one-hot signal.
3. Timing counter increments each clock, activating T0, T1, T2, ...
4. Combinational logic ANDs (opcode signal) with (T-state) to produce
control signals.
5. Control signals drive datapath.

Advantages
• » Fastest — direct hardware logic, no memory lookup.
• Ideal for RISC machines (small instruction set).

Disadvantages
• Very difficult to modify (new instruction ⇒ redesign gates).
• Complex design for large instruction sets.
• Debugging tough — no software layer.

14.4 Microprogrammed Control Unit

★ DEFINITION
CU stores control signals as microinstructions in a special "Control
Memory" (usually a ROM). Sequences of microinstructions form a
microprogram for each machine instruction. CU acts like a "mini-CPU
inside CPU".

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 Invented by Maurice Wilkes (1951).

Terminology

Term Meaning

Microinstruction Set of control signals for one clock cycle (each bit
= one control line)

Microprogram Sequence of microinstructions implementing one

machine instruction

Control Memory (CM) ROM/RAM storing microinstructions

Control Address Register Points to next microinstruction (like PC)

(CAR)

Control Buffer Register Holds microinstruction currently read

(CBR)

Sequencer / µPC Determines next CAR value (branch, jump in

microprogram)

Mapping Logic Converts opcode → starting address in control

memory

Working
1. Machine instruction fetched → opcode extracted.
2. Mapping logic converts opcode → CAR = start address of microprogram.
3. Microinstruction from CM loaded into CBR.
4. Control signals emitted; datapath executes one step.
5. Sequencer computes next CAR (usually CAR+1, sometimes branch).

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6. Repeat until microprogram ends → next machine instruction fetch.

Advantages
• Very flexible — new instruction = new microcode (no gate redesign).
• Easier to design and debug for complex ISAs (CISC).
• Can emulate other machines (e.g., IBM System/360 famously used this).

Disadvantages
• Slower than hardwired (each cycle involves a memory read).
• Requires extra hardware (Control Memory).
• More power consumption.

14.5 Types of Microinstruction Format

1. Horizontal Microinstruction — Wide word (100s of bits), one bit per
control signal. Fast, more parallelism, but very wide memory required.
2. Vertical Microinstruction — Narrow word, encoded control signals need
decoder. Compact memory, but slower (extra decode step).
3. Diagonal / Nano-programming — Compromise. Two-level: micro → nano
ROM.

14.6 Hardwired vs Microprogrammed —

Comparison Table
# Feature Hardwired CU Microprogrammed CU

1 Implementation Fixed logic (gates, FFs, Control memory + µPC

counters)

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2 Speed Very fast Slower (memory lookup)

3 Flexibility Rigid — hardware Flexible — just modify

change needed microcode

4 Design cost High for large ISA Low even for complex ISA

5 Best for RISC processors CISC processors

6 Debugging Difficult Easier (change firmware)

7 Chip area / Less More (control memory)

power

8 Examples MIPS, ARM Cortex-A, Intel x86 (many gens), IBM

RISC-V S/360, VAX

✎ PYQ / EXAM QUESTION

Q. (RGPV 2020, 2022 · 10 marks) What is a control unit? Explain
hardwired and microprogrammed control unit with block diagram. Compare
them on any 6 parameters.

♪ VIVA / INTERVIEW
Q1: Why RISC prefers hardwired?
A: RISC has few, simple, fixed-length instructions — hardwired logic is
fast and easy for such ISA. Speed matters more than flexibility.
Q2: Modern Intel/AMD CPUs — are they hardwired or microprogrammed?
A: Hybrid. Simple instructions decode via hardwired paths; complex CISC
instructions break into µops using microcode. Best of both worlds.

COA MODULE 1 | Page 73 of 103

⚠ COMMON MISTAKE
× Common confusion: "Microprogrammed CU has microprocessor inside."
Wrong. Microprogramming is just a technique — CU internally uses a
small ROM + counter, not a full microprocessor.

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Chapter 15 — 30+ Solved Numericals
& RTL Problems
Har problem ka format: Concept · Formula · Step-by-step · Shortcut ·
Common mistake.

15.1 CPU Performance & MIPS

▶ SOLVED EXAMPLE
N1. Clock = 1 GHz, CPI = 5, Instructions = 10⁷. Find execution time and
MIPS.
Formula: T = (IC × CPI) / f ; MIPS = f / (CPI × 10⁶)
Step: T = (10⁷ × 5) / (10⁹) = 0.05 sec. MIPS = 10⁹ / (5×10⁶) = 200.
Ans: Execution time = 50 ms, MIPS = 200
Shortcut: MIPS = f(GHz) × 1000 / CPI

▶ SOLVED EXAMPLE
N2. A CPU runs at 2 GHz. Program takes 3 × 10⁹ clock cycles. Find
execution time.
Ans: T = 3×10⁹ / 2×10⁹ = 1.5 sec

▶ SOLVED EXAMPLE

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N3. Program A: 500 million instrs, avg CPI 4, clock 2 GHz. Program B:
800 million instrs, avg CPI 2, clock 2 GHz. Which is faster?
TA = 5×10⁸ × 4 / 2×10⁹ = 1.0 sec

TB = 8×10⁸ × 2 / 2×10⁹ = 0.8 sec

B is faster.
Common mistake: "Zyada instructions = slow" — nahi, CPI aur clock bhi
matter karta hai.

15.2 Bus & Memory

▶ SOLVED EXAMPLE
N4. A CPU has 24-bit address bus, 16-bit data bus. Max addressable
memory?
2²⁴ = 16,777,216 = 16 MB (byte-addressable). If 16-bit word addressed, 16
MW = 32 MB.

▶ SOLVED EXAMPLE
N5. Bus: 64-bit wide @ 1600 MT/s (transfers/sec). Peak bandwidth?
= 64 × 1.6 × 10⁹ / 8 = 12.8 GB/s ✓ (matches DDR3-1600)

▶ SOLVED EXAMPLE
N6. If address bus width doubles from 20 to 40 bits, how many times
memory grows?
2⁴⁰ / 2²⁰ = 2²⁰ = 1,048,576× (1 M times bigger — from 1 MB to 1 TB!)

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15.3 Instruction Cycle & RTL
▶ SOLVED EXAMPLE
N7. Write RTL for the machine instruction LDA 350 (load ACC from
memory 350) in single-bus organization.

T0: MAR ← PC
T1: MDR ← M[MAR], PC ← PC + 1
T2: IR ← MDR
T3: MAR ← IR[address] ; = 350
T4: MDR ← M[MAR] ; read value at 350
T5: ACC ← MDR

▶ SOLVED EXAMPLE
N8. Write RTL for STA 400 (store ACC to memory 400).

T0-T2: fetch (same as above)

T3: MAR ← IR[address] ; 400
T4: MDR ← ACC
T5: M[MAR] ← MDR

▶ SOLVED EXAMPLE
N9. Write RTL for ADD R1, R2 .

T0-T2: fetch
T3: Y ← R2

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 T4: Z ← R1 + Y
T5: R1 ← Z

▶ SOLVED EXAMPLE
N10. Write RTL for JMP 500 .

T0-T2: fetch
T3: PC ← IR[address] ; = 500

▶ SOLVED EXAMPLE
N11. Write RTL for BRZ label (branch if zero flag set).

T0-T2: fetch
T3: If (Z=1) then PC ← IR[address]

15.4 Addressing Modes Numericals

▶ SOLVED EXAMPLE
N12. Memory: M[100]=500, M[500]=800, M[800]=200.
Registers: R1 = 500, R2 = 200. PC = 400. Instruction has address field =
100.
Find operand for each mode:

Mode EA Operand

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 Immediate — 100

Direct 100 M[100]=500

Indirect M[100]=500 M[500]=800

Register (R1) — R1=500

Register Indirect (R1) 500 M[500]=800

Indexed (100+R2) 100+200=300 M[300] (given?)

Relative (PC+100) 400+100=500 M[500]=800

▶ SOLVED EXAMPLE
N13. Auto-increment mode: R2 = 500 initially, M[500] = 90, M[501] =
55.
Execute MOV R1, [R2]+ twice. Show R1 and R2 after each execution.
Step 1: R1 ← M[500] = 90, then R2 = 501.
Step 2: R1 ← M[501] = 55, then R2 = 502.

15.5 Instruction Format Encoding

▶ SOLVED EXAMPLE
N14. A CPU uses 32-bit instruction format: 8-bit opcode, 4-bit
addressing mode, 8-bit register field, 12-bit address. How many:
(a) distinct opcodes possible? = 2⁸ = 256
(b) addressing modes? = 2⁴ = 16

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(c) registers addressable? = 2⁸ = 256
(d) directly addressable memory? = 2¹² = 4096 bytes = 4 KB

▶ SOLVED EXAMPLE
N15. A machine has 60 different instructions and 5-bit opcode. Can it
accommodate all?
Ans: 2⁵ = 32 < 60 → Not enough bits. Minimum bits = ⌈log₂60⌉ = 6.

▶ SOLVED EXAMPLE
N16. If a CPU has 16 GPRs, how many bits needed to encode a register
operand?
Ans: log₂16 = 4 bits

15.6 Number Systems & Flags

▶ SOLVED EXAMPLE
N17. Add 4-bit signed: 0101 + 0011.
= 1000. In signed, +5 + +3 = +8; but 4-bit signed max = +7 →
OVERFLOW = 1.
Cin to MSB = 1, Cout = 0 → 1 ⊕ 0 = 1 → V = 1.

▶ SOLVED EXAMPLE

COA MODULE 1 | Page 80 of 103

N18. Add 4-bit unsigned: 1010 + 0111.
= (1)0001. Carry = 1, Sum = 0001. Unsigned: 10 + 7 = 17 > 15 → C = 1
valid answer 17.

▶ SOLVED EXAMPLE
N19. Compute flags after CMP 30, 30 (unsigned 8-bit).
30 − 30 = 0. Flags: Z = 1, C = 0, N = 0, V = 0.

15.7 Stack & Expression Evaluation

▶ SOLVED EXAMPLE
N20. Convert infix (A + B) × (C − D) to postfix and evaluate with
stack.
Postfix: A B + C D − ×
Stack trace: push A → [A]; push B → [A,B]; '+' → pop → push (A+B);
push C, D; '−' → push (C−D); '×' → push ((A+B)×(C−D)). Final answer
on top.

▶ SOLVED EXAMPLE
N21. Evaluate 5 1 2 + 4 * + 3 − using stack.
Push 5 → [5]; push 1 → [5,1]; push 2 → [5,1,2]; '+' → [5,3]; push 4 →
[5,3,4]; '*' → [5,12]; '+' → [17]; push 3 → [17,3]; '−' → [14]. Answer: 14

▶ SOLVED EXAMPLE

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N22. Stack initial SP=1000, entries M[1000]=A, M[999]=B (grows down).
Execute PUSH C . New state?
SP ← SP − 1 = 999. Wait — 999 is already occupied. Correct sequence for
downward stack: SP ← SP − 1 = 999, M[SP] ← C. But 999 was B.
Convention: SP points to top. Actually top is 999. So POP pop B (SP
becomes 1000). Then push C: SP ← SP − 1 = 999, M[999] ← C. Details
depend on ISA.

15.8 Register Transfer with Buses

▶ SOLVED EXAMPLE
N23. Single-bus CPU: transfer R2 to R5. Write RTL.
Bus ← R2; R5 ← Bus (needs 2 cycles because single bus).

▶ SOLVED EXAMPLE
N24. Two-bus CPU: perform R1 ← R2 + R3.
BusA ← R2; BusB ← R3; ALU-out ← BusA + BusB; R1 ← ALU-out — can be
done in 1 or 2 cycles.

▶ SOLVED EXAMPLE
N25. Three-bus CPU can do R1 ← R2 + R3 in ONE clock cycle: sources
on 2 buses, ALU computes, result on 3rd bus into R1 same cycle.

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15.9 Control Unit & Microprogram
▶ SOLVED EXAMPLE
N26. Control memory: 4096 words × 32 bits. What is the CAR width?
log₂4096 = 12 bits.

▶ SOLVED EXAMPLE
N27. If a microinstruction is horizontally encoded with 60 control signals,
minimum bit-width?
60 bits (one per signal). Vertical encoded: log₂60 = 6 bits (if 60
mutually exclusive) — but signals lose parallelism.

▶ SOLVED EXAMPLE
N28. Machine has 128 machine instructions, each averaging 4
microinstructions. Total microprogram memory?
128 × 4 = 512 microinstructions minimum. If each is 40 bits, 512 × 40 =
20,480 bits = 2.5 KB control memory.

15.10 Instruction Cycle Time

▶ SOLVED EXAMPLE
N29. Fetch 4 cycles + Decode 1 + Execute 3 + Store 2 = 10 clock cycles
per instruction. At 1 GHz clock, one instruction = 10 ns. Instructions/sec
= 10⁸ = 100 MIPS.

COA MODULE 1 | Page 83 of 103

▶ SOLVED EXAMPLE
N30. ALU delay 4 ns, register access 1 ns, decoder 2 ns. Cycle time min
= max delay = 4 ns. Max clock frequency = 1/4ns = 250 MHz.

15.11 Mixed / Advanced

▶ SOLVED EXAMPLE
N31. A processor has separate 32-bit IR field: 6-bit opcode, 3-bit
addressing mode, 5-bit register, 18-bit displacement. What's the max
directly-jumpable range (relative)?
18-bit signed = −131072 to +131071 bytes = ±128 KB.

▶ SOLVED EXAMPLE
N32. 8-bit CPU (Reg width 8). Add unsigned 200 + 100.
Binary: 11001000 + 01100100 = (1)00101100. Sum register = 00101100 = 44.
Carry = 1.
Real 300 exceeds 255. Answer wraps around. C flag set.

► STICKY-NOTE TIP
Ye 30 numericals aap zaroor practice karo — RGPV Autonomous paper
mein 40% weightage inhi jaise questions ka aata hai. Har question ka
RTL/Formula-first approach follow karo.

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Chapter 16 — Exam Corner:
2/5/10/15 Mark Question Bank

16.1 Two-Mark Questions (Direct Definitions)

1. Define Computer Architecture and Computer Organization.
2. What is the difference between architecture and organization?
3. List any four registers of a CPU with their function.
4. Define ALU. Name any four operations it performs.
5. What is a bus? Name three types of buses.
6. Define instruction cycle.
7. What is the difference between opcode and operand?
8. List the flags in a status register.
9. What is RTL? Give one example.
10. What is stack? Explain LIFO.
11. Define addressing mode. Name any 4 modes.
12. Define control unit.
13. What is a microinstruction?
14. Differentiate direct and indirect addressing.
15. What is the role of PC and IR?
16. What is bus width? Its significance?
17. Define von Neumann architecture.
18. What is DMA? (short intro; detailed in Module 3)
19. Difference between CISC and RISC (intro).

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20. What is CMOS battery on motherboard?

16.2 Five-Mark Questions

1. Distinguish between Computer Architecture and Organization (min. 6
points).
2. Draw block diagram of a general-purpose computer and describe each unit.
3. Compare Von Neumann and Harvard architectures.
4. Explain the function of registers PC, IR, MAR, MDR, ACC, and Flag register.
5. Explain PUSH and POP operations of stack with diagram and RTL.
6. Explain the difference between Carry and Overflow flags with examples.
7. Describe the Instruction Cycle with a flowchart.
8. Explain any six addressing modes with example.
9. What is bus arbitration? Explain daisy chaining.
10. Draw the layout of a desktop motherboard and label its parts.

16.3 Ten-Mark Questions

1. Explain the complete internal architecture of a CPU with a neat block
diagram. Discuss the role of each block.
2. Explain in detail — with block diagram, working, advantages, disadvantages,
and comparison — Hardwired vs Microprogrammed Control Unit.
3. Explain the different instruction formats (0, 1, 2, 3-address). Evaluate
Y = (A + B) × (C − D) using each format.
4. Explain all nine addressing modes with syntax, effective-address calculation
and example program.
5. Write the Register Transfer sequence for fetching and executing (a) ADD
R1, R2 (b) LDA 200 (c) STA 300 (d) BRZ 500.

COA MODULE 1 | Page 86 of 103

6. Discuss stack organization. Explain PUSH, POP, CALL, RETURN. Give an
example of postfix expression evaluation using stack.
7. Describe the ALU in detail — arithmetic, logical, shift and compare
operations. Explain overflow and carry generation with examples.

16.4 Fifteen-Mark Questions (Long Answers /

Full-Length)
1. Explain the complete Von Neumann model of a computer. Describe the
block diagram, functional units, buses, and instruction cycle. Extend the
discussion to explain how a modern desktop CPU differs in organization.
2. Compare and contrast Hardwired and Microprogrammed control units in
detail. Describe the complete microprogrammed CU with mapping logic,
CAR, CBR, control memory, and sequencer. Explain horizontal vs vertical
microinstruction encoding with examples.
3. Design a small hypothetical CPU: define its instruction format (op-code,
address, mode bits), list its addressing modes, and write RTL for any 5
instructions.

16.5 Model Question Paper (30 marks, 90 min)

Section A — 5×2 = 10 marks (any five)
1. Define computer organization.
2. State function of MAR and MDR.
3. Compare carry and overflow.
4. What is a microinstruction?
5. Give RTL for PUSH.
6. Define bus width.

Section B — 2×5 = 10 marks (any two)

COA MODULE 1 | Page 87 of 103

 1. Distinguish organization vs architecture (any 6 points).
2. Explain PUSH, POP, CALL, RETURN with RTL.
3. Six addressing modes with examples.

Section C — 1×10 = 10 marks

1. Explain Instruction Cycle with flowchart + RTL for fetch/decode/execute of ADD instru

COA MODULE 1 | Page 88 of 103

Chapter 17 — Viva & Interview
Question Bank (60+ Qs)
Section A — Basic Concept
1. Q: Architecture aur Organization mein difference?
A: Architecture = What (visible to programmer). Organization = How
(hardware detail).
2. Q: Motherboard kis kaam aata hai?
A: Sab hardware components ko connect kar ke electrical/data paths
provide karta hai.
3. Q: Von Neumann aur Harvard architecture mein farak?
A: Von Neumann — single memory both for data + instructions. Harvard —
separate.
4. Q: Kya modern PCs pure Von Neumann hain?
A: Nahi — cache levels internally Harvard hote hain (separate I-cache, D-
cache).
5. Q: ROM aur RAM mein 3 farak?
A: RAM volatile, read/write, main memory. ROM non-volatile, mostly read,
firmware storage.

Section B — CPU & Registers

1. PC ka role kya hai? → Next instruction ka address rakhna.
2. MAR aur MDR ka jodi kaam? → MAR address bhejta hai, MDR data laata/le
jaata hai.
3. Kya PC ka size address bus se related hai? → Haan — usually same width.

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4. ACC ki jagah GPR use karne ka fayda? → Zyada parallelism, kam data
movement.
5. Sign flag aur Overflow flag alag kyun? → Sign = MSB copy (result
negative?), Overflow = signed overflow detect. Alag purposes.
6. Flag register mein kaunse bits store hote hain? → Z, C, N, V, P, AC, I
(interrupt enable) etc.
7. Zero flag kab set hoti hai? → Jab ALU result bilkul 0 ho.
8. Stack Pointer ka size PC jitna hi kyun? → Kyunki dono memory address
point karte hain.

Section C — ALU & Arithmetic

1. ALU combinational hai ya sequential? → Combinational.
2. Subtraction ALU mein kaise hoti hai? → A − B = A + 2's-complement(B).
3. Ripple-carry adder ka limitation? → Delay bahut aata hai carry propagation
ka.
4. Multiplier kaise banate hain? → Shift & add, ya Booth's algorithm.
5. Logical vs Arithmetic shift ka difference? → Logical: 0 fill; Arithmetic: sign
bit copy.

Section D — Instruction Cycle & RTL

1. Fetch phase kitne steps ka hai? → 3 (MAR←PC; MDR←M[MAR], PC++;
IR←MDR).
2. Kya fetch aur decode overlap ho sakte hain? → Haan — pipelining ka basic
idea.
3. RTL kya hai? → Symbolic notation of data flow between registers.
4. Indirect jump ka RTL? → PC ← M[IR[address]].
5. Control function kya hoti hai? → Boolean condition jab true ho tab transfer
hota hai.

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Section E — Instruction Format & Addressing
1. Zero-address instruction stack machine mein hoti hai — kyun? → Operands
top-of-stack se implicit milte hain.
2. 3-address ka fayda? → Fewer instructions, easier compiler codegen.
3. RISC me sirf load/store memory access karti hain — kyun? → Pipeline
simple, uniform cycle time.
4. Indexed addressing kis structure ke liye ideal? → Arrays.
5. Auto-increment kis case mein useful? → Sequential access (array, string).
6. Relative addressing kaise position-independent code deta hai? → EA = PC +
offset, code chahe kahin bhi load ho.

Section F — Bus & Control Unit

1. Address bus unidirectional kyun hoti hai? → CPU always sends address;
devices never write address back.
2. Bus width bandwidth ko kaise affect karti hai? → BW = width × frequency.
3. Kya bahut wide bus bandwidth bada dena easy hai? → Nahi — signal skew,
crosstalk, cost badhta hai.
4. Hardwired CU RISC mein kyun better? → Speed critical, ISA simple aur
fixed.
5. Microprogrammed CU flexible kyun kehte hain? → Firmware update se new
instructions add ho sakti hain.
6. Horizontal microinstruction ki disadvantage? → Bahut wide (100+ bits),
memory zyada chahiye.

Section G — Applications / Practical

1. x86 hardwired hai ya microprogrammed? → Hybrid — hardwired decoder +
microcode for complex instructions.

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2. Kya ARM CPU RISC hai? → Haan — load/store, fixed 32-bit (Thumb has
16-bit) instructions.
3. Kya Java bytecode 0-address hai? → Haan — JVM stack-based.
4. Kya BIOS ROM mein rehta hai? → Haan — flash-EEPROM chip on
motherboard.
5. Ek desktop CPU ke andar kitne physical registers? → 100s (renamed) —
architectural only 16 in x86-64.

Section H — Tricky Questions

1. SP overflow kab hoga? → Deep recursion / infinite pushes without pops.
2. Interrupt aane pe kaunsa register save hota hai stack pe? → PC + PSW
(flags).
3. MDR aur ACC same hain kya? → Bilkul nahi. MDR = memory buffer; ACC
= ALU accumulator.
4. Kya PC read-only hai programmer ke liye? → Some ISAs read-only, others
allow direct load via JMP.
5. Ek 16-bit CPU 4 GB memory address kar sakti hai? → Nahi direct — 2¹⁶ =
64 KB only. Segmentation ya banked memory se extend kar sakte hain.

Section I — Real Systems

1. x86 ISA CISC hai ya RISC? → CISC (variable-length, many addressing
modes).
2. ARM Cortex ISA? → RISC.
3. Intel Core i9 mein L1 cache size? → 32 KB Data + 32 KB Instruction per
core (approx).
4. MIPS R4000 hardwired ya microprogrammed? → Hardwired.
5. Kya modern CPUs single-bus organization use karti hain? → Nahi —
multiple buses (front-side, back-side, ring bus, mesh interconnect).

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Section J — Interview Extras
1. Big-Endian vs Little-Endian samjhao. → MSB first vs LSB first byte
ordering.
2. Kya endianness architecture ka part hai ya organization? → Architecture
(programmer visible).
3. Register file size aur speed mein tradeoff? → Zyada registers → slower
access (more decoders).
4. Kya cache level architecture ka part hai? → Zyada organization — logically
transparent to programmer.
5. Barrel shifter kis kaam aata hai? → n-bit shift in single cycle.
6. Difference between load-store and register-memory architecture? → Load-
store: ALU ops only on regs. Reg-mem (x86): ALU ops can have one
memory operand.
7. Microcode update kya hota hai (real world)? → Intel/AMD ship BIOS
updates to patch CPU bugs (like Spectre) via microcode.
8. Kya assembly language architecture-specific hai? → Haan — har CPU ka
ISA alag hota hai.
9. C compiler ne code likha; wo direct hardware chala sakta hai? → Nahi —
pehle assemble & link hoke machine code banega jo CPU chalayega.
10. Aap agar naya CPU design karo — pehla decision kya hoga? → ISA
(architecture) — kaunse instructions, addressing modes, register file.

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Chapter 18 — Common Mistakes &
Exam Traps
⚠ COMMON MISTAKE
M1. Confusing "Architecture" ↔ "Organization". Fix: Architecture =
programmer-visible; Organization = hardware-visible.

⚠ COMMON MISTAKE
M2. Saying "Carry = Overflow". Fix: Carry — unsigned overflow. Overflow
— signed overflow. Independent flags.

⚠ COMMON MISTAKE
M3. Forgetting PC increments during T1 (parallel with MDR ← M[MAR]).
Fix: Always increment PC during fetch phase — same clock as memory
read.

⚠ COMMON MISTAKE
M4. Writing MAR ← IR[opcode] instead of IR[address]. Fix: MAR gets the
address field of IR, not opcode.

⚠ COMMON MISTAKE

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M5. Mixing up Immediate mode & Direct mode. Fix: Immediate → operand
IS in instruction. Direct → address is in instruction, operand is in memory.

⚠ COMMON MISTAKE
M6. Believing microprogrammed CU is a small microprocessor. Fix: It's a
ROM + counter + decoder — not a full CPU.

⚠ COMMON MISTAKE
M7. Saying stack always grows upward. Fix: In real x86/ARM stack grows
downward (SP decreases on PUSH). Only Morris-Mano textbook diagrams
show upward.

⚠ COMMON MISTAKE
M8. 24-bit address bus → 24 MB memory. WRONG. It's 2²⁴ = 16 MB
(byte).

⚠ COMMON MISTAKE
M9. ROM = permanent, cannot be changed. Fix: EEPROM & Flash are
ROM types but can be electrically erased/updated.

⚠ COMMON MISTAKE
M10. Assuming CPI is always 1. Fix: Real CPUs have CPI varying with
instruction type & memory hits.

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Chapter 19 — Memory Tricks,
Formula & Cheat Sheet

19.1 Memory Tricks (Ratta Marne Ke Liye :))

❖ MEMORY TRICK
M-01. Registers → "PIMMASF": PC · IR · MAR · MDR · ACC · Status ·
Flags.
M-02. Addressing modes → "I DIRR IRAA": Immediate, Direct, Indirect,
Register, Register-Indirect, Indexed, Relative, Auto-Increment, Auto-
Decrement.
M-03. ALU flags → "ZCNVP": Zero, Carry, Negative, oVerflow, Parity.
M-04. Instruction cycle → "FDO-EW": Fetch, Decode, Operand-fetch,
Execute, Write-back.
M-05. Bus types → "ADC": Address, Data, Control.
M-06. CU types → "HM": Hardwired (Fast, Fixed) & Microprogrammed
(Flexible, MEmory-driven).
M-07. Von Neumann → "ONE": ONE memory. Harvard → "TWO"
memories.

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19.2 Formula Sheet
∑ FORMULA / RULE
CPU Performance:
• Clock period T = 1/f
• Execution time = (IC × CPI) / f
• MIPS = f / (CPI × 10⁶)
• MFLOPS = FP_ops / (10⁶ × time)
Memory / Bus:
• Addressable memory = 2ⁿ (n = address bus width)
• Data transfer rate = width × frequency
• Register operand bits = log₂(#registers)
ALU:
• Subtraction: A − B = A + ~B + 1
• Overflow: Cin(MSB) ⊕ Cout(MSB)
• Multiply by 2ⁿ: SHL by n
• Divide by 2ⁿ (signed): ASR by n
Stack:
• PUSH: SP ← SP + 1; M[SP] ← DATA (upward) / SP ← SP − 1;
M[SP] ← DATA (downward)
• POP: DATA ← M[SP]; SP ← SP − 1 (upward) / DATA ←
M[SP]; SP ← SP + 1 (downward)
• CALL: PUSH PC; PC ← target
• RETURN: POP → PC
Fetch RTL:
T0: MAR ← PC

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 T1: MDR ← M[MAR], PC ← PC + 1
T2: IR ← MDR

19.3 Cheat Sheet — All Definitions in One Page

Term One-line Definition

Architecture Programmer-visible attributes (ISA, addressing modes,

registers)

Organization Hardware implementation detail (bus widths, control

signals, memory tech)

Von Neumann Single memory for data + instructions

Harvard Separate memory for data & instructions

CPU Central processing unit — brain of computer

ALU Performs arithmetic + logical + shift + compare

Control Unit Generates control signals for datapath

Register Fast temporary storage inside CPU

PC Program counter — address of next instruction

IR Instruction register — holds current instruction

MAR / MDR Address / Data interface with memory

ACC Accumulator — default ALU operand/destination

Flag Register Stores Z, C, N, V, P bits after ALU operation

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Stack LIFO memory area for saving return address, locals

Instruction Cycle Fetch → Decode → Execute (→ Write back)

Opcode / Operand Operation code / data on which to operate

Bus Shared parallel wires — Address / Data / Control

RTL Register Transfer Language — symbolic hardware data

flow

Micro-operation One-cycle RTL step

Addressing Mode Rule to locate operand

Immediate Operand in instruction

Direct Address in instruction

Indirect Instruction gives address of pointer

Hardwired CU Combinational logic — fast, rigid

Microprogrammed Control memory + µPC — flexible, slower

CU

CISC / RISC Complex/Reduced instruction set computers

COA MODULE 1 | Page 99 of 103

Chapter 20 — Revision Notes (One-
Page & One-Hour)

20.1 One-Page Revision Notes »

◈ QUICK SUMMARY
1. COA = Architecture (WHAT, programmer view) + Organization
(HOW, hardware view).
2. Computer = 5 units: Input · Output · Memory · ALU · Control (last
two = CPU).
3. Von Neumann = 1 memory, Harvard = 2 memories.
4. CPU registers: PC (next instr addr) · IR (current instr) · MAR/MDR
(memory interface) · ACC (ALU default) · Flags (Z/C/N/V/P) · GPRs ·
SP.
5. Stack = LIFO. PUSH: SP±; M[SP]←DATA. POP: DATA←M[SP]; SP∓.
CALL saves PC on stack; RETURN pops it.
6. ALU: Arithmetic (+,−,×,÷) · Logical (AND OR XOR NOT) · Shift ·
Compare. Flags: Carry = unsigned overflow, Overflow = signed overflow
(Cin ⊕ Cout of MSB).
7. Instruction cycle = Fetch → Decode → Execute → Write-back.
Fetch RTL: MAR←PC → MDR←M[MAR], PC++ → IR←MDR.

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 8. Instruction formats: 0-addr (stack) · 1-addr (ACC) · 2-addr
(destructive) · 3-addr (RISC).
9. Bus = Address (uni) + Data (bi) + Control (bi). 2ⁿ locations for n-
bit address bus.
10. RTL notation: R1 ← R2 (transfer). Add ", " for parallel. M[X] =
memory at X.
11. 9 addressing modes: Immediate · Direct · Indirect · Register · Reg-
Indirect · Indexed · Relative · Auto-Inc · Auto-Dec.
12. CU: Hardwired (fast, fixed, RISC) vs Microprogrammed (flexible,
slower, CISC). Microinstruction stored in Control Memory; CAR points to
it; CBR holds it.

20.2 One-Hour Revision Plan ⌚

Time Topic Focus

0–5 min COA introduction Arch vs Org table (6 points)

5–10 Block diagram + Von Diagram + comparison

min Neumann vs Harvard

10–20 CPU registers + Stack PIMMASF trick + PUSH/POP RTL

min

20–30 ALU, Carry vs Overflow Formula + 2 examples

min

30–40 Instruction cycle + RTL Fetch RTL, sample instr RTL

min

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 40–50 Instruction formats + 4 formats + I DIRR IRAA +
min Addressing modes example

50–60 Control unit Hardwired vs Microprogrammed

min table (8 points)

20.3 Last-Minute "Night-Before" Points ◐

1. Architecture = What, Organization = How.
2. Von Neumann = shared memory, Harvard = separate.
3. Registers PIMMASF; know function of each.
4. Fetch = MAR←PC ; MDR←M[MAR], PC++ ; IR←MDR (3 clock cycles).
5. Carry ≠ Overflow.
6. Stack LIFO; PUSH first increments/decrements SP.
7. CALL pushes PC; RETURN pops it.
8. 3-address instructions minimize count; 0-address minimize size.
9. 2ⁿ = memory size for n-bit address bus.
10. Hardwired = fast/rigid; Microprogrammed = slow/flexible.

► STICKY-NOTE TIP
(*) Final Advice: "Diagram + RTL + Table" — teenon ka combination har
answer mein daalne se professor impressed hoke full marks dene ko
majboor ho jaayega. All the best!

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 ★ End of Module 1 ★
Module 2 (Computer Arithmetic) coming next in follow-up request!

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