ARM Cortex Processors

Contents
• Introduction to ARM CORTEX series,
• improvement over classical series and advantages for
embedded system design.
• CORTEX A, CORTEX M, CORTEX R processors series,
versions, features and applications.
• Need of operating system in developing complex
applications in embedded system,
• desired features of operating system & hardware support
from processor,
• Firmware development using CMSIS standard for ARM
Cortex.
• Survey of CORTEX M3 based controllers, its features and
comparison.
•
ARM_Archit
ecture_Ove
[Link]

Single instruction, multiple data (SIMD)

04/01/19 [Link] VIIT,Pune

definitive_guide.pdf
fig 1.2
definitive_guide.pdf
fig 1.3
• Focused on small memory system devices such as
microcontrollers and reducing the size of the
processor, the Cortex-M3 supports only the
Thumb-2 (and traditional Thumb) instruction set.
• Instead of using ARM instructions for some
operations, as in traditional ARM processors,
it uses the Thumb-2 instruction set for all
operations.
As a result, the Cortex-M3 processor is not
backward compatible with traditional
•
•
•
•
•
•
•
•
definitive_guide.pdf
• fig 1.4

• The Relationship between the Thumb Instruction

Set in Thumb-2 Technology and the Traditional
Thumb
• A Profile (ARMv7-A): Application processors which
are designed to handle complex applications
such as high-end embedded operating systems
(OSs) (e.g., Symbian, Linux, and Windows
Embedded).
• These processors requiring the
– highest processing power,
– virtual memory system support with memory
management units (MMUs),
– enhanced Java support
– secure program execution environment.
• Example products include high-end mobile phones
and electronic wallets for financial transactions.
• R Profile (ARMv7-R):
• Real-time, high-performance processors
targeted primarily at the higher end of the
real time market
• Applications, such as
• high-end breaking systems
• hard drive controllers, in which high
processing power and high reliability are
essential and for which low latency is
important.
• M Profile (ARMv7-M):
• Processors targeting low-cost applications in
which
– processing efficiency is important
– Low cost
– Less power consumption,
– low interrupt latency,
– ease of use are critical,
• Industrial control applications, including
real-time control systems
Multi-Thread mode
 Thread mode
• Thread mode is the normal mode that programs run in.
• Thread mode is entered on reset and normally on return
from an exception.
• Thread mode can be privileged or unprivileged software
execution.
 Handler mode
• Handler mode is the mode that exceptions are
handled in.

• It is always privileged software execution,

therefore the core will automatically switch to
Privileged mode when exceptions occur.
 Nested vector interrupt control
• NVIC is a method of prioritizing interrupts, improving
the MCU’s performance and reducing interrupt
latency.
• NVIC also provides implementation schemes for
handling interrupts that occur when other interrupts
are being executed or when the CPU is in the
process of restoring its previous state and resuming
its suspended process.
• NVIC is to ensure that higher priority interrupts are
completed before lower-priority interrupts, even if the
lower-priority interrupt is triggered first.
• For example, if a lower-priority interrupt is being
registered* or executed and a higher-priority interrupt
occurs, the CPU will stop the lower-priority interrupt and
process the higher-priority one first
 Normal interrupt – back to back
traditional systems would repeat the complete state save and
restore cycle twice, resulting in higher latency.
 tail-chaining technology in the NVIC
• Tail-chaining achieves much lower latency by replacing serial
stack pop and push actions that normally take over 42 clock
cycles with a simple 6 cycle instruction fetch.

• The processor state is automatically saved on interrupt entry,

and restored on interrupt exit, in fewer cycles than a software
implementation, thus significantly enhancing performance
LOW ISR first, then high priority
 High prio ISR first, then low priority
NVIC abandons a stack Pop if an exception arrives and
services the new interrupt immediately as shown below. By
pre-empting and switching to the second interrupt without
completing the state restore and save, the NVIC achieves
lower latency in a deterministic manner.
 ARM CORTEX series feature
• Advanced 3 stage pipeline
• Harvard architecture
• Branch speculation (prediction)
• Two operating modes (Thread & Handler)
• single cycle multiply and hardware divide (1.25
DMIPS/MHz)
• Thumb®-2 instruction set architecture
• Nested Vectored Interrupt Controller (NVIC)
• Integrated debug and trace
• Memory Protection Unit (MPU)
• bus matrix and interfaces
 Contd….
• unaligned data storage and atomic bit
manipulation
• Working smarter to sleep longer
• RTOS kernel in hardware (SysTick)
• Migrating from banked shadow based
exception model stack based exception
model
• Power management through NVIC
• Memory protection unit (MPU)
•
•
 Improvement over classical series
Architectural Block ARM Classic Series Cortex
Core ARM9-ARM11 Cortex M3/M4
Instruction Tightly coupled memory Yes No

Data Tightly Coupled memory Yes No

Cache Yes No
Co-Processor Yes No
System Controller Yes Yes
MMU Yes No
MPU Yes Yes
Debug Yes Yes
Write Buffer Yes

System Timer No Yes

Nested Vectored interrupt No Yes
Controller
 Classical Series Cortex M3/M4

Processor 1. User 1. Thread

modes 2. Handler
2. Supervisor

3. System

4. Undefined

5. Abort

6. FIQ

7. IRQ
Privilege Other than user , all the modes are 1. Thread mode will be in privileged and
access privileged can be changed to unprivileged by
writing in to control register

2. Handler will always be privileged

Stack 1. you have separate stack for each of 1. main stack

the modes(user and system have the 2. Process stack
same)
 Contd…….Exception Handling
Classical series Cortex M3/M4

Exceptions 1. Reset 1. Reset

2. Data Abort 2. Non Maskable Interrupt

3. Prefetch abort 3. Hard Fault

4. FIQ 4. Memory management

5. IRQ 5. Bus fault

6. Undefined Instruction6. Usage fault

7. SWI 7. System service call

8. Debug Monitor
9. Pending request for system
service(Pend SV)
10. Systick
11. External interrupt( uart,timer,rtc etc)
 Other comparison points
Classical Series Cortex M3/M4

Selection of A bit in register1 BIGEND configuration signal

endianess of coprocessor (external pin)is sampled during reset
(Big or Little 15
Endian) Determines the
endianess
Status registers CPSR and SPSR APSR
IPSR
EPSR
All the three embedded in a single register called as XPSR

Special Registers ------ [Link]

FAULT MASK
BASE PRI
CONTROLFirst three is used for disabling of exceptions
[Link] is used for stack and access (privileged or non
privileged)selection

MPU Enabling and size Separate set of registers are available

is defined in
coprocessor
Pipeline stages 5-8 3
 Classical series Cortex M3/M4

Vector location It can be at 0x00000000 It can be at 0x00000000

(low vector) Or Or
0x00000080 to 0x3FFFFF80,
0xFFFFFFFF (High
Offset has to be specified in the
vector)
vector table offset register
stack Stack can be It is always full descending
full ascending
full descending
Empty ascending
Empty descending
Exception entry Typically R4-R12 and LR XPSR, PC,R0,R1,R2,R3,
will be pushed to the R12, LR
stack
 Advantages for embedded system design
• Greater performance efficiency
• Low power consumption
• Enhanced determinism
• Improved code density
• Ease of use
• Lower cost solutions
• Wide choice of development tools
• Nonmaskable interrupts for critical tasks
• highly deterministic nested vector interrupts
………………………………………….etc
Comparison table for cortex A,R,M

1. [Link]
cortex-a-cortex-r-and-cortex-m-1/?
2. [Link]
06/[Link]
3. Difference between Cortex-A, Cortex-R and
Cortex-M Tenet Technetronics'
[Link]
Need of operating system for complex
application
Basic need ?
Further need…….
•File system organization,
• network communication,
• network management,
• database management,
•user-interface graphics, etc
 Desired features of operating system and
Hardware support from processor
1. Clock support
2. Real time priority levels
3. Fast task preemption
4. Predicted and fast interrupt latency
5. Support for resource sharing among tasks
6. Support for memory management/protection
7. Support for asynchronous I/O
………………………………….ETC
• With a significant amount of hardware components
being identical, a large portion of the Hardware
Abstraction Layer (HAL) can be identical.
• The latest study of the development for the
embedded market shows that software complexity
and cost will increase over time
 Interfacing of CORTEX based microcontrollers using
CMSIS
• ARM has recognized that after solving the diversity
issue on the hardware side, there is still a need to
create a standard to access these hardware
components.
• CMSIS; a framework to be extended by vendors,
– a common API (Application Programming
Interface) for core specific components and
conventions
– Easy reuse of code or develop new code for ARM
Cortex-M based devices.
 Cortex Microcontroller Software
Interface Standard (CMSIS)
• a vendor-independent Hardware Abstraction
Layer (HAL) for microcontrollers that are based
on Arm® Cortex® processors.
• It defines generic tool interfaces and enables
consistent device support.
• Its software interfaces
✔ simplify software re-use,
✔ reduce the learning curve for microcontroller
developers,
✔ improve time to market for new devices.
 Cortex Microcontroller Software
Interface Standard (CMSIS)
• It provides interfaces to
✔ processor and peripherals,
✔ real-time operating systems,
✔ middleware components.
• It includes a delivery mechanism for
✔ devices,
✔ boards,
✔ software
• It enables the combination of software
components from multiple vendors.
 Target
CMSIS-... Description
Processors
Standardized API for the Cortex-M
processor core and peripherals.
All Cortex-M,
Core(M) Includes intrinsic functions for
SecurCore
Cortex-M4/M7/M33/M35P SIMD
instructions.
Standardized API and basic run-time
Cortex-A5/A7/
Core(A) system for the Cortex-A5/A7/A9
A9
processor core and peripherals.
Generic peripheral driver interfaces for
middleware. Connects microcontroller
peripherals with middleware that
Driver All Cortex
implements for example
communication stacks, file systems, or
graphic user interfaces.
CMSIS-...
Target Processors Description
DSP library collection with over 60
Functions for various data types:
fixed-point (fractional q7, q15, q31) and
DSP All Cortex-M single precision floating-point (32-bit).
Implementations optimized for the SIMD
instruction set are available for
Cortex-M4/M7/M33/M35P.
Collection of efficient neural network
kernels developed to maximize the
NN All Cortex-M
performance and minimize the memory
footprint on Cortex-M processor cores.
Common API for real-time operating
systems along with a reference
Cortex-M0/M0+/
RTOS v1 implementation based on RTX. It
M3/M4/M7
enables software components that can
work across multiple RTOS systems.
CMSIS-.. Target
Description
. Processors
Extends CMSIS-RTOS v1 with
All Cortex-M, Armv8-M support, dynamic object
RTOS
Cortex-A5/A creation, provisions for multi-core
v2
7/A9 systems, binary compatible
interface.
Describes a delivery mechanism
All Cortex-M, for software components, device
SecurCore, parameters, and evaluation board
Pack
Cortex-A5/A support. It simplifies software
7/A9 re-use and product life-cycle
management (PLM).
Peripheral description of a device
All Cortex-M, that can be used to create
SVD
SecurCore peripheral awareness in debuggers
CMSIS- Target
Description
... Processors
Firmware for a debug unit
DAP All Cortex that interfaces to the
CoreSight Debug Access Port.
Defines methods to describe
system resources and to
Zone All Cortex partition these resources into
multiple projects and
execution areas.
 Core Peripheral Access Layer (CPAL)
• The lowest level
• defines addresses,
• access methods for common components and
functionality that exists in every Cortex-M system.
• Access to core registers, NVIC, debug subsystem is
provided by this layer.
• Tool specific access to special purpose registers
(e.g. CONTROL, xPSR), will be provided in the form
of inline functions or compiler intrinsics.
• This layer will be provided by ARM.
 Middleware Access Layer (MWAL)
• This layer is also defined by ARM,
• Will be adapted by silicon vendors for their
respective devices.
• The Middleware Access Layer defines a common
API for accessing peripherals.
• The Middleware Access Layer is still under
development.
Device Peripheral Access Layer (DPAL)
• Hardware register addresses and other definitions,
as well as device specific access functions will be
defined in this layer.
• The Device Peripheral Access Layer is very similar to
the Core Peripheral Access Layer and will be
provided by the silicon vendor.
• Access methods provided by CPAL may be
referenced and the vector table will be adapted to
include device specific exception handler address.