Embedded processor – Unit 1-
part 1
1
ARM architecture
2
Registers
• General-purpose registers hold
either data or an address.
• They are identified with the letter r
prefixed to the register number.
For example, register 4 is given the
label r4.
• All the registers shown are 32 bits
in size.
• There are up to 18 active registers:
16 data registers and 2 processor
status registers.
• The data registers are visible to the
programmer as r0 to r15.
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Registers continue…
• The ARM processor has
three registers assigned
to a particular task or
special function: r13,
r14, and r15.
• Register r13 is
traditionally used as the
stack pointer (sp) and
stores the head of the
stack in the current
processor mode.
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Registers continue
• Stack is a reserved area of memory used to temporarily store data. During
an interrupt, the CPU automatically stores the return address of the
currently executing program on the stack so that execution can resume
after the interrupt service routine (ISR) finishes. The stack is also used to
store register values, local variables, and function return addresses.
• Stack Pointer (SP) is a special CPU register that holds the address of the
top of the stack. During a PUSH operation, the stack pointer is updated
and the data is written to the stack. During a POP operation, the data is
read from the stack and the stack pointer is updated accordingly.
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Registers continue
• Register r14 is called the link register (lr) and is where the
core puts the return address whenever it calls a subroutine.
• Register r15 is the program counter (pc) and contains the
address of the next instruction to be fetched by the
processor.
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Registers continue
• Depending upon the context, registers r13 and r14 can also be used as
general-purpose registers, which can be particularly useful since these
registers are banked during a processor mode change (note: ARM
processor can operate in seven operating modes).
• However, it is dangerous to use r13 as a general register when the
processor is running any form of operating system because operating
systems often assume that r13 always points to a valid stack frame.
• In ARM state the registers r0 to r13 are orthogonal—any instruction that
you can apply to r0 you can equally well apply to any of the other registers
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Registers continue
• In addition to the 16 data registers, there are
two program status registers: cpsr and spsr
(the current and saved program status
registers, respectively).
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Current Program Status Register (cpsr
register)
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Cpsr register continue…
• The ARM core uses the cpsr to monitor and control internal operations.
• The cpsr is a dedicated 32-bit register and resides in the register file.
• Figure shows the basic layout of a generic program status register. Note
that the shaded parts are reserved for future expansion.
• The cpsr is divided into four fields, each 8 bits wide: flags, status,
extension, and control.
• In current designs the extension and status fields are reserved for future
use.
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Cpsr register continue…
• The control field contains the processor mode, state, and
interrupt mask bits. The flags field contains the condition
flags.
• Some ARM processor cores have extra bits allocated. For
example, the J bit, which can be found in the flags field, is
only available on Jazelle-enabled processors, which execute 8-
bit instructions.
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ARM memory organization
• In addition to the processor register state, an
ARM system has memory state. Memory may be
viewed as a linear array of bytes numbered from
zero up to 2³²-1.
• Data items may be 8-bit bytes, 16-bit half-words
or 32-bit words.
• The 'little-endian‘ is the standard memory
organization used by the ARM.
• ARM can also be configured to work with a 'big-
endian' memory organization.
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ARM “little-endian” memory
organization
• In addition to the processor
register state, an ARM system has
memory state. Memory may be
viewed as a linear array of bytes
numbered from zero up to 2³²-l.
• Data items may be 8-bit bytes,
16-bit half-words or 32-bit words.
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ARM “little-endian” continue…
• In little-endian memory
organization, the Least Significant
Byte (LSB) of a multi-byte data
item is stored at the lowest
memory address, and the Most
Significant Byte (MSB) is stored at
the highest memory address.
• The memory organization is
illustrated in Figure. This shows a
small area of memory where each
byte location has a unique
number.
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ARM “little-endian” continue…
• A byte may occupy any of these
locations.
• A word-sized data item must
occupy a group of four byte
locations starting at a byte
address which is a multiple of
four.
• Half-words occupy two byte
locations starting at an even byte
address.
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ARM “little-endian” continue…
• The ‘little-endian’ is the
standard, memory
organization used by
the ARM.
• ARM can also be
configured to work with
a 'big-endian' memory
organization
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Big-endian memory organization?
• In Big-endian memory
organization, the Least
Significant Byte (LSB) of a
multi-byte data item is
stored at the highest
memory address, and the
Most Significant Byte (MSB)
is stored at the lowest
memory address.
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ARM “little-endian” Vs Big-endian
memory organization
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ARM memory organization continue…
• Embedded systems often use multiple memory devices. It is usually necessary
to have a method to help organize these devices and protect the system from
applications trying to make inappropriate accesses to hardware. This is
achieved with the assistance of memory management hardware.
• ARM cores have three different types of memory management hardware—no
extensions providing no protection, a memory protection unit (MPU)
providing limited protection, and a memory management unit (MMU)
providing full protection.
• Non-protected memory is fixed and provides very little flexibility. It is normally
used for small, simple embedded systems that require no protection from
rogue applications.
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ARM memory organization continue…
• Memory protection units (MPUs) employ a simple system
that uses a limited number of memory regions. These regions
are controlled with a set of special coprocessor registers, and
each region is defined with specific access permissions.
• This type of memory management is used for systems that
require memory protection but don’t have a complex
memory map.
Memory management unit (MMU):
MMUs are the most comprehensive memory management
hardware available on the
ARM.
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ARM Processor Modes
• There are seven processor modes in total.
• Each processor mode is either privileged or
nonprivileged mode.
• A privileged mode allows full read-write access to the
cpsr. Conversely, a nonprivileged mode only allows
read access to the control field in the cpsr but still
allows read-write access to the condition flags.
• Six privileged modes (abort, fast interrupt
request, interrupt request, supervisor, system, and
undefined) and one nonprivileged mode (user)
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ARM Processor Modes ..continue
• The processor enters abort mode when there is a failed attempt to access
memory.
• Fast interrupt request and interrupt request modes correspond to the two
interrupt levels available on the ARM processor.
• Supervisor mode is the mode that the processor is in after reset and is
generally the mode that an operating system kernel operates in.
• System mode is a special version of user mode that allows full read-write
access to the cpsr.
• Undefined mode is used when the processor encounters an instruction that is
undefined or not supported by the implementation.
• User mode is used for programs and applications.
Note: Every processor mode except user mode can change mode by writing
directly to the mode bits of the cpsr.
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Banked registers
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Banked registers…continue
• Figure shows all 37 registers in the register file. Of those, 20 registers are
hidden from a program at different times. These registers are called
banked registers and are identified by the shading in the diagram. They
are available only when the processor is in a particular mode; for
example, abort mode has banked registers r13_abt, r14_abt and
spsr_abt.
• If you change processor mode, a banked register from the new mode will
replace an existing register.
• Figure (in the next page) also shows a new register appearing in interrupt
request mode: the saved program status register (spsr), which stores the
previous mode’s cpsr. You can see in the diagram the cpsr being copied
into spsr_irq.
• To return back to user mode, a special return instruction is used that
instructs the core to restore the original cpsr from the spsr_irq and bank
in the user registers r13 and r14.
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Saved program status register (spsr)?
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Processor mode
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Addressing modes in ARM
What is addressing modes?
The CPU can access data in various ways. The data could be in
a register, or in memory, or be provided as an immediate
value. These various ways of accessing data are called
addressing modes.
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Addressing modes in ARM…continue
Various addressing mode supported by the ARM7TDMI processor
include the following:
• Immediate addressing mode
• Register addressing mode
• Register indirect addressing mode
• Base Indexed Indirect Addressing Mode (also called Register Offset
Addressing Mode)
• Base with Scaled Index Indirect Addressing Mode
• Register Indirect with Offset Addressing Mode (also called pre-indexed
addressing mode)
• Pre-indexed addressing mode with auto-indexing
• Post-indexed addressing mode
• Program counter (PC)-relative addressing mode
• Multiple Register Addressing Mode
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Immediate Addressing Mode
• In Immediate addressing mode, the data is given directly in
the instruction. Note that the immediate data must be
preceded by the pound sign, “#”.
• This addressing mode can be used to load information into
any registers.
Examples:
MOV r0, #25 ; Moves or copy the immediate value 25 into
register R0
ADD r3, r3,#1 ; Adds the immediate value 1 to the contents of
R3 and stores the result back in R3 (i.e., increments R3 by 1).
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Register Addressing Mode
• In this addressing mode, the operand is stored
in a register.
Examples:
MOV r1, r2 ; copy the content of r2 into r1
ADD r0, r1, r2 ; r0 = r1+r2
SUB r7, r5, r3 ; r7 = r5- r3 (i.e., subtracts the contents of R3 from
R5 and stores the result in R7).
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Register Indirect Addressing Mode
• In this addressing mode, the register contains
the memory address of the operand.
Examples:
LDR r0, [r1] ; Loads the data from the memory location whose
address is stored in r1 into r0
STR r0, [r1] ; Stores the data from r0 into the memory location
whose address is stored in r1
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Base Indexed Indirect Addressing Mode (also called Register
Offset Addressing Mode)
• In Base Indexed Indirect Addressing Mode, the effective memory
address is obtained by adding the contents of an index register to
the contents of a base register. The resulting address is then used
to access memory.
Syntax:
LDR rd, [rn, rm]
where:
Rn = Base register
Rm = Index (offset) register
Rd = Destination register
Example:
LDR r0, [r1, r2];
Meaning: Loads the data from the memory location whose address is
(R1 + R2) into R0.
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Base with Scaled Index Indirect Addressing Mode
• In Base with Scaled Index Indirect Addressing Mode, the effective memory
address is calculated by adding a shifted (scaled) index register to the base
register. The resulting address is then used to access memory.
Syntax:
LDR Rd, [Rn, Rm, LSL #n]
where:
• Rn = Base register
• Rm = Index register
• LSL #n = Logical Shift Left by n bits (scaling)
• Rd = Destination register
Example:
LDR r0, [r1, r2, LSL #2]
Meaning: Loads the data from the memory location whose address is r1 + (r2
× 4) into r0. (i.e., Effective Address = R1 + (R2 << 2))
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Register Indirect with Offset Addressing Mode
(also called pre-indexed addressing mode)
In Register Indirect with Offset Addressing Mode, the effective memory
address is obtained by adding (or subtracting) an offset to the base
register. This addressing mode is also called pre-indexed addressing mode.
Example:
LDR r0, [r1, #4] ; Loads the data from the
memory location whose address is (r1 + 4)
into r0
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Pre-indexed Addressing mode with auto-
indexing
• In this addressing mode, the effective memory address is obtained by
adding (or subtracting) an offset to the base register. The base register is
updated with the new address before the data transfer, and the updated
address is used to access memory. The Pre-indexed Addressing mode
with auto-indexing instruction come with exclamation mark (!).
Example:
LDR r0, [r1, #4]! ;
Meaning:
• Update the base register: r1 = r1 + 4
• Use the updated address to access memory.
• Load the data from memory into r0.
Note: On the ARM this auto-indexing costs no extra time since it is performed
on the processor’s datapath while the data being feached from the
memory.
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Post-indexed Addressing Mode
In Post-indexed Addressing Mode, the data is transferred from the
memory location pointed to by the base register. After the data transfer is
completed, the base register is updated by adding or subtracting the
specified offset. Thus, the memory is accessed first, and then the base
register is updated with the new address.
Example:
LDR r0, [r1], #4
Meaning:
• Load data from address r1
• Then update r1 = r1 + 4
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Program counter (PC)-relative
Addressing Mode
• In this addressing mode, the Program Counter (PC) is used as
the base register.
Example:
LDR r0, [PC, #8] ; Load data from the address PC + 8
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Multiple Register Addressing Mode
• Transfers multiple registers using a single instruction.
Example:
LDMIA R0!, {R1-R4}
Meaning:
Loads multiple registers (R1 to R4) from consecutive memory locations
starting at the address stored in R0, and then updates R0 to the
next memory address.
Explanation
• LDM = Load Multiple
• IA = Increment After
• R0 = Base register
• ! = Write-back (update the base register after the transfer)
• {R1-R4} = Registers to be loaded
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Pipeline
• A pipeline is the mechanism used by a RISC processor to execute
instructions.
• In the pipeline, the processor fetches the next instruction while decoding
and executing the other instruction. This speeds up execution the
execution speed of the processor.
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Pipeline…continue
• The figure shows ARM 7 pipeline,
which has 3 stages-fetch, decode,
and execute. The figure illustrates the
pipeline using a simple example.
• In the first cycle the core fetches the
ADD instruction from memory.
• In the second cycle the core fetches
the SUB instruction and decodes the
ADD instruction.
• In the third cycle, both the SUB and
ADD instructions are moved along
the pipeline. The ADD instruction is
executed, the SUB instruction is
decoded, and the CMP instruction is
fetched. This procedure is called
filling the pipeline.
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Pipeline…continue
• The pipeline divides instruction execution into several stages.
As the pipeline length increases, the amount of work done at
each stage is reduced, which allows the processor to attain a
higher operating frequency. This in turn increases the
performance.
• The system latency also increases because it takes more
cycles to fill the pipeline before the core can execute an
instruction.
• The increased pipeline length also means there can be data
dependency between certain stages.
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Pipeline design for each ARM family
differs
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Pipeline…continue
• The ARM9 core increases the pipeline length to five stages, as shown in
Figure. The ARM9 adds a memory and writeback stage, which allows the
ARM9 to increase the instruction throughput by around 13% compared
with an ARM7.
• The maximum core frequency attainable using an ARM9 is also higher.
• The ARM10 increases the pipeline length still further by adding a sixth
stage, as shown in Figure. The ARM10 can provide 34% more throughput
than an ARM7 processor core, but again at a higher latency cost.
• Code written for the ARM7 will execute on an ARM9 or ARM10.
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ARM9 Pipeline (5 Stages)
• ARM9 divides instruction execution into five stages (Fetch → Decode → Execute
→ Memory → Write Back).
Stage 1: Fetch (F)
• Fetches the instruction from program memory.
• The Program Counter (PC) is updated to point to the next instruction.
Stage 2: Decode (D)
• Decodes the fetched instruction.
• Identifies the operation (ADD, SUB, MOV, etc.).
• Reads the required source registers.
Stage 3: Execute (E)
• The ALU performs the required operation.
• Arithmetic and logical operations are executed.
• Effective addresses for load/store instructions are calculated.
Stage 4: Memory (M)
• Accesses the data memory.
• For LDR, data is read from memory.
• For STR, data is written to memory.
Stage 5: Write Back (WB)
• Writes the result back to the destination register.
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ARM10 Pipeline (6 Stages)
• ARM10 extends ARM9 by dividing execution into an additional
stage. Fetch → Decode → Issue → Execute → Memory → Write
Back
• Stage 1: Fetch (F)
• Fetches the instruction from memory.
• Stage 2: Issue (IS)
• Checks whether operands and execution resources are available.
• Sends the instruction to the appropriate execution unit.
• Stage 3: Decode (D)
• Decodes the instruction.
• Reads source registers
• Stage 4: Execute (E)
• Performs arithmetic, logical, multiplication, and address
calculations.
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ARM10 Pipeline (6 Stages)…continue
• Stage 5: Memory (M)
• Reads from or writes to data memory for load/store instructions.
• Stage 6: Write Back (WB)
• Writes the final result into the destination register.
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Interrupts
• An interrupt is a signal generated by hardware or software that
temporarily stops the normal execution of the processor and transfers
control to a special routine called the Interrupt Service Routine (ISR) to
service the interrupt request. After servicing the interrupt, the processor
returns to the main program.
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Interrupts continue…
When interrupt occurs the ARM processor automatically
performs these operations:
• Completes the execution of the current instruction.
• Switches to IRQ mode.
• The banked registers R13_irq and R14_irq become active,
replacing the User mode R13 and R14.
• Copies the CPSR into SPSR_irq.
• Saves the return address into R14_irq (LR_irq).
• Sets the I (IRQ disable) bit in the CPSR to disable further
IRQ interrupts.
• Loads the PC with the IRQ vector address (0x00000018)
and begins executing the Interrupt Service Routine (ISR).
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Interrupts continue…
• There are two interrupt request levels available on the ARM processor
core—interrupt request (IRQ) and fast interrupt request (FIQ).
• The cpsr has two interrupt mask bits, 7 and 6 (or I and F ), which control
the masking of IRQ and FIQ, respectively. The I bit masks IRQ when set to
binary 1, and similarly the F bit masks FIQ when set to binary 1.
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ARM processor interrupts and its
vector table
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ARM processor interrupts and its
vector table
Reset vector is the location of the first instruction executed by the processor when power
is applied. This instruction branches to the initialization code.
• Undefined instruction vector is used when the processor cannot decode an instruction.
• Software interrupt vector is called when you execute a SWI instruction. The SWI
instruction is frequently used as the mechanism to invoke an operating system routine.
• Prefetch abort vector occurs when the processor attempts to fetch an instruction from an
address without the correct access permissions. The actual abort occurs in the decode
stage.
• Data abort vector is similar to a prefetch abort but is raised when an instruction attempts
• to access data memory without the correct access permissions.
• Interrupt request vector is used by external hardware to interrupt the normal execution
flow of the processor. It can only be raised if IRQs are not masked in the cpsr.
• Fast interrupt request vector is similar to the interrupt request but is reserved for
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hardware requiring faster response times. It can only be raised if FIQs are not masked in the
Cpsr register
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Core Extensions
Some ARM processors have core extensions
features.
• There are three hardware extensions
(1) Cache and tightly coupled memory
(2) Memory management
(3) Coprocessor interface
• The core extensions improve performance, manage
resources, and provide extra functionality and are
designed to provide flexibility in handling particular
applications.
• Each ARM family has different extensions available.
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Cache and Tightly Coupled Memory
• Cache is a block of fast memory placed between main
memory and the core. It allows for more efficient fetches
from some memory types.
• With a cache the processor core can run for the majority of
the time without having to wait for data from slow external
memory.
• Most ARM-based embedded systems use a single-level cache
internal to the processor.
• Of course, many small embedded systems do not require the
performance gains that a cache brings
54
Cache and Tightly Coupled
Memory…continue
• ARM has two forms of
cache. The first is found
attached to the Von
Neumann–style cores.
It combines both data
and instruction into a
single unified cache
(see figure).
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Cache and Tightly Coupled
Memory…continue
• The second form of cache is
attached to the Harvard-style
cores. It has separate caches for
data and instruction.
• A cache provides an overall
increase in performance but at
the expense of unpredictable
execution time.
• But for real-time systems it is
paramount that code execution
is deterministic the time taken
for loading and storing
instructions or data must be
predictable.
• This is achieved using a form
of memory called tightly coupled
memory (TCM).
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Cache and Tightly Coupled
Memory…continue
• TCM is fast SRAM located
close to the core and
guarantees the clock cycles
required to fetch instructions
or data—critical for real-time
algorithms requiring
deterministic behavior.
• By combining both
technologies, ARM processors
can have both improved
performance and predictable
real-time response. Figure
shows an example core with a
combination of caches and
TCMs.
57
Memory Management
• Embedded systems often use multiple memory devices. It is usually
necessary to have a method to help organize these devices and protect
the system from applications trying to make inappropriate accesses to
hardware. This is achieved with the assistance of memory management
hardware.
• ARM cores have three different types of memory management
hardware—no extensions providing no protection, a memory protection
unit (MPU) providing limited protection, and a memory management unit
(MMU) providing full protection.
• Non-protected memory is fixed and provides very little flexibility. It is
normally used for small, simple embedded systems that require no
protection from rogue applications.
58
Memory Management…continue
• Memory protection units (MPUs) employ a
simple system that uses a limited number of
memory regions. These regions are controlled
with a set of special coprocessor registers, and
each region is defined with specific access
permissions.
• This type of memory management is used for
systems that require memory protection but
don’t have a complex memory map.
59
Memory management continue…
Memory management unit (MMU):
MMUs are the most comprehensive memory
management hardware available on the
ARM.
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Coprocessors
• Coprocessors can be attached to the ARM processor. A coprocessor extends the
processing features of a core by extending the instruction set or by providing
configuration registers.
• More than one coprocessor can be added to the ARM core via the coprocessor
interface.
• The coprocessor can be accessed through a group of dedicated ARM instructions
that provide a load-store type interface.
• The ARM processor uses coprocessor registers to control the cache, TCMs, and
memory management.
• The coprocessor can also extend the instruction set by providing a specialized
group of new instructions.
• These new instructions are processed in the decode stage of the ARM pipeline. If
the decode stage sees a coprocessor instruction, then it offers it to the relevant
coprocessor.
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