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Computer Architecture and Organization
Assignment 2
TYPE OF QUESTION: MCQ/MSQ/Fill in the blanks
Number of questions: 10 Total mark: 10 x 1 = 10
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1. How many hexadecimal digits are required to represent a 32-bit binary number?
a. 4
b. 8
c. 16
d. 32
Correct Answer: b
Explanation:
1 hexadecimal digit = 4 bits
32/4=8
Thus, 8 hexadecimal digits are required.
2. The number (101.0101111)2 in hexadecimal notation is:
a. 5.5EH
b. [Link]
c. A.5EH
d. 5.7EH
Correct Answer: a.
Explanation:
Integer part: 101→ 0101=5
Fraction: 0101111→ 0101 1110
(add trailing zero) 0101=5,1110=E
Result: (5.5E)16
3. Using n bits the maximum and minimum numbers that can be represented in 2’s
complement is:
a. +(2n-1 - 1) and -(2n-1)
b. +(2n-1 - 1) and -(2n-1 - 1)
c. +(2n + 1) and -(2n - 1)
d. +(2n-1 - 1) and -(2n-1 + 1)
Correct Answer: a.
Explanation: The maximum numbers that can be represented in 2’s complement for an n
bit number is +(2n-1 - 1) and the minimum is –(2n-1)
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4. Which addressing mode requires two memory accesses to obtain the operand value?
a. Direct addressing
b. Register addressing
c. Immediate addressing
d. Indirect addressing
Correct Answer: d
Explanation:
Indirect addressing works as:
Access memory location containing pointer.
Access the actual operand using that pointer.
Therefore, two memory accesses are required.
5. Registers R1 and R2 contain values 300 and 1200 respectively in decimal, and the word
length of the processor is 32 bits. The effective address of the memory operand in
decimal for the instruction “LOAD R1, 1050(R2) will be ______________.
a. 1050
b. 1200
c. 2250
d. 2550
Correct Answer: c
Explanation:
This is indexed addressing.
EA=R2+1050=2250
Then: R1=Mem[2250]
6. Which feature contributes most directly to the faster instruction execution typically
observed in RISC processors?
a. Complex instructions performing multiple operations
b. Simple instructions with uniform execution time
c. Large number of addressing modes
d. Microprogrammed control unit
Correct Answer: b
Explanation: RISC processors use simple, fixed-length instructions that can often be
executed in a single clock cycle, enabling efficient pipelining and faster execution.
7. For a processor based on a 2-address instruction format, each address field may specify:
(S1) A memory operand
(S2) A processor register
(S3) An immediate constant data
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a. Either S1 or S2
b. S1 only
c. S2 only
d. All of S1, S2 and S3
Correct Answer: a
Explanation: In a 2-address instruction format, address fields are used to identify the
locations of operands. These locations may be (i) A memory location or (ii) A processor
register.
Immediate constants are usually stored in a separate immediate field and are not referred
to as addresses.
8. Which of the following statements regarding the MIPS32 register set is false?
a. R0 is hard-wired to the value zero.
b. R31 is used to store the return address during a function call.
c. Any general-purpose register can be used as an index register.
d. MIPS32 has a dedicated index register IX.
Correct Answer: d
Explanation: R0 always contains zero. R31 stores the return address for instructions such
as JAL. Any general-purpose register can be used as an index register. MIPS32 does not
have a dedicated index register (IX).
Therefore, statement (d) is false.
9. In MIPS instruction BLT $S1,$S2,Label means:
a. If $S1 is less than $S2 then do not branch to location Label
b. If $S1 is not less than $S2 then branch to location Label
c. If $S2 is less than $S1 then branch to location Label
d. If $S1 is less than $S2 then branch to location Label
Correct Answer: d.
Explanation: BLT means Branch Less Than. If $S1 is less than $S2 then branch to location
Label.
10. A MIPS32 processor fetches 32-bit words from memory. Which of the following
addresses can be used to store a word so that it can be fetched in a single memory access?
a. 001AH
b. 001CH
c. 001DH
d. 001EH
Correct Answer: b
Explanation:
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A 32-bit word occupies 4 bytes.
Therefore, a word must start at an address divisible by 4:
001CH = (28)10, and
28 mod 4 = 0
Hence, the word is properly aligned and can be fetched in one access.
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