VT

MODULE 2
Lithography
1. Explain the complete photolithography process.
2. Discuss the basic principles of optical lithography.
3. Explain positive and negative photoresists.
4. Compare positive and negative photoresists.
5. Explain photoresist processing steps.
6. Discuss light sources used in lithography.
7. Explain contact, proximity and projection printing.
8. Explain mask preparation and mask engineering.
9. Discuss Optical Proximity Correction (OPC).
10. Explain Phase Shift Mask (PSM).

Oxidation
1. Explain thermal oxidation process.
2. Compare dry oxidation and wet oxidation.
3. Explain silicon oxidation mechanism.
4. Derive the Deal-Grove oxidation model.
5. Explain linear and parabolic oxidation regions.
6. Discuss oxidation kinetics.
7. Explain Si-SiO₂ interface properties.
8. Explain defects produced during oxidation.
9. Explain oxidation furnaces with neat diagrams.
10. Compare oxidation techniques used in modern CMOS.
1. Explain the Complete Photolithography Process
Answer
Photolithography is the process used to transfer circuit patterns from a mask onto a silicon wafer. It is
the most important patterning technique in VLSI fabrication.
Steps in Photolithography
1. Wafer Cleaning
• Silicon wafer is cleaned to remove dust, organic materials, and contaminants.
• Ensures good adhesion of photoresist.
2. Oxide/Film Formation
• A thin layer of SiO₂ or other material is deposited or grown on the wafer.
• This layer will be patterned.
3. Photoresist Coating
• A light-sensitive material called photoresist is spin-coated on the wafer.
• Produces a uniform thin film.
4. Soft Bake (Pre-Bake)
• Wafer is heated to remove solvents from the photoresist.
• Improves adhesion and uniformity.
5. Mask Alignment
• Photomask containing circuit patterns is aligned accurately with the wafer.
6. UV Exposure
• Ultraviolet light is passed through the mask.
• Exposed regions of photoresist undergo chemical changes.
7. Development
• Developer solution removes selected portions of photoresist.
• Pattern appears on the wafer surface.
8. Hard Bake
• Further heating strengthens the remaining photoresist.
• Improves resistance to etching.
9. Etching
• Exposed oxide or film regions are removed using wet or dry etching.
• Pattern is transferred onto the underlying layer.
10. Photoresist Stripping
• Remaining photoresist is removed.
• Patterned layer remains on the wafer.
Advantages
• High precision pattern transfer.
• Suitable for mass production.
• Enables fabrication of very small devices.
Conclusion
Photolithography transfers IC patterns from a mask to a wafer through coating, exposure, development,
etching, and resist removal, making it a fundamental process in VLSI manufacturing.

2. Discuss the Basic Principles of Optical Lithography

Answer
Optical lithography is a pattern transfer technique in which light is used to transfer geometric patterns
from a photomask onto a photoresist-coated silicon wafer. It is the most widely used lithography
method in VLSI fabrication.
Basic Principle
The process is based on the interaction of light with a photosensitive material (photoresist). When
ultraviolet (UV) light passes through a mask, it exposes selected regions of the photoresist. After
development, the exposed or unexposed regions are removed, creating the desired pattern.
Working Principle
1. Light Source
• UV light is used as the exposure source.
• Common wavelengths: 436 nm (G-line), 365 nm (I-line), 248 nm (KrF), and 193 nm (ArF).
2. Photomask
• Contains transparent and opaque regions representing circuit patterns.
• Controls where light reaches the wafer.
3. Photoresist Layer
• Applied uniformly on the wafer surface.
• Undergoes chemical changes when exposed to light.
4. Exposure Process
• Light passes through transparent mask regions.
• Pattern is projected onto the photoresist.
5. Development
• Developer removes selected portions of photoresist.
• Produces the required pattern.
6. Pattern Transfer
• The developed resist acts as a mask during etching or implantation.
 • Pattern is transferred to the underlying layer.
Resolution of Optical Lithography
Resolution determines the minimum feature size that can be printed.
𝑘1 𝜆
𝑅=
𝑁𝐴
Where:
• R = Resolution
• λ = Wavelength of light
• NA = Numerical Aperture
• k₁ = Process constant
Smaller wavelength and higher NA improve resolution.
Advantages
• High throughput.
• Accurate pattern transfer.
• Suitable for large-scale IC manufacturing.
• Cost-effective for mass production.
Limitations
• Diffraction limits resolution.
• Complex alignment required.
• Difficult to print extremely small features without enhancement techniques.

3. Explain Positive and Negative Photoresists

Introduction
Photoresist is a light-sensitive material used in photolithography to transfer patterns from a mask onto
a silicon wafer. Based on their reaction to UV light, photoresists are classified as positive and negative
photoresists.
Positive Photoresist
• In a positive photoresist, the regions exposed to UV light become more soluble in the
developer solution.
• During development, the exposed portions are removed while the unexposed regions remain on
the wafer.
• The final resist pattern is the same as the mask pattern.
Advantages
• High resolution and accuracy.
• Better linewidth control.
• Suitable for submicron VLSI fabrication.
Disadvantages
• Lower adhesion to the wafer.
• More expensive than negative resist.
Examples
• Novolac resin with Diazonaphthoquinone (DNQ).
• Chemically Amplified Resists (CAR).
Negative Photoresist
• In a negative photoresist, the exposed regions undergo polymerization or cross-linking and
become insoluble.
• During development, the unexposed portions are removed while the exposed portions remain.
• The final resist pattern is the reverse of the mask pattern.
Advantages
• Excellent adhesion.
• High resistance to chemical etching.
• Lower cost.
Disadvantages
• Lower resolution.
• Pattern distortion due to swelling.
Examples
• SU-8 Photoresist.
• Polyisoprene-based resists.
Conclusion
Positive photoresists provide higher resolution and are widely used in modern VLSI fabrication,
whereas negative photoresists offer better adhesion and etch resistance for specific applications.

4. Compare Positive and Negative Photoresists

Parameter Positive Photoresist Negative Photoresist

Reaction to UV Light Becomes soluble Becomes insoluble

Development Exposed area removed Unexposed area removed

Pattern Obtained Same as mask Reverse of mask

Resolution High Moderate

Linewidth Control Excellent Poor

Adhesion Lower Better

Parameter Positive Photoresist Negative Photoresist

Etch Resistance Moderate High

Cost Higher Lower

Swelling Effect Minimal More

Applications Advanced VLSI, IC fabrication MEMS, thick-film applications

Conclusion
Positive resists are preferred in modern VLSI due to superior resolution, while negative resists are used
where strong adhesion and etch resistance are required.

5. Explain Photoresist Processing Steps

Introduction
Photoresist processing is the sequence of operations used to transfer a circuit pattern onto a wafer
during photolithography.
Steps
1. Wafer Cleaning
• Remove dust, grease, moisture, and contaminants.
• Ensures good adhesion of photoresist.
2. Adhesion Promotion
• HMDS (Hexamethyldisilazane) is applied.
• Improves photoresist bonding to the wafer.
3. Photoresist Coating
• Photoresist is deposited using spin coating.
• Produces a uniform thin film.
4. Soft Bake (Pre-bake)
• Removes excess solvents.
• Improves resist uniformity and adhesion.
5. Mask Alignment and Exposure
• Wafer is aligned with the photomask.
• UV light exposes selected regions.
6. Post Exposure Bake (PEB)
• Reduces standing-wave effects.
• Improves image quality.
7. Development
 • Developer removes either exposed or unexposed regions depending on resist type.
• Pattern becomes visible.
8. Hard Bake
• Increases mechanical strength.
• Improves resistance to etching.
9. Etching
• Transfers the resist pattern to the underlying layer.
10. Resist Stripping
• Remaining photoresist is removed after etching.
• Leaves the final patterned wafer.
Conclusion
Photoresist processing ensures accurate transfer of mask patterns onto the wafer and is a critical step in
IC fabrication.

6. Discuss Light Sources Used in Lithography

Introduction
Light sources provide the radiation required to expose photoresists during lithography. Shorter
wavelengths allow smaller feature sizes and higher resolution.
Types of Light Sources
1. Mercury Vapor Lamp
• Traditional UV source.
• Common wavelengths:
o g-line = 436 nm
o h-line = 405 nm
o i-line = 365 nm
• Used in conventional lithography.
2. Excimer Lasers
• Produce deep ultraviolet (DUV) radiation.
KrF Laser
• Wavelength: 248 nm
• Used for submicron fabrication.
ArF Laser
• Wavelength: 193 nm
• Used for advanced CMOS technology.
F₂ Laser
• Wavelength: 157 nm
• Limited commercial use.
3. Extreme Ultraviolet (EUV) Source
• Wavelength: 13.5 nm.
• Uses laser-produced plasma.
• Enables fabrication below 10 nm technology nodes.
4. X-ray Source
• Very short wavelength.
• Extremely high resolution.
• Expensive and complex.
5. Electron Beam Source
• Uses focused electron beams.
• No mask required.
• Mainly used for mask fabrication and research.
Advantages of Short Wavelength Sources
• Improved resolution.
• Reduced diffraction effects.
• Higher packing density.
Conclusion
Modern VLSI fabrication mainly uses ArF and EUV sources because they provide the high resolution
required for nanoscale devices.
7. Explain Contact, Proximity and Projection Printing
1. Contact Printing
• Mask directly touches the wafer surface during exposure.
Advantages
• Simple and inexpensive.
• High light intensity.
Disadvantages
• Mask damage due to contact.
• Particle contamination.
Resolution
• About 1 µm.
2. Proximity Printing
 • Small gap (10–50 µm) between mask and wafer.
Advantages
• Less mask wear.
• Reduced contamination.
Disadvantages
• Diffraction effects reduce resolution.
Resolution
• Around 2–4 µm.
3. Projection Printing
• Uses lenses to project the mask image onto the wafer.
• No physical contact between mask and wafer.
Advantages
• Excellent resolution.
• High throughput.
• Suitable for VLSI and ULSI fabrication.
Disadvantages
• Expensive optical system.
Resolution
• Submicron and nanometer range.
Comparison Table

Feature Contact Proximity Projection

Mask-Wafer Gap 0 10–50 µm No Contact

Resolution High Medium Very High

Mask Damage High Low None

Cost Low Medium High

Application Simple ICs Medium Density ICs Modern VLSI

Conclusion
Projection printing is the most widely used lithography technique in modern semiconductor
manufacturing due to its high resolution and reliability.

8. Explain Mask Preparation and Mask Engineering

Introduction
A photomask contains the circuit pattern that is transferred onto the wafer during lithography.
Mask Preparation Steps
1. Circuit layout design using CAD tools.
2. Pattern generation using electron-beam writing.
3. Chrome deposition on quartz substrate.
4. Resist coating on chrome layer.
5. Pattern exposure and development.
6. Chrome etching to form the mask pattern.
7. Inspection and defect repair.
8. Final cleaning and certification.
Mask Engineering
Mask engineering involves improving mask performance to achieve accurate pattern transfer.
Techniques
• Optical Proximity Correction (OPC)
• Phase Shift Masks (PSM)
• Resolution Enhancement Techniques (RET)
• Sub-resolution assist features (SRAF)
Importance
• Improves pattern fidelity.
• Reduces lithographic errors.
• Enables smaller feature fabrication.
Conclusion
Mask preparation and engineering are essential for achieving high-resolution and defect-free IC
manufacturing.

9. Discuss Optical Proximity Correction (OPC)

Introduction
Optical Proximity Correction (OPC) is a resolution enhancement technique used to compensate for
distortions caused by diffraction and process effects during lithography.
Need for OPC
• Printed features differ from designed features.
• Corners become rounded.
• Line widths vary.
Working Principle
• Modify mask patterns before fabrication.
 • Add small corrective features.
• Compensate for optical distortions.
Types of OPC
1. Rule-Based OPC
• Uses predefined correction rules.
• Faster implementation.
2. Model-Based OPC
• Uses lithography simulation models.
• More accurate.
Advantages
• Improves critical dimension control.
• Enhances pattern accuracy.
• Enables smaller feature sizes.
Applications
• Deep UV lithography.
• Advanced CMOS fabrication.
• Submicron technologies.
Conclusion
OPC significantly improves pattern fidelity and is an essential technique in modern VLSI
manufacturing.

10. Explain Phase Shift Mask (PSM)

Introduction
A Phase Shift Mask (PSM) is an advanced photomask that improves image resolution by controlling
the phase of transmitted light.
Principle
• Adjacent light waves are shifted by 180° (π radians).
• Destructive interference occurs at feature boundaries.
• Produces sharper image edges.
Types of PSM
1. Alternating PSM
• Adjacent openings have opposite phases.
• Highest resolution enhancement.
2. Attenuated PSM
 • Partially transmits light.
• Easier fabrication.
3. Chromeless PSM
• Uses phase differences without opaque chrome patterns.
Advantages
• Improved resolution.
• Better depth of focus.
• Smaller feature fabrication.
• Enhanced linewidth control.
Disadvantages
• Complex mask fabrication.
• Higher cost.
• Difficult design verification.
Applications
• Deep submicron lithography.
• Advanced CMOS processes.
• High-density VLSI circuits.
Conclusion
Phase Shift Masks improve lithographic resolution beyond conventional limits and are widely used in
advanced semiconductor manufacturing.
 OXIDATION
11. Explain Thermal Oxidation Process
Introduction
Thermal oxidation is the process of growing a silicon dioxide (SiO₂) layer on a silicon wafer by
exposing it to oxygen or water vapor at high temperatures (900–1200°C). The oxide layer acts as an
insulator, mask, and gate dielectric in VLSI fabrication.
Process Steps
1. Wafer cleaning to remove contaminants.
2. Loading wafers into oxidation furnace.
3. Heating to oxidation temperature.
4. Introduction of oxidizing ambient:
o Dry Oxidation: O₂
o Wet Oxidation: H₂O vapor
5. Oxide growth on silicon surface.
6. Cooling and unloading.
Chemical Reactions
Dry Oxidation: 𝑆𝑖 + 𝑂2 → 𝑆𝑖𝑂2
Wet Oxidation: 𝑆𝑖 + 2𝐻2 𝑂 → 𝑆𝑖𝑂2 + 2𝐻2
Advantages
• High-quality oxide formation.
• Excellent electrical insulation.
• Good surface passivation.
Applications
• Gate oxide formation.
• Field oxide growth.
• Surface protection.
Conclusion
Thermal oxidation is one of the most important processes in semiconductor manufacturing for
producing high-quality SiO₂ layers.

12. Compare Dry Oxidation and Wet Oxidation

Parameter Dry Oxidation Wet Oxidation

Oxidizing Species O₂ H₂O Vapor

Parameter Dry Oxidation Wet Oxidation

Growth Rate Slow Fast

Oxide Quality Excellent Good

Density High Lower

Dielectric Strength Higher Lower

Process Time Longer Shorter

Oxide Thickness Thin Oxides Thick Oxides

Cost Higher Lower

Application Gate Oxide Field Oxide

Chemical Reactions
Dry: 𝑆𝑖 + 𝑂2 → 𝑆𝑖𝑂2
Wet: 𝑆𝑖 + 2𝐻2 𝑂 → 𝑆𝑖𝑂2 + 2𝐻2
Conclusion
Dry oxidation is used for thin, high-quality gate oxides, while wet oxidation is preferred for rapid
growth of thick oxides.

13. Explain Silicon Oxidation Mechanism

Introduction
Silicon oxidation occurs when oxygen or water molecules react with silicon to form silicon dioxide.
Oxidation Mechanism
Step 1: Transport
Oxidizing species (O₂ or H₂O) reach the oxide surface.
Step 2: Diffusion
Species diffuse through the existing oxide layer.
Step 3: Interface Reaction
Oxidant reacts with silicon at the Si-SiO₂ interface.
Step 4: Oxide Growth
New oxide is formed at the interface.
Key Observation
As oxide thickness increases:
• Diffusion path increases.
• Oxidation rate decreases.
Growth Reaction :𝑆𝑖 + 𝑂2 → 𝑆𝑖𝑂2 or 𝑆𝑖 + 2𝐻2 𝑂 → 𝑆𝑖𝑂2 + 2𝐻2
Conclusion
Silicon oxidation is controlled by oxidant diffusion and interface reaction kinetics.

14. Derive the Deal-Grove Oxidation Model

Introduction
The Deal-Grove model mathematically describes thermal oxide growth on silicon.
Assumptions
1. Oxide grows uniformly.
2. Diffusion through oxide follows Fick's law.
3. Steady-state conditions exist.
Oxidation Rate Equation
The oxide thickness 𝑥𝑜 is given by:
𝑥𝑜2 + 𝐴𝑥𝑜 = 𝐵(𝑡 + 𝜏)
where:
• 𝑥𝑜 = oxide thickness
• 𝑡= oxidation time
• 𝐴= linear rate constant
• 𝐵= parabolic rate constant
• 𝜏= correction factor
Linear Rate Constant:
2𝐷
𝐴=
𝑘𝑠
where
• 𝐷= diffusion coefficient
• 𝑘𝑠 = surface reaction constant
Parabolic Rate Constant
2𝐷𝐶 ∗
𝐵=
𝑁1
where
• 𝐶 ∗ = oxidant concentration
• 𝑁1 = number of oxidant molecules per unit volume
Special Cases
Thin Oxide (Linear Region)
 𝐵
𝑥𝑜 = 𝑡
𝐴
Thick Oxide (Parabolic Region)

𝑥𝑜 = √𝐵𝑡
Conclusion
The Deal-Grove model accurately predicts oxide growth behavior in thermal oxidation.

15. Explain Linear and Parabolic Oxidation Regions

1. Linear Region
Occurs when oxide thickness is small.
Characteristics
• Interface reaction controls growth.
• Oxidant easily reaches silicon surface.
• Growth rate is constant.
Equation
𝐵
𝑥𝑜 = 𝑡
𝐴
Graph
Oxide thickness increases linearly with time.

2. Parabolic Region
Occurs for thick oxides.
Characteristics
• Diffusion controls growth.
• Oxidant must travel through thick oxide.
• Growth rate decreases with time.
Equation

𝑥𝑜 = √𝐵𝑡
or
𝑥𝑜2 = 𝐵𝑡
Graph
Oxide thickness follows a square-root dependence on time.
Conclusion
Thin oxides grow in the linear region, while thick oxides follow parabolic growth behavior.
16. Discuss Oxidation Kinetics
Introduction
Oxidation kinetics describes the rate of oxide growth on silicon.
Factors Affecting Oxidation Rate
1. Temperature
Higher temperature increases oxidation rate.
Arrhenius relation:
𝑅𝑎𝑡𝑒 ∝ 𝑒 −𝐸𝑎/𝑘𝑇
2. Oxidizing Ambient
Wet oxidation is faster than dry oxidation.
3. Crystal Orientation
Growth rate:
(111) > (110) > (100)
4. Pressure
Higher pressure increases growth rate.
5. Doping Concentration
Heavy doping enhances oxidation.
Deal-Grove Kinetics
𝑥𝑜2 + 𝐴𝑥𝑜 = 𝐵(𝑡 + 𝜏)
Conclusion
Oxidation kinetics depends on diffusion and chemical reaction processes and is described by the Deal-
Grove model.

17. Explain Si–SiO₂ Interface Properties

Introduction
The Si–SiO₂ interface is one of the most important interfaces in semiconductor devices.
Properties
1. Excellent Electrical Insulation
SiO₂ has high resistivity and dielectric strength.
2. Low Interface State Density
Provides stable MOS transistor operation.
3. Surface Passivation
Reduces dangling bonds at silicon surface.
4. High Breakdown Strength
Typically:
107 𝑉/𝑐𝑚
5. Good Thermal Stability
Stable at high processing temperatures.
Interface Charges
• Fixed oxide charge
• Mobile ionic charge
• Trapped oxide charge
• Interface trapped charge
Applications
• MOS capacitors
• CMOS transistors
• Gate dielectrics
Conclusion
The excellent quality of the Si–SiO₂ interface is the foundation of modern MOS technology.

18. Explain Defects Produced During Oxidation

Introduction
Oxidation may introduce defects that affect device performance and reliability.
Major Defects
1. Fixed Oxide Charges
Charges trapped near interface.
2. Mobile Ionic Contamination
Na⁺ and K⁺ ions migrate under electric field.
3. Interface Traps
Dangling bonds at Si-SiO₂ interface.
4. Oxide Traps
Charges trapped inside oxide.
5. Stacking Faults
Crystal defects generated during oxidation.
6. Dislocations
Mechanical stress-induced defects.
Effects
• Threshold voltage shift.
 • Increased leakage current.
• Reduced reliability.
• Mobility degradation.
Prevention
• Clean processing environment.
• High-purity oxidation gases.
• Post-oxidation annealing.
Conclusion
Controlling oxidation defects is essential for reliable VLSI device fabrication.
19. Explain Oxidation Furnaces with Neat Diagram
Introduction
An oxidation furnace is used to grow thermal oxide on silicon wafers.
Main Components
1. Quartz reaction tube.
2. Resistance heating coils.
3. Wafer boat.
4. Gas inlet system.
5. Temperature controller.
6. Exhaust outlet.
Simple Diagram
Types
Horizontal Furnace
• Most commonly used.
• Good temperature uniformity.
Vertical Furnace
• Better contamination control.
• Higher throughput.
Advantages
• Uniform oxide growth.
• Batch processing.
• High-quality oxidation.
Conclusion
Oxidation furnaces provide a controlled environment for growing high-quality silicon dioxide layers.
20. Compare Oxidation Techniques Used in Modern CMOS

Oxidizing Growth Oxide

Technique Application
Species Rate Quality

Dry Oxidation O₂ Slow Excellent Gate Oxide

Wet Oxidation H₂O Fast Good Field Oxide

O₂ at high
High Pressure Oxidation Faster Very Good Advanced CMOS
pressure

Rapid Thermal Oxidation

O₂/H₂O Very Fast Excellent Thin Gate Oxides
(RTO)

Low Temperature
Plasma Oxidation Plasma Oxygen Fast Good
Processes

Rapid Thermal Oxidation (RTO)

Advantages
• Very short process time.
• Excellent oxide quality.
• Reduced dopant redistribution.
High Pressure Oxidation
Advantages
• Faster oxidation at lower temperature.
• Improved oxide uniformity.
Conclusion: Modern CMOS technology mainly uses Dry Oxidation, Rapid Thermal Oxidation (RTO), and High-Pressure
Oxidation for achieving high-quality ultra-thin gate oxides required in advanced devices.